master-thesis/netpfga/log/compile-2019-07-24-224335-tablesize64-6.4

+ date
Mit Jul 24 22:43:35 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
+ make
make -C src/ clean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
make -C testdata/ clean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
rm -rf nf_sume_sdnet_ip/
rm -f 
rm -f sw/config_tables.c
make -C src/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
actions_egress.p4(52): warning: Table v6_networks is not used; removing
table v6_networks {
      ^^^^^^^^^^^
actions_egress.p4(73): warning: Table v4_networks is not used; removing
table v4_networks {
      ^^^^^^^^^^^
actions_nat64_generic.p4(178): warning: Table nat46 is not used; removing
    table nat46 {
          ^^^^^
minip4_solution.p4(38): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates
    out metadata meta,
                 ^^^^
minip4_solution.p4(35)
parser RealParser(
       ^^^^^^^^^^
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
make -C testdata/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
./gen_testdata.py
Applying pkt on nf0 at 1: 
Applying pkt on nf1 at 2: 
Applying pkt on nf2 at 3: 
Applying pkt on nf3 at 4: 
nf0_applied times:  [1]
nf1_applied times:  [2]
nf2_applied times:  [3]
nf3_applied times:  [4]
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
Xilinx SDNet Compiler version 2018.2, build 2342300

Compilation successful
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_externs.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ ./testdata/ ./sw/ --base_address 0x44020000
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_API.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_CLI.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API 
cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg 
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
# The following command only applies if running P4_SWITCH Questa Simulation with Ubuntu
sed -i 's/vsim/vsim \-ldflags \"\-B\/usr\/lib\/x86\_64\-linux-gnu\"/g' nf_sume_sdnet_ip/SimpleSumeSwitch/questa.bash
# modify the P4_SWITCH_tb so that it writes the table configuration writes to a file
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/modify_P4_SWITCH_tb.py nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv
# Fix introduced for SDNet 2017.4
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
# Fix introduced for SDNet 2018.2
sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
cp testdata/*.axi nf_sume_sdnet_ip/SimpleSumeSwitch/
+ date
Mit Jul 24 22:43:41 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch
+ ./vivado_sim.bash
+ find -name '*.v' -o -name '*.vp' -o -name '*.sv'
+ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv %
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4_compute_realmain_lookup_table_0_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_4_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_user_metadata_table_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_TopPipe_fl_realmain_src_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_TopPipe_fl_realmain_dst_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_version
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ihl
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_diff_serv
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ecn
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_totalLen
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_identification
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_flags
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_fragOffset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_ttl
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_protocol
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_src_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv4_dst_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ethernet_ethertype
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_user_metadata_chk_ipv4
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_p_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_static_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_3
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_3
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_3_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_3_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_4
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec_compute_TopPipe_fl_realmain_tmp_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_TopPipe_fl_realmain_tmp_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_5
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2_compute_realmain_lookup_table_0_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_2_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_6
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1_compute_realmain_lookup_table_0_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_1_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_7
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_p_ipv4_protocol
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_user_metadata_switch_task
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_user_metadata_chk_icmp
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp6_na_ns_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_p_icmp6_option_link_layer_addr_isValid
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_nat64_icmp6_generic_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_8
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_9
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_p_icmp_type
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_p_icmp_code
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_1_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_10
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_realmain_lookup_table_0_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_11
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_p_icmp_type
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_p_icmp_code
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_realmain_lookup_table_0_req_lookup_request_key
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_local_state_id
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_2_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_12
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat64_0_tuple_in_request.v" into library work
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_nat64_0_tuple_in_request
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat64_0_tuple_in_request.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request.v" into library work
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_1_t.HDL/TopPipe_lvl_1_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_lookup_table_0_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_lookup_table_0_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_lookup_table_0_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_do_nothing_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_do_nothing_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_do_nothing_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_all_ports_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_all_ports_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_all_ports_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_all_ports_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_port1_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_port1_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_port1_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_send_to_port1_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_TopPipe_fl_realmain_temp_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_p_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_p_ethernet_src_addr
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_swap_eth_addresses_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_3
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_sink
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_sink_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_sink_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_1_t.HDL/TopPipe_lvl_1_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_realmain_nat64_0_req_lookup_request_key_0
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp" into library work
ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library work
INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v" into library work
INFO: [VRFC 10-311] analyzing module TB_System_Stim
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" into library work
INFO: [VRFC 10-311] analyzing module Check
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" into library work
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch_tb
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_3_sec
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_3_sec_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_3_sec_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_dst_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_src_addr
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_ethertype
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopDeparser_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_line
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library work
INFO: [VRFC 10-311] analyzing module S_RESETTER_control
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library work
INFO: [VRFC 10-311] analyzing module TopParser_t_Engine
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter
INFO: [VRFC 10-311] analyzing module TopParser_t_start
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_tcp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_udp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_cpu_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_na_ns_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_arp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dma_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf3_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf2_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf1_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf0_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_send_dig_to_cpu
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_drop
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_pkt_len
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_ethertype
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_digest_data_1_unused
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_ethertype
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_version
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ihl
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_diff_serv
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ecn
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_totalLen
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_identification
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_flags
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_fragOffset
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ttl
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_protocol
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_version
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_traffic_class
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_flow_label
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_payload_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_next_header
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_hop_limit
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_src_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_dst_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_seqNo
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ackNo
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_data_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_res
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_cwr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ece
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_urg
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ack
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_psh
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_rst
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_syn
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_fin
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_window
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_urgentPtr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_payload_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_code
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_task
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_ingress_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_ethertype
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_table_id
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_code
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_checksum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_router
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_solicitated
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_override
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_reserved
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_target_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_ll_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_isValid
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_hw_type
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_protocol
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_hw_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_protocol_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_opcode
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_src_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_src_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_dst_mac_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_dst_ipv4_addr
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_ingress_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_task
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_switch_task
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp6_na_ns
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_ipv4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_udp_v4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_udp_v6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_tcp_v4
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_tcp_v6
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_length_without_ip_header
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_cast_length
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_v4sum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_v6sum
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_headerdiff
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_table_id
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_digest_data_unused
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_dma_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf3_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf2_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf1_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf0_q_size
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_send_dig_to_cpu
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_drop
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_dst_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_src_port
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_pkt_len
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_reject
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopParser_t_accept
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library work
INFO: [VRFC 10-311] analyzing module TopParser_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library work
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library work
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/realmain_lookup_table_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/realmain_lookup_table_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Wrap
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_IntTop
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Lookup
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Hash_Lookup
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_RamR1RW1
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Cam
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Update
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Hash_Update
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Randmod4
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Randmod4_Rnd
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Randmod5
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_Randmod5_Rnd
INFO: [VRFC 10-311] analyzing module realmain_lookup_table_0_t_csr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library work
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_memory_base
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/realmain_nat64_0_t.v" into library work
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_cdc.sv" into library work
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/realmain_nat64_0_t.vp" into library work
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Wrap
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_IntTop
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Lookup
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Hash_Lookup
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_RamR1RW1
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Cam
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Update
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Hash_Update
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Randmod4
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Randmod4_Rnd
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Randmod5
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_Randmod5_Rnd
INFO: [VRFC 10-311] analyzing module realmain_nat64_0_t_csr
+ true
+ mkdir -p xsim.dir/xsc
+ find -name '*.c'
+ xargs /opt/Xilinx/Vivado/2018.2/bin/xsc -mt off -v 1
Turned off multi-threading.
Running compilation flow
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc  -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/    -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc  -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/    -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/user.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -DXILINX_SIMULATOR
./Testbench/user.c: In function ‘register_write_control’:
./Testbench/user.c:39:5: warning: implicit declaration of function ‘SV_write_control’ [-Wimplicit-function-declaration]
     SV_write_control(&sv_addr, &sv_data);
     ^~~~~~~~~~~~~~~~
./Testbench/user.c: In function ‘register_read_control’:
./Testbench/user.c:53:5: warning: implicit declaration of function ‘SV_read_control’ [-Wimplicit-function-declaration]
     SV_read_control(&sv_addr, &sv_data);
     ^~~~~~~~~~~~~~~
./Testbench/user.c: In function ‘CAM_Init’:
./Testbench/user.c:101:76: warning: passing argument 9 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
     if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
                                                                            ^~~~~~~~~~~~~~
In file included from ./Testbench/user.c:7:0:
./Testbench/CAM.h:169:5: note: expected ‘void (*)(addr_t,  uint32_t) {aka void (*)(long long unsigned int,  unsigned int)}’ but argument is of type ‘void (*)(uint32_t,  uint32_t) {aka void (*)(unsigned int,  unsigned int)}’
 int CAM_Init_ValidateContext(
     ^~~~~~~~~~~~~~~~~~~~~~~~
./Testbench/user.c:101:92: warning: passing argument 10 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
     if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
                                                                                            ^~~~~~~~~~~~~
In file included from ./Testbench/user.c:7:0:
./Testbench/CAM.h:169:5: note: expected ‘uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)}’ but argument is of type ‘uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}’
 int CAM_Init_ValidateContext(
     ^~~~~~~~~~~~~~~~~~~~~~~~
Done compilation
Linking with command:
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -shared  -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o"     -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel  -lrdi_xsim_systemc  -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ 

Running command : /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -shared  -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o"     -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel  -lrdi_xsim_systemc  -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ 
Done linking: "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so"
+ /opt/Xilinx/Vivado/2018.2/bin/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl 
Multi-threading is on. Using 6 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module work.S_RESETTER_line
Compiling module work.S_RESETTER_lookup
Compiling module work.S_RESETTER_control
Compiling module work.TopParser_t_EngineStage_0_ErrorC...
Compiling module work.TopParser_t_EngineStage_0_Extrac...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_TopPar...
Compiling module work.TopParser_t_start_compute_p_ethe...
Compiling module work.TopParser_t_start_compute_p_ethe...
Compiling module work.TopParser_t_start_compute_p_ethe...
Compiling module work.TopParser_t_start_compute_p_ethe...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv4...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_ipv6...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_tcp_...
Compiling module work.TopParser_t_start_compute_p_udp_...
Compiling module work.TopParser_t_start_compute_p_udp_...
Compiling module work.TopParser_t_start_compute_p_udp_...
Compiling module work.TopParser_t_start_compute_p_udp_...
Compiling module work.TopParser_t_start_compute_p_udp_...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_cpu_...
Compiling module work.TopParser_t_start_compute_p_cpu_...
Compiling module work.TopParser_t_start_compute_p_cpu_...
Compiling module work.TopParser_t_start_compute_p_cpu_...
Compiling module work.TopParser_t_start_compute_p_cpu_...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_icmp...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_p_arp_...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_user_m...
Compiling module work.TopParser_t_start_compute_digest...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_sume_m...
Compiling module work.TopParser_t_start_compute_contro...
Compiling module work.TopParser_t_start_compute_contro...
Compiling module work.TopParser_t_start
Compiling module work.TopParser_t_reject_compute_contr...
Compiling module work.TopParser_t_reject_compute_contr...
Compiling module work.TopParser_t_reject
Compiling module work.TopParser_t_EngineStage_0_TupleF...
Compiling module work.TopParser_t_EngineStage_0
Compiling module work.TopParser_t_EngineStage_1_ErrorC...
Compiling module work.TopParser_t_accept_compute_contr...
Compiling module work.TopParser_t_accept_compute_contr...
Compiling module work.TopParser_t_accept
Compiling module work.TopParser_t_EngineStage_1
Compiling module work.TopParser_t_Engine
Compiling module work.TopParser_t
Compiling module work.TopPipe_lvl_t_setup_compute_real...
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
Compiling module work.TopPipe_lvl_t_setup
Compiling module work.TopPipe_lvl_t_EngineStage_0
Compiling module work.TopPipe_lvl_t_Engine
Compiling module work.TopPipe_lvl_t
Compiling module work.realmain_nat64_0_t_Hash_Lookup
Compiling module work.xpm_memory_base(MEMORY_SIZE=7024...
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=70...
Compiling module work.realmain_nat64_0_t_RamR1RW1
Compiling module work.realmain_nat64_0_t_Cam
Compiling module work.realmain_nat64_0_t_Lookup
Compiling module work.realmain_nat64_0_t_Hash_Update
Compiling module work.realmain_nat64_0_t_Randmod4_Rnd
Compiling module work.realmain_nat64_0_t_Randmod4
Compiling module work.realmain_nat64_0_t_Randmod5_Rnd
Compiling module work.realmain_nat64_0_t_Randmod5
Compiling module work.realmain_nat64_0_t_Update
Compiling module work.realmain_nat64_0_t_IntTop
Compiling module work.realmain_nat64_0_t_Wrap
Compiling module work.realmain_nat64_0_t_csr
Compiling module work.realmain_nat64_0_t
Compiling module work.TopPipe_lvl_0_t_condition_sec_4_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_4_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_4_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_4_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_4
Compiling module work.TopPipe_lvl_0_t_EngineStage_0
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_0...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_0...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_0...
Compiling module work.TopPipe_lvl_0_t_EngineStage_1
Compiling module work.TopPipe_lvl_0_t_NoAction_0_sec_c...
Compiling module work.TopPipe_lvl_0_t_NoAction_0_sec_c...
Compiling module work.TopPipe_lvl_0_t_NoAction_0_sec
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
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Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_control...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_s...
Compiling module work.TopPipe_lvl_0_t_EngineStage_2
Compiling module work.TopPipe_lvl_0_t_condition_sec_3_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_3_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_3
Compiling module work.TopPipe_lvl_0_t_EngineStage_3
Compiling module work.TopPipe_lvl_0_t_act_0_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_0_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_0_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_0_sec
Compiling module work.TopPipe_lvl_0_t_act_sec_compute_...
Compiling module work.TopPipe_lvl_0_t_act_sec_compute_...
Compiling module work.TopPipe_lvl_0_t_act_sec_compute_...
Compiling module work.TopPipe_lvl_0_t_act_sec
Compiling module work.TopPipe_lvl_0_t_EngineStage_4
Compiling module work.TopPipe_lvl_0_t_condition_sec_2_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_2_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_2_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_2_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_2
Compiling module work.TopPipe_lvl_0_t_EngineStage_5
Compiling module work.TopPipe_lvl_0_t_condition_sec_1_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_1_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_1_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_1_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_1
Compiling module work.TopPipe_lvl_0_t_EngineStage_6
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_realmain_nat64_i...
Compiling module work.TopPipe_lvl_0_t_EngineStage_7
Compiling module work.TopPipe_lvl_0_t_condition_sec_0_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_0_...
Compiling module work.TopPipe_lvl_0_t_condition_sec_0
Compiling module work.TopPipe_lvl_0_t_EngineStage_8
Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_1_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_1_sec
Compiling module work.TopPipe_lvl_0_t_EngineStage_9
Compiling module work.TopPipe_lvl_0_t_condition_sec_co...
Compiling module work.TopPipe_lvl_0_t_condition_sec_co...
Compiling module work.TopPipe_lvl_0_t_condition_sec_co...
Compiling module work.TopPipe_lvl_0_t_condition_sec_co...
Compiling module work.TopPipe_lvl_0_t_condition_sec
Compiling module work.TopPipe_lvl_0_t_EngineStage_10
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec_comput...
Compiling module work.TopPipe_lvl_0_t_act_2_sec
Compiling module work.TopPipe_lvl_0_t_EngineStage_11
Compiling module work.TopPipe_lvl_0_t_local_end_comput...
Compiling module work.TopPipe_lvl_0_t_local_end_comput...
Compiling module work.TopPipe_lvl_0_t_local_end
Compiling module work.TopPipe_lvl_0_t_EngineStage_12
Compiling module work.TopPipe_lvl_0_t_Engine
Compiling module work.TopPipe_lvl_0_t
Compiling module work.realmain_lookup_table_0_t_Hash_L...
Compiling module work.xpm_memory_base(MEMORY_SIZE=880,...
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=88...
Compiling module work.realmain_lookup_table_0_t_RamR1R...
Compiling module work.realmain_lookup_table_0_t_Cam
Compiling module work.realmain_lookup_table_0_t_Lookup
Compiling module work.realmain_lookup_table_0_t_Hash_U...
Compiling module work.realmain_lookup_table_0_t_Randmo...
Compiling module work.realmain_lookup_table_0_t_Randmo...
Compiling module work.realmain_lookup_table_0_t_Randmo...
Compiling module work.realmain_lookup_table_0_t_Randmo...
Compiling module work.realmain_lookup_table_0_t_Update
Compiling module work.realmain_lookup_table_0_t_IntTop
Compiling module work.realmain_lookup_table_0_t_Wrap
Compiling module work.realmain_lookup_table_0_t_csr
Compiling module work.realmain_lookup_table_0_t
Compiling module work.TopPipe_lvl_1_t_local_start_comp...
Compiling module work.TopPipe_lvl_1_t_local_start_comp...
Compiling module work.TopPipe_lvl_1_t_local_start
Compiling module work.TopPipe_lvl_1_t_EngineStage_0
Compiling module work.TopPipe_lvl_1_t_realmain_lookup_...
Compiling module work.TopPipe_lvl_1_t_realmain_lookup_...
Compiling module work.TopPipe_lvl_1_t_realmain_lookup_...
Compiling module work.TopPipe_lvl_1_t_EngineStage_1
Compiling module work.TopPipe_lvl_1_t_realmain_do_noth...
Compiling module work.TopPipe_lvl_1_t_realmain_do_noth...
Compiling module work.TopPipe_lvl_1_t_realmain_do_noth...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_send_to...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_realmain_swap_et...
Compiling module work.TopPipe_lvl_1_t_EngineStage_2
Compiling module work.TopPipe_lvl_1_t_sink_compute_con...
Compiling module work.TopPipe_lvl_1_t_sink_compute_con...
Compiling module work.TopPipe_lvl_1_t_sink
Compiling module work.TopPipe_lvl_1_t_EngineStage_3
Compiling module work.TopPipe_lvl_1_t_Engine
Compiling module work.TopPipe_lvl_1_t
Compiling module work.TopDeparser_t_EngineStage_0_Erro...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_extract_headers_se...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.xpm_cdc_sync_rst(DEST_SYNC_FF=2,...
Compiling module work.xpm_fifo_rst(COMMON_CLOCK=0)
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Compiling module work.S_SYNCER_for__OUT_
Compiling module work.S_CONTROLLER_SimpleSumeSwitch
Compiling module work.SimpleSumeSwitch
Compiling module work.TB_System_Stim
Compiling module work.Check
Compiling module work.SimpleSumeSwitch_tb
Compiling module work.glbl
Built simulation snapshot work.SimpleSumeSwitch_tb#work.glbl

****** Webtalk v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Wed Jul 24 22:44:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Wed Jul 24 22:44:34 2019...
+ /opt/Xilinx/Vivado/2018.2/bin/xsim --runall SimpleSumeSwitch_tb#work.glbl

****** xsim v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsim_script.tcl
# xsim {work.SimpleSumeSwitch_tb#work.glbl} -autoloadwcfg -runall
Vivado Simulator 2018.2
Time resolution is 1 ps
run -all
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat64_0.realmain_nat64_0_t_Wrap_inst.realmain_nat64_0_t_IntTop_inst.realmain_nat64_0_t_Lookup_inst.realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_373  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat64_0.realmain_nat64_0_t_Wrap_inst.realmain_nat64_0_t_IntTop_inst.realmain_nat64_0_t_Lookup_inst.realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_373  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat64_0.realmain_nat64_0_t_Wrap_inst.realmain_nat64_0_t_IntTop_inst.realmain_nat64_0_t_Lookup_inst.realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_373  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat64_0.realmain_nat64_0_t_Wrap_inst.realmain_nat64_0_t_IntTop_inst.realmain_nat64_0_t_Lookup_inst.realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_373  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_nat64_0.realmain_nat64_0_t_Wrap_inst.realmain_nat64_0_t_IntTop_inst.realmain_nat64_0_t_Lookup_inst.realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_373  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_lookup_table_0.realmain_lookup_table_0_t_Wrap_inst.realmain_lookup_table_0_t_IntTop_inst.realmain_lookup_table_0_t_Lookup_inst.realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_954  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_lookup_table_0.realmain_lookup_table_0_t_Wrap_inst.realmain_lookup_table_0_t_IntTop_inst.realmain_lookup_table_0_t_Lookup_inst.realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_954  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_lookup_table_0.realmain_lookup_table_0_t_Wrap_inst.realmain_lookup_table_0_t_IntTop_inst.realmain_lookup_table_0_t_Lookup_inst.realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_954  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_lookup_table_0.realmain_lookup_table_0_t_Wrap_inst.realmain_lookup_table_0_t_IntTop_inst.realmain_lookup_table_0_t_Lookup_inst.realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_954  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_lookup_table_0.realmain_lookup_table_0_t_Wrap_inst.realmain_lookup_table_0_t_IntTop_inst.realmain_lookup_table_0_t_Lookup_inst.realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_954  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_nat64_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1696  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1786  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.wlrpvy4rsdrfl6s4u7kkyypl3_198.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1875  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.mvz7xkeut076iznclj71pbiykw6_1202.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1905  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.hyrzp6taloqmmwij4f4sj4ghvca_564.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1969  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.j4ljiyl61srd3ect0w0_1048.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2053  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.k6j2b0g89m17enc7130a7tltr1s_699.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1875  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.jx2gwgarhcldkoh6_10.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1905  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.mpjcdkflu7yrzqmbuolk5m3_440.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2234  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.floqxoej5aicutpz7i0zfl3a2yo_1736.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2318  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.ioexwad3y5i2qhphqmb2ken4km02_773.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2402  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.k9vs7qqzhhdv2zey1_659.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1969  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.uaw8hbzp8uthjy28n20bk_2023.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2053  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.t539xkdlyz0yc8oovx06y8hcclnmjtr_2504.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2654  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.dvkcxpj9tgydwxf0uaacewfj1lgs44n_577.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1875  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.xlxy2vk2641yoha3e_1822.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1905  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.osh9yoxxjklf0zptis9c_990.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2841  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.m7o3hoymg8uqcdqizeadzv8k_2122.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2402  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.gghdqjx444zucre728gloe6_277.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3009  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.rqi3coc7d6nfo9vpmtw1osvanvjfag_1667.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2234  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.jmn7mgem3iz1kdmn9sqw93_2107.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1969  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.aup6zkcizv14pimeye6t4q44_717.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2318  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.dnamqnvcoxbq1q8d4ajs2o9r82uvt_186.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3345  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.ooy32m177bv6ya8qd36kkxz9ae9s_566.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2053  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.lah2fef13rfm7lr6x_454.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2654  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.viwe29jpldowrxiyo9oh20jjqtzx6c6_1217.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1875  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.c7982oxn1ft1zx03d0_1883.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1905  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.z20ebgxmlf2wz2spqe_2680.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2841  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.ufi21gd9cod5i8zmbsn_386.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2402  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.z9lcgcecur72ty6e3hwewxm68okrwjkz_836.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3009  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.kmx85e9k8hls511lexi9vcc3n9opnyf_1703.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2234  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.khxyr7u7157o34roo3qky80hlj_1032.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4040  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.akxg1tfymljerus1vpcnepyv8wl7y_170.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1969  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.i4bhqagkugyabg8pt4qtyisoea79s5_80.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2318  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.oifasqvrhgnf3x3oyfx42u_1092.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4292  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.lyq1o92avk5w3720fvrfdo_576.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2053  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.w5y7682mjw2ipu44fcs95o4cqw9j_321.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2654  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.rrx2o92507e60rsejcoaqy_2580.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1875  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.te3fcfez76chzmfek_1821.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1905  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.lkis63w9hmt3fpru78meaacsu_1457.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2234  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.x59vx3wada7a411ba31_2374.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2318  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.of49eycjluhg2js6xdhgiiy1js06gv_1190.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2402  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.onctbgj1uc88lix0_190.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1969  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.nczo24ruhk6u3b1ok20l9jc3z6zpaw_782.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2053  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.mjjip2n5ms3clnld2wphvbc0_2464.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2654  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.la3bvivtp1cnzub8_1029.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5144  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.kty4eu99g0lcln2zjl4dm8w48s9_2303.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1905  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.s487z0rob4coa34tq19uftml_2207.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2402  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.xob1479vc8hxdsk2seqzos5lpnt7wwh_1463.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1969  File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/xpm_memory.sv
[SW] CAM_Init() - start
[SW] CAM_Init() - done
[SW] CAM_EnableDevice() - start
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
[SW] CAM_EnableDevice() - done
[SW] CAM_Init() - start
[SW] CAM_Init() - done
[SW] CAM_EnableDevice() - start
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
[SW] CAM_EnableDevice() - done
[2520658]  INFO: finished packet stimulus file
[3155404]  INFO: packet 1 tuple OK < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
[3155404]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
[3158736]  INFO: packet 1  data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
[3165400]  INFO: packet 2 tuple OK < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001040000 >
[3165400]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
[3168732]  INFO: packet 2  data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
[3175396]  INFO: packet 3 tuple OK < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001100000 >
[3175396]  INFO: packet 3  data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
[3178728]  INFO: packet 3  data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
[3185392]  INFO: packet 4 tuple OK < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001400000 >
[3185392]  INFO: packet 4  data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
[3188724]  INFO: packet 4  data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
[6524056]  INFO: stopping simulation after 1000 idle cycles
[6524056]  INFO: all expected data successfully received
[6524056]  INFO: TEST PASSED
$finish called at time : 6524056 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" Line 207
exit
INFO: [Common 17-206] Exiting xsim at Wed Jul 24 22:44:44 2019...
+ grep ^expected /home/nico/master-thesis/netpfga/log/compile-2019-07-24-224335-tablesize64-6.4
+ sed -e s/.*= <// -e s/.*= (//
+ expected_line=
+ grep ^actual /home/nico/master-thesis/netpfga/log/compile-2019-07-24-224335-tablesize64-6.4
+ sed -e s/.*= <// -e s/.*= (//
+ actual_line=
+ [  !=  ]
+ date
Mit Jul 24 22:44:44 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
+ make config_writes
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata
orig dic: OrderedDict([(0, ('00000020', '00000001')), (1, ('00000020', '00000000')), (2, ('00000120', '00000001')), (3, ('00000120', '00000000'))])
new dic: OrderedDict()
+ date
Mit Jul 24 22:44:44 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
+ make uninstall_sdnet
rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip
+ make install_sdnet
rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip
cp -r nf_sume_sdnet_ip /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/
mkdir /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/hdl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper/
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/tcl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/Makefile /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
make -C /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
rm -rf ip_*  vivado*.* *.xml xgui/ .Xil* *.*~ *.zip 
vivado -mode batch -source nf_sume_sdnet.tcl

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source nf_sume_sdnet.tcl
# set design nf_sume_sdnet
# set top nf_sume_sdnet
# set device xc7vx690t-3-ffg1761
# set proj_dir ./ip_proj
# set ip_version 1.00
# set lib_name NetFPGA
# create_project -name ${design} -force -dir "./${proj_dir}" -part ${device}
# set_property source_mgmt_mode All [current_project]  
# set_property top ${top} [current_fileset]
# set_property ip_repo_paths $::env(SUME_FOLDER)/lib/hw/  [current_fileset]
# update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
# puts "nf_sume_sdnet"
nf_sume_sdnet
# read_verilog "./wrapper/sume_to_sdnet.v"
# read_verilog "./wrapper/nf_sume_sdnet.v"
# read_verilog "./wrapper/changeEndian.v"
# add_files -scan_for_includes ./SimpleSumeSwitch/
# import_files -force
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
# update_compile_order -fileset sources_1
# update_compile_order -fileset sim_1
# ipx::package_project
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/wrapper/changeEndian.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.h'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_cdc.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/xpm_memory.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/dpi.h'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM.h'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM_INST0.h'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request.vp'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat64_0_tuple_in_request.vp'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv'.
INFO: [IP_Flow 19-5169] Module 'nf_sume_sdnet' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'axis_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'S_AXI'.
INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'.
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'S_AXI_ARESETN'.
INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'axis_resetn'.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
ipx::package_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1299.496 ; gain = 19.000 ; free physical = 7253 ; free virtual = 15633
# set_property name ${design} [ipx::current_core]
# set_property library ${lib_name} [ipx::current_core]
# set_property vendor_display_name {NetFPGA} [ipx::current_core]
# set_property company_url {http://www.netfpga.org} [ipx::current_core]
# set_property vendor {NetFPGA} [ipx::current_core]
# set_property supported_families {{virtex7} {Production}} [ipx::current_core]
# set_property taxonomy {{/NetFPGA/Generic}} [ipx::current_core]
# set_property version ${ip_version} [ipx::current_core]
# set_property display_name ${design} [ipx::current_core]
# set_property description ${design} [ipx::current_core]
# ipx::add_user_parameter {C_M_AXIS_DATA_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_M_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {256} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {C_S_AXIS_DATA_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_S_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {256} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {C_M_AXIS_TUSER_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_M_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {128} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {C_S_AXIS_TUSER_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_S_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {128} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {C_S_AXI_DATA_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_S_AXI_DATA_WIDTH} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {32} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {C_S_AXI_ADDR_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {C_S_AXI_ADDR_WIDTH} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {12} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
# ipx::add_user_parameter {SDNET_ADDR_WIDTH} [ipx::current_core]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_resolve_type {user} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property display_name {SDNET_ADDR_WIDTH} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value {11} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]]
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]]
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]]
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]]
# update_ip_catalog -rebuild 
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
# ipx::infer_user_parameters [ipx::current_core]
# ipx::check_integrity [ipx::current_core]
INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
# ipx::save_core [ipx::current_core]
# update_ip_catalog
# close_project
INFO: [Common 17-206] Exiting Vivado at Wed Jul 24 22:45:12 2019...
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
+ date
Mit Jul 24 22:45:12 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default
+ make
rm -f config_writes.py*
rm -f *.pyc
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./ 
+ date
Mit Jul 24 22:45:12 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA
+ ./tools/scripts/nf_test.py sim --major switch --minor default
make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl
# set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
# set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
# set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
# set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
# set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
# set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
# set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
# set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
# set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
# set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
# set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
# set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
# set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
# set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
# set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
# set M00_BASEADDR 0x44000000
# set M00_HIGHADDR 0x44000FFF
# set M00_SIZEADDR 0x1000
# set M01_BASEADDR 0x44010000
# set M01_HIGHADDR 0x44010FFF
# set M01_SIZEADDR 0x1000
# set M02_BASEADDR 0x44020000
# set M02_HIGHADDR 0x44020FFF
# set M02_SIZEADDR 0x1000
# set M03_BASEADDR 0x44030000
# set M03_HIGHADDR 0x44030FFF
# set M03_SIZEADDR 0x1000
# set M04_BASEADDR 0x44040000
# set M04_HIGHADDR 0x44040FFF
# set M04_SIZEADDR 0x1000
# set M05_BASEADDR 0x44050000
# set M05_HIGHADDR 0x44050FFF
# set M05_SIZEADDR 0x1000
# set M06_BASEADDR 0x44060000
# set M06_HIGHADDR 0x44060FFF
# set M06_SIZEADDR 0x1000
# set M07_BASEADDR 0x44070000
# set M07_HIGHADDR 0x44070FFF
# set M07_SIZEADDR 0x1000
# set M08_BASEADDR 0x44080000
# set M08_HIGHADDR 0x44080FFF
# set M08_SIZEADDR 0x1000
# set IDENTIFIER_BASEADDR $M00_BASEADDR
# set IDENTIFIER_HIGHADDR $M00_HIGHADDR
# set IDENTIFIER_SIZEADDR $M00_SIZEADDR
# set INPUT_ARBITER_BASEADDR $M01_BASEADDR
# set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
# set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
# set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
# set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
# set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
# set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
# set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
# set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
# set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
# set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
# set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
# set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
# set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
# set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
# set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
# set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
# set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
# set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
# set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
# set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
# set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
# set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
# set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
INFO: [Common 17-206] Exiting Vivado at Wed Jul 24 22:45:18 2019...
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl	

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl
# set DEF_LIST {
# 	{MICROBLAZE_AXI_IIC 0 0 ""} \
# 	{MICROBLAZE_UARTLITE 0 0 ""} \
# 	{MICROBLAZE_DLMB_BRAM 0 0 ""} \
# 	{MICROBLAZE_ILMB_BRAM 0 0 ""} \
# 	{MICROBLAZE_AXI_INTC 0 0 ""} \
# 	{INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \
# 	{OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \
# 	{OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \
# 	{NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \
# 	{NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
# 	{NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
# 	{NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
# 	{NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \
# 
# 
# }
# set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/
# set target_file $target_path/sume_register_defines.h
# proc write_header { target_file } {
# 
# # creat a blank header file
# # do a fresh rewrite in case the file already exits
# file delete -force $target_file
# open $target_file "w"
# set h_file [open $target_file "w"]
# 
# 
# puts $h_file "//-"
# puts $h_file "// Copyright (c) 2015 University of Cambridge"
# puts $h_file "// All rights reserved."
# puts $h_file "//"
# puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory "
# puts $h_file "// under National Science Foundation under Grant No. CNS-0855268,"
# puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and"
# puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), "
# puts $h_file "// as part of the DARPA MRC research programme."
# puts $h_file "//"
# puts $h_file "// @NETFPGA_LICENSE_HEADER_START@"
# puts $h_file "//"
# puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor"
# puts $h_file "// license agreements.  See the NOTICE file distributed with this work for"
# puts $h_file "// additional information regarding copyright ownership.  NetFPGA licenses this"
# puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the"
# puts $h_file "// \"License\"); you may not use this file except in compliance with the"
# puts $h_file "// License.  You may obtain a copy of the License at:"
# puts $h_file "//"
# puts $h_file "//   http://www.netfpga-cic.org"
# puts $h_file "//"
# puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed"
# puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR"
# puts $h_file "// CONDITIONS OF ANY KIND, either express or implied.  See the License for the"
# puts $h_file "// specific language governing permissions and limitations under the License."
# puts $h_file "//"
# puts $h_file "// @NETFPGA_LICENSE_HEADER_END@"
# puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
# puts $h_file "// This is an automatically generated header definitions file"
# puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
# puts $h_file ""
# 
# close $h_file 
# 
# };
# proc write_core {target_file prefix id has_registers lib_name} {
# 
# 
# set h_file [open $target_file "a"]
# 
# #First, read the memory map information from the reference_project defines file
# source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
# 
# 
# set baseaddr [set $prefix\_BASEADDR]
# set highaddr [set $prefix\_HIGHADDR]
# set sizeaddr [set $prefix\_SIZEADDR]
# 
# puts $h_file "//######################################################"
# puts $h_file "//# Definitions for $prefix"
# puts $h_file "//######################################################"
# 
# puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr"
# puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr"
# puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr"
# puts $h_file ""
# 
# #Second, read the registers information from the library defines file
# if $has_registers {
# 	set lib_path "$public_repo_dir/std/cores/$lib_name"
# 	set regs_h_define_file $lib_path
# 	set regs_h_define_file_read [open $regs_h_define_file r]
# 	set regs_h_define_file_data [read $regs_h_define_file_read]
# 	close $regs_h_define_file_read
# 	set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"]
# 
#        foreach read_line $regs_h_define_file_data_line {
#             if {[regexp "#define" $read_line]} {
#                 puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]"
#             }
# 	}
# }
# puts $h_file ""
# close $h_file 
# };
# write_header  $target_file 
# foreach lib_item $DEF_LIST { 
#      write_core  $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3] 
# }
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
INFO: [Common 17-206] Exiting Vivado at Wed Jul 24 22:45:24 2019...
cd ../sw/embedded/src  && cp /home/nico/projects/P4-NetFPGA/tools/scripts/xparam2regdefines.py . && python xparam2regdefines.py
cd ../sw/embedded/src  && rm -f xparam2regdefines.py && mv reg_defines.h ../
cd ../sw/embedded && cp /home/nico/projects/P4-NetFPGA/tools/scripts/python_parser.py . && python python_parser.py
cd ../sw/embedded && rm -f python_parser.py && mv reg_defines.py ../../test/reg_defines_simple_sume_switch.py 
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
rm -rf proj_* vivado*.* *.*~ .Xil* /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/
rm -rf *[0-9]_{stim,expected,log}.axi
rm -f *.axi
rm -f portconfig.sim
rm -f seed
rm -f *.log
rm -f ../test/Makefile
rm -rf ../test/*.log
rm -rf ../test/*.axi
rm -rf ../test/seed
rm -rf ../test/*.sim
rm -rf ../test/proj_*
rm -rf ../test/ip_repo
rm -f ../test/vivado*.*
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.py
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.pyc
rm -f ../hw/create_ip/id_rom16x32.coe
cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
echo 16028002 >> rom_data.txt
echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt
grep: ../../../RELEASE_NOTES: No such file or directory
echo 00000204 >> rom_data.txt
echo 0000FFFF >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py 
16

mv -f id_rom16x32.coe ../hw/create_ip/
mv -f rom_data.txt ../hw/create_ip/
cp -f /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_defines_simple_sume_switch.py /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/reg_defines_simple_sume_switch.py
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl -tclargs sim_switch_default

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl
# set design $::env(NF_PROJECT_NAME)
# set top top_sim
# set sim_top top_tb
# set device  xc7vx690t-3-ffg1761
# set proj_dir ./project
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
# set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/
# set repo_dir ./ip_repo
# set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc 
# set project_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_general.xdc
# set nf_10g_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_10g.xdc
# set test_name [lindex $argv 0] 
# source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
# create_project -name ${design} -force -dir "$::env(NF_DESIGN_DIR)/hw/${proj_dir}" -part ${device}
# set_property source_mgmt_mode DisplayOnly [current_project]  
# set_property top ${top} [current_fileset]
# puts "Creating User Datapath reference project"
Creating User Datapath reference project
# create_fileset -constrset -quiet constraints
# file copy ${public_repo_dir}/ ${repo_dir}
# set_property ip_repo_paths ${repo_dir} [current_fileset]
# add_files -fileset constraints -norecurse ${bit_settings}
# add_files -fileset constraints -norecurse ${project_constraints}
# add_files -fileset constraints -norecurse ${nf_10g_constraints}
# set_property is_enabled true [get_files ${project_constraints}]
# set_property is_enabled true [get_files ${bit_settings}]
# set_property is_enabled true [get_files ${project_constraints}]
# update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/ip_repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
# create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
# set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci]
# reset_target all [get_ips nf_sume_sdnet_ip]
# generate_target all [get_ips nf_sume_sdnet_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_sume_sdnet_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_sume_sdnet_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_sume_sdnet_ip'...
# create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip
# set_property -dict [list CONFIG.C_BASEADDR $INPUT_ARBITER_BASEADDR] [get_ips input_arbiter_ip]
# set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci]
# reset_target all [get_ips input_arbiter_ip]
# generate_target all [get_ips input_arbiter_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'input_arbiter_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'input_arbiter_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'input_arbiter_ip'...
# create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip
# set_property -dict [list CONFIG.C_BASEADDR $OUTPUT_QUEUES_BASEADDR] [get_ips sss_output_queues_ip]
# set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci]
# reset_target all [get_ips sss_output_queues_ip]
# generate_target all [get_ips sss_output_queues_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'sss_output_queues_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'sss_output_queues_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'sss_output_queues_ip'...
# create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
create_ip: Time (s): cpu = 00:00:22 ; elapsed = 00:01:00 . Memory (MB): peak = 1690.246 ; gain = 390.395 ; free physical = 7624 ; free virtual = 15312
# set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {1024} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip]
# set_property generate_synth_checkpoint false [get_files identifier_ip.xci]
# reset_target all [get_ips identifier_ip]
# generate_target all [get_ips identifier_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'identifier_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'identifier_ip'...
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'identifier_ip'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'identifier_ip'...
# create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip
# set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip]
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '5.000' to '5.0' has been ignored for IP 'clk_wiz_ip'
# set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci]
# reset_target all [get_ips clk_wiz_ip]
# generate_target all [get_ips clk_wiz_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_ip'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_ip'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_ip'...
# create_ip -name barrier -vendor NetFPGA -library NetFPGA -module_name barrier_ip
# reset_target all [get_ips barrier_ip]
# generate_target all [get_ips barrier_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'barrier_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'barrier_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'barrier_ip'...
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip0
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_0_log.axi] [get_ips axis_sim_record_ip0]
# reset_target all [get_ips axis_sim_record_ip0]
# generate_target all [get_ips axis_sim_record_ip0]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip0'...
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip1
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_1_log.axi] [get_ips axis_sim_record_ip1]
# reset_target all [get_ips axis_sim_record_ip1]
# generate_target all [get_ips axis_sim_record_ip1]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip1'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip1'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip1'...
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip2
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_2_log.axi] [get_ips axis_sim_record_ip2]
# reset_target all [get_ips axis_sim_record_ip2]
# generate_target all [get_ips axis_sim_record_ip2]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip2'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip2'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip2'...
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip3
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_3_log.axi] [get_ips axis_sim_record_ip3]
# reset_target all [get_ips axis_sim_record_ip3]
# generate_target all [get_ips axis_sim_record_ip3]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip3'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip3'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip3'...
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip4
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/dma_0_log.axi] [get_ips axis_sim_record_ip4]
# reset_target all [get_ips axis_sim_record_ip4]
# generate_target all [get_ips axis_sim_record_ip4]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip4'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip4'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip4'...
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip0
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_0_stim.axi] [get_ips axis_sim_stim_ip0]
# generate_target all [get_ips axis_sim_stim_ip0]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip0'...
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip1
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_1_stim.axi] [get_ips axis_sim_stim_ip1]
# generate_target all [get_ips axis_sim_stim_ip1]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip1'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip1'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip1'...
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip2
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_2_stim.axi] [get_ips axis_sim_stim_ip2]
# generate_target all [get_ips axis_sim_stim_ip2]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip2'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip2'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip2'...
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip3
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_3_stim.axi] [get_ips axis_sim_stim_ip3]
# generate_target all [get_ips axis_sim_stim_ip3]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip3'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip3'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip3'...
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip4
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/dma_0_stim.axi] [get_ips axis_sim_stim_ip4]
# generate_target all [get_ips axis_sim_stim_ip4]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip4'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip4'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip4'...
# create_ip -name axi_sim_transactor -vendor NetFPGA -library NetFPGA -module_name axi_sim_transactor_ip
# set_property -dict [list CONFIG.STIM_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.axi CONFIG.EXPECT_FILE $::env(NF_DESIGN_DIR)/test/reg_expect.axi CONFIG.LOG_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.log] [get_ips axi_sim_transactor_ip]
# reset_target all [get_ips axi_sim_transactor_ip]
# generate_target all [get_ips axi_sim_transactor_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_sim_transactor_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_sim_transactor_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_sim_transactor_ip'...
# update_ip_catalog
# source $::env(NF_DESIGN_DIR)/hw/tcl/control_sub_sim.tcl
## set scripts_vivado_version 2018.2
## set current_vivado_version [version -short]
## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
##    puts ""
##    puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
## 
##    return 1
## }
## set design_name control_sub
## if { [get_projects -quiet] eq "" } {
##    puts "ERROR: Please open or create a project!"
##    return 1
## }
## set errMsg ""
## set nRet 0
## set cur_design [current_bd_design -quiet]
## set list_cells [get_bd_cells -quiet]
## if { ${design_name} eq "" } {
##    # USE CASES:
##    #    1) Design_name not set
## 
##    set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
##    set nRet 1
## 
## } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
##    # USE CASES:
##    #    2): Current design opened AND is empty AND names same.
##    #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
##    #    4): Current design opened AND is empty AND names diff; design_name exists in project.
## 
##    if { $cur_design ne $design_name } {
##       puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
##       set design_name [get_property NAME $cur_design]
##    }
##    puts "INFO: Constructing design in IPI design <$cur_design>..."
## 
## } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
##    # USE CASES:
##    #    5) Current design opened AND has components AND same names.
## 
##    set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
##    set nRet 1
## } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
##    # USE CASES: 
##    #    6) Current opened design, has components, but diff names, design_name exists in project.
##    #    7) No opened design, design_name exists in project.
## 
##    set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
##    set nRet 2
## 
## } else {
##    # USE CASES:
##    #    8) No opened design, design_name not in project.
##    #    9) Current opened design, has components, but diff names, design_name not in project.
## 
##    puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
## 
##    create_bd_design $design_name
## 
##    puts "INFO: Making design <$design_name> as current_bd_design."
##    current_bd_design $design_name
## 
## }
INFO: Currently there is no design <control_sub> in project, so creating one...
Wrote  : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd> 
INFO: Making design <control_sub> as current_bd_design.
## puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
INFO: Currently the variable <design_name> is equal to "control_sub".
## if { $nRet != 0 } {
##    puts $errMsg
##    return $nRet
## }
## proc create_root_design { parentCell } {
## 
##   if { $parentCell eq "" } {
##      set parentCell [get_bd_cells /]
##   }
## 
##   # Get object for parentCell
##   set parentObj [get_bd_cells $parentCell]
##   if { $parentObj == "" } {
##      puts "ERROR: Unable to find parent cell <$parentCell>!"
##      return
##   }
## 
##   # Make sure parentObj is hier blk
##   set parentType [get_property TYPE $parentObj]
##   if { $parentType ne "hier" } {
##      puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
##      return
##   }
## 
##   # Save current instance; Restore later
##   set oldCurInst [current_bd_instance .]
## 
##   # Set parent object as current
##   current_bd_instance $parentObj
## 
## 
##   # Create interface ports
##   set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M00_AXI
##   set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M01_AXI
##   set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M02_AXI
##   set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M03_AXI
##   set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M04_AXI
##   set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M05_AXI
##   set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M06_AXI
##   set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M07_AXI
##   set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.CLK_DOMAIN {} CONFIG.DATA_WIDTH {32} CONFIG.FREQ_HZ {100000000} CONFIG.ID_WIDTH {0} CONFIG.MAX_BURST_LENGTH {256} CONFIG.NUM_READ_OUTSTANDING {2} CONFIG.NUM_WRITE_OUTSTANDING {2} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0}  ] $S00_AXI
## 
##   # Create ports
##   set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ]
##   set axi_lite_areset [ create_bd_port -dir I -type rst axi_lite_areset ]
##   set core_clk [ create_bd_port -dir I -type clk core_clk ]
##   set_property -dict [ list CONFIG.FREQ_HZ {200000000}  ] $core_clk
##   set core_resetn [ create_bd_port -dir I -type rst core_resetn ]
##   
##   
##     
## 
##   # Create instance: axi_interconnect_0, and set properties
##   set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
##   set_property -dict [ list CONFIG.NUM_MI {8} CONFIG.TRANSLATION_MODE {0} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0              
##   set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
## 
## 
## # Add AXI clock converter
## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0
## connect_bd_intf_net [get_bd_intf_ports S00_AXI] [get_bd_intf_pins axi_clock_converter_0/S_AXI]
## connect_bd_intf_net [get_bd_intf_pins axi_clock_converter_0/M_AXI] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI]
## 
##   # Create interface connections
##   connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI]
## 
##   # Create port connections
##   connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk]  [get_bd_pins axi_clock_converter_0/s_axi_aclk] 
## connect_bd_net -net core_clk_1 [get_bd_ports core_clk]  [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] 
## connect_bd_net -net axi_lite_areset_1 [get_bd_ports axi_lite_areset] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] 
## connect_bd_net -net core_resetn_1 [get_bd_ports core_resetn] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN]  [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] 
## 
##   # Create address segments
## source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
##   assign_bd_address [get_bd_addr_segs {M00_AXI/Reg }]  
##   set_property offset $M00_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}]
##   set_property range $M00_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}] 
## 
##  assign_bd_address [get_bd_addr_segs {M01_AXI/Reg }]  
##   set_property offset $M01_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}]
##   set_property range $M01_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}] 
## 
## 
## assign_bd_address [get_bd_addr_segs {M02_AXI/Reg }]  
##   set_property offset $M02_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}]
##   set_property range $M02_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}] 
## 
## assign_bd_address [get_bd_addr_segs {M03_AXI/Reg }]  
##   set_property offset $M03_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}]
##   set_property range $M03_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}] 
## 
##  
##   # Restore current instance
##   current_bd_instance $oldCurInst
## 
##   save_bd_design
## }
## create_root_design ""
CRITICAL WARNING: [BD 41-737] Cannot set the parameter TRANSLATION_MODE on /axi_interconnect_0. It is read-only.
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
</M00_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
</M01_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
</M02_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
</M03_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
Wrote  : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd> 
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/axi_clocking.v"
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/nf_datapath.v"
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_sim.v"
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_tb.v"
# update_compile_order -fileset sources_1
# update_compile_order -fileset sim_1
# set_property top ${sim_top} [get_filesets sim_1]
# set_property include_dirs ${proj_dir} [get_filesets sim_1]
# set_property simulator_language Mixed [current_project]
# set_property verilog_define { {SIMULATION=1} } [get_filesets sim_1]
# set_property -name xsim.more_options -value {-testplusarg TESTNAME=basic_test} -objects [get_filesets sim_1]
# set_property runtime {} [get_filesets sim_1]
# set_property target_simulator xsim [current_project]
# set_property compxlib.xsim_compiled_library_dir {} [current_project]
# set_property top_lib xil_defaultlib [get_filesets sim_1]
# update_compile_order -fileset sim_1
update_compile_order: Time (s): cpu = 00:00:21 ; elapsed = 00:00:10 . Memory (MB): peak = 2029.410 ; gain = 8.020 ; free physical = 7492 ; free virtual = 15200
loading libsume..
Traceback (most recent call last):
  File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py", line 42, in <module>
    import config_writes
  File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py", line 7
    
                        ^
IndentationError: expected an indented block
    while executing
"exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py"
    invoked from within
"set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]"
    (file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 177)
INFO: [Common 17-206] Exiting Vivado at Wed Jul 24 22:46:55 2019...
Makefile:120: recipe for target 'sim' failed
make: *** [sim] Error 1
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_stim.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_expected.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_stim.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_expected.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_stim.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_expected.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_stim.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_expected.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_expected.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.log': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_expect.axi': No such file or directory
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.axi': No such file or directory
NetFPGA environment:
   Root dir:       /home/nico/projects/P4-NetFPGA
   Project name:   simple_sume_switch
   Project dir:    /tmp/nico/test/simple_sume_switch
   Work dir:       /tmp/nico
512
=== Work directory is /tmp/nico/test/simple_sume_switch
=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
+ date
Mit Jul 24 22:46:55 CEST 2019
+ [  = no ]
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch
+ make
make -C hw distclean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
rm -rf proj_* vivado*.* *.*~ .Xil* /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/
rm -rf *[0-9]_{stim,expected,log}.axi
rm -f *.axi
rm -f portconfig.sim
rm -f seed
rm -f *.log
rm -f ../test/Makefile
rm -rf ../test/*.log
rm -rf ../test/*.axi
rm -rf ../test/seed
rm -rf ../test/*.sim
rm -rf ../test/proj_*
rm -rf ../test/ip_repo
rm -f ../test/vivado*.*
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.py
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.pyc
rm -rfv project;\
	rm -rfv ../sw/embedded/project;\
	rm -rfv vivado*;\
	rm -rfv *.log;\
	rm -rfv .Xil;\
	rm -rfv ..rej;\
	rm -rfv .srcs;\
	rm -rfv webtalk*;\
	rm -rfv *.*~;\
	rm -rfv ip_repo;\
	rm -rfv ip_proj;\
	rm -rfv std;\
                
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
make -C sw/embedded/ distclean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
rm -rf `find . -name "SDK_Workspace"`
rm -rf `find . -name "*.log"`
rm -rf `find . -name "*.jou"`
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
rm -rfv vivado*;\

make -C hw project
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
rm -f ../hw/create_ip/id_rom16x32.coe
cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
echo 16028002 >> rom_data.txt
echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt
grep: ../../../RELEASE_NOTES: No such file or directory
echo 00000204 >> rom_data.txt
echo 0000FFFF >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py 
16

mv -f id_rom16x32.coe ../hw/create_ip/
mv -f rom_data.txt ../hw/create_ip/
echo "Create reference project under folder /project";\
if test -d project/; then\
	echo "Project already exists"; \
else \
	vivado -mode batch -source tcl/simple_sume_switch.tcl;\
	if [ -f patch/simple_sume_switch.patch ]; then\
		patch -p1 < patch/simple_sume_switch.patch;\
	fi;\
fi;\

Create reference project under folder /project

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source tcl/simple_sume_switch.tcl
# set design $::env(NF_PROJECT_NAME) 
# set top top
# set device xc7vx690t-3-ffg1761
# set proj_dir ./project
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
# set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/
# set repo_dir ./ip_repo
# set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc 
# set project_constraints ./constraints/nf_sume_general.xdc
# set nf_10g_constraints ./constraints/nf_sume_10g.xdc
# source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
## set M00_BASEADDR 0x44000000
## set M00_HIGHADDR 0x44000FFF
## set M00_SIZEADDR 0x1000
## set M01_BASEADDR 0x44010000
## set M01_HIGHADDR 0x44010FFF
## set M01_SIZEADDR 0x1000
## set M02_BASEADDR 0x44020000
## set M02_HIGHADDR 0x44020FFF
## set M02_SIZEADDR 0x1000
## set M03_BASEADDR 0x44030000
## set M03_HIGHADDR 0x44030FFF
## set M03_SIZEADDR 0x1000
## set M04_BASEADDR 0x44040000
## set M04_HIGHADDR 0x44040FFF
## set M04_SIZEADDR 0x1000
## set M05_BASEADDR 0x44050000
## set M05_HIGHADDR 0x44050FFF
## set M05_SIZEADDR 0x1000
## set M06_BASEADDR 0x44060000
## set M06_HIGHADDR 0x44060FFF
## set M06_SIZEADDR 0x1000
## set M07_BASEADDR 0x44070000
## set M07_HIGHADDR 0x44070FFF
## set M07_SIZEADDR 0x1000
## set M08_BASEADDR 0x44080000
## set M08_HIGHADDR 0x44080FFF
## set M08_SIZEADDR 0x1000
## set IDENTIFIER_BASEADDR $M00_BASEADDR
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
# source ./tcl/export_registers.tcl
## set DEF_LIST {
## 	{MICROBLAZE_AXI_IIC 0 0 ""} \
## 	{MICROBLAZE_UARTLITE 0 0 ""} \
## 	{MICROBLAZE_DLMB_BRAM 0 0 ""} \
## 	{MICROBLAZE_ILMB_BRAM 0 0 ""} \
## 	{MICROBLAZE_AXI_INTC 0 0 ""} \
## 	{INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \
## 	{OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \
## 	{OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \
## 	{NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \
## 	{NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
## 	{NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
## 	{NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
## 	{NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \
## 
## 
## }
## set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/
## set target_file $target_path/sume_register_defines.h
## proc write_header { target_file } {
## 
## # creat a blank header file
## # do a fresh rewrite in case the file already exits
## file delete -force $target_file
## open $target_file "w"
## set h_file [open $target_file "w"]
## 
## 
## puts $h_file "//-"
## puts $h_file "// Copyright (c) 2015 University of Cambridge"
## puts $h_file "// All rights reserved."
## puts $h_file "//"
## puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory "
## puts $h_file "// under National Science Foundation under Grant No. CNS-0855268,"
## puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and"
## puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), "
## puts $h_file "// as part of the DARPA MRC research programme."
## puts $h_file "//"
## puts $h_file "// @NETFPGA_LICENSE_HEADER_START@"
## puts $h_file "//"
## puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor"
## puts $h_file "// license agreements.  See the NOTICE file distributed with this work for"
## puts $h_file "// additional information regarding copyright ownership.  NetFPGA licenses this"
## puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the"
## puts $h_file "// \"License\"); you may not use this file except in compliance with the"
## puts $h_file "// License.  You may obtain a copy of the License at:"
## puts $h_file "//"
## puts $h_file "//   http://www.netfpga-cic.org"
## puts $h_file "//"
## puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed"
## puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR"
## puts $h_file "// CONDITIONS OF ANY KIND, either express or implied.  See the License for the"
## puts $h_file "// specific language governing permissions and limitations under the License."
## puts $h_file "//"
## puts $h_file "// @NETFPGA_LICENSE_HEADER_END@"
## puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
## puts $h_file "// This is an automatically generated header definitions file"
## puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
## puts $h_file ""
## 
## close $h_file 
## 
## };
## proc write_core {target_file prefix id has_registers lib_name} {
## 
## 
## set h_file [open $target_file "a"]
## 
## #First, read the memory map information from the reference_project defines file
## source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
## set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
## 
## 
## set baseaddr [set $prefix\_BASEADDR]
## set highaddr [set $prefix\_HIGHADDR]
## set sizeaddr [set $prefix\_SIZEADDR]
## 
## puts $h_file "//######################################################"
## puts $h_file "//# Definitions for $prefix"
## puts $h_file "//######################################################"
## 
## puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr"
## puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr"
## puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr"
## puts $h_file ""
## 
## #Second, read the registers information from the library defines file
## if $has_registers {
## 	set lib_path "$public_repo_dir/std/cores/$lib_name"
## 	set regs_h_define_file $lib_path
## 	set regs_h_define_file_read [open $regs_h_define_file r]
## 	set regs_h_define_file_data [read $regs_h_define_file_read]
## 	close $regs_h_define_file_read
## 	set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"]
## 
##        foreach read_line $regs_h_define_file_data_line {
##             if {[regexp "#define" $read_line]} {
##                 puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]"
##             }
## 	}
## }
## puts $h_file ""
## close $h_file 
## };
## write_header  $target_file 
## foreach lib_item $DEF_LIST { 
##      write_core  $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3] 
## }
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
# create_project -name ${design} -force -dir "./${proj_dir}" -part ${device}
# set_property source_mgmt_mode DisplayOnly [current_project]
# set_property top ${top} [current_fileset]
# puts "Creating User Datapath reference project"
Creating User Datapath reference project
# create_fileset -constrset -quiet constraints
# file copy ${public_repo_dir}/ ${repo_dir}
# set_property ip_repo_paths ${repo_dir} [current_fileset]
# add_files -fileset constraints -norecurse ${bit_settings}
# add_files -fileset constraints -norecurse ${project_constraints}
# add_files -fileset constraints -norecurse ${nf_10g_constraints}
# set_property is_enabled true [get_files ${project_constraints}]
# set_property is_enabled true [get_files ${bit_settings}]
# set_property is_enabled true [get_files ${nf_10g_constraints}]
# set_property constrset constraints [get_runs synth_1]
# set_property constrset constraints [get_runs impl_1]
# update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
# create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip
# set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci]
# reset_target all [get_ips input_arbiter_ip]
# generate_target all [get_ips input_arbiter_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'input_arbiter_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'input_arbiter_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'input_arbiter_ip'...
# create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip
# set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci]
# reset_target all [get_ips sss_output_queues_ip]
# generate_target all [get_ips sss_output_queues_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'sss_output_queues_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'sss_output_queues_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'sss_output_queues_ip'...
# source ./tcl/control_sub.tcl
## set scripts_vivado_version 2018.2
## set current_vivado_version [version -short]
## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
##    puts ""
##    puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
## 
##    return 1
## }
## set design_name control_sub
## if { [get_projects -quiet] eq "" } {
##    puts "ERROR: Please open or create a project!"
##    return 1
## }
## set errMsg ""
## set nRet 0
## set cur_design [current_bd_design -quiet]
## set list_cells [get_bd_cells -quiet]
## if { ${design_name} eq "" } {
##    # USE CASES:
##    #    1) Design_name not set
## 
##    set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
##    set nRet 1
## 
## } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
##    # USE CASES:
##    #    2): Current design opened AND is empty AND names same.
##    #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
##    #    4): Current design opened AND is empty AND names diff; design_name exists in project.
## 
##    if { $cur_design ne $design_name } {
##       puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
##       set design_name [get_property NAME $cur_design]
##    }
##    puts "INFO: Constructing design in IPI design <$cur_design>..."
## 
## } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
##    # USE CASES:
##    #    5) Current design opened AND has components AND same names.
## 
##    set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
##    set nRet 1
## } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
##    # USE CASES: 
##    #    6) Current opened design, has components, but diff names, design_name exists in project.
##    #    7) No opened design, design_name exists in project.
## 
##    set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
##    set nRet 2
## 
## } else {
##    # USE CASES:
##    #    8) No opened design, design_name not in project.
##    #    9) Current opened design, has components, but diff names, design_name not in project.
## 
##    puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
## 
##    create_bd_design $design_name
## 
##    puts "INFO: Making design <$design_name> as current_bd_design."
##    current_bd_design $design_name
## 
## }
INFO: Currently there is no design <control_sub> in project, so creating one...
Wrote  : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd> 
INFO: Making design <control_sub> as current_bd_design.
## puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
INFO: Currently the variable <design_name> is equal to "control_sub".
## if { $nRet != 0 } {
##    puts $errMsg
##    return $nRet
## }
## proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } {
## 
##   if { $parentCell eq "" || $nameHier eq "" } {
##      puts "ERROR: create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"
##      return
##   }
## 
##   # Get object for parentCell
##   set parentObj [get_bd_cells $parentCell]
##   if { $parentObj == "" } {
##      puts "ERROR: Unable to find parent cell <$parentCell>!"
##      return
##   }
## 
##   # Make sure parentObj is hier blk
##   set parentType [get_property TYPE $parentObj]
##   if { $parentType ne "hier" } {
##      puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
##      return
##   }
## 
##   # Save current instance; Restore later
##   set oldCurInst [current_bd_instance .]
## 
##   # Set parent object as current
##   current_bd_instance $parentObj
## 
##   # Create cell and set as current instance
##   set hier_obj [create_bd_cell -type hier $nameHier]
##   current_bd_instance $hier_obj
## 
##   # Create interface pins
##   create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB
##   create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB
## 
##   # Create pins
##   create_bd_pin -dir I -type clk LMB_Clk
##   create_bd_pin -dir I -from 0 -to 0 -type rst LMB_Rst
## 
##   # Create instance: dlmb_bram_if_cntlr, and set properties
##   set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ]
##   set_property -dict [ list CONFIG.C_ECC {0}  ] $dlmb_bram_if_cntlr
## 
##   # Create instance: dlmb_v10, and set properties
##   set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ]
## 
##   # Create instance: ilmb_bram_if_cntlr, and set properties
##   set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ]
##   set_property -dict [ list CONFIG.C_ECC {0}  ] $ilmb_bram_if_cntlr
## 
##   # Create instance: ilmb_v10, and set properties
##   set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ]
## 
##   # Create instance: lmb_bram, and set properties
##   set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ]
##   set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}  ] $lmb_bram
## 
##   # Create interface connections
##   connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M]
##   connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0]
##   connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
##   connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M]
##   connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0]
##   connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
## 
##   # Create port connections
##   connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk]
##   connect_bd_net -net microblaze_0_LMB_Rst [get_bd_pins LMB_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst]
##   
##   # Restore current instance
##   current_bd_instance $oldCurInst
## }
## proc create_hier_cell_mbsys { parentCell nameHier } {
## 
##   if { $parentCell eq "" || $nameHier eq "" } {
##      puts "ERROR: create_hier_cell_mbsys() - Empty argument(s)!"
##      return
##   }
## 
##   # Get object for parentCell
##   set parentObj [get_bd_cells $parentCell]
##   if { $parentObj == "" } {
##      puts "ERROR: Unable to find parent cell <$parentCell>!"
##      return
##   }
## 
##   # Make sure parentObj is hier blk
##   set parentType [get_property TYPE $parentObj]
##   if { $parentType ne "hier" } {
##      puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
##      return
##   }
## 
##   # Save current instance; Restore later
##   set oldCurInst [current_bd_instance .]
## 
##   # Set parent object as current
##   current_bd_instance $parentObj
## 
##   # Create cell and set as current instance
##   set hier_obj [create_bd_cell -type hier $nameHier]
##   current_bd_instance $hier_obj
## 
##   # Create interface pins
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI
## 
##   # Create pins
##   create_bd_pin -dir I -type clk Clk
##   create_bd_pin -dir I -from 0 -to 0 In0
##   create_bd_pin -dir I -from 0 -to 0 In1
##   create_bd_pin -dir I dcm_locked
##   create_bd_pin -dir I -type rst ext_reset_in
##   create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn
## 
##   # Create instance: mdm_1, and set properties
##   set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ]
## 
##   # Create instance: microblaze_0, and set properties
##   set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:10.0 microblaze_0 ]
##   set_property -dict [ list CONFIG.C_DEBUG_ENABLED {1} CONFIG.C_D_AXI {1} CONFIG.C_D_LMB {1} CONFIG.C_I_LMB {1}  ] $microblaze_0
## 
##   # Create instance: microblaze_0_axi_intc, and set properties
##   set microblaze_0_axi_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 microblaze_0_axi_intc ]
##   set_property -dict [ list CONFIG.C_HAS_FAST {1}  ] $microblaze_0_axi_intc
## 
##   # Create instance: microblaze_0_axi_periph, and set properties
##   set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]
##   set_property -dict [ list CONFIG.NUM_MI {3}  ] $microblaze_0_axi_periph
## 
##   # Create instance: microblaze_0_local_memory
##   create_hier_cell_microblaze_0_local_memory $hier_obj microblaze_0_local_memory
## 
##   # Create instance: microblaze_0_xlconcat, and set properties
##   set microblaze_0_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 microblaze_0_xlconcat ]
## 
##   # Create instance: rst_clk_wiz_1_100M, and set properties
##   set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ]
## 
##   # Create interface connections
##   connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins M01_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI]
##   connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins M02_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI]
##   connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]
##   connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG]
##   connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB]
##   connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB]
##   connect_bd_intf_net -intf_net microblaze_0_intc_axi [get_bd_intf_pins microblaze_0_axi_intc/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]
##   connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins microblaze_0/INTERRUPT] [get_bd_intf_pins microblaze_0_axi_intc/interrupt]
## 
##   # Create port connections
##   connect_bd_net -net In0_1 [get_bd_pins In0] [get_bd_pins microblaze_0_xlconcat/In0]
##   connect_bd_net -net In1_1 [get_bd_pins In1] [get_bd_pins microblaze_0_xlconcat/In1]
##   connect_bd_net -net clk_wiz_1_locked [get_bd_pins dcm_locked] [get_bd_pins rst_clk_wiz_1_100M/dcm_locked]
##   connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst]
##   connect_bd_net -net microblaze_0_Clk [get_bd_pins Clk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_intc/processor_clk] [get_bd_pins microblaze_0_axi_intc/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk]
##   connect_bd_net -net microblaze_0_intr [get_bd_pins microblaze_0_axi_intc/intr] [get_bd_pins microblaze_0_xlconcat/dout]
##   connect_bd_net -net reset_1 [get_bd_pins ext_reset_in] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]
##   connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/LMB_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset]
##   connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn]
##   connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins microblaze_0_axi_intc/processor_rst] [get_bd_pins rst_clk_wiz_1_100M/mb_reset]
##   connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins peripheral_aresetn] [get_bd_pins microblaze_0_axi_intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn]
##   
##   # Restore current instance
##   current_bd_instance $oldCurInst
## }
## proc create_hier_cell_nf_mbsys { parentCell nameHier } {
## 
##   if { $parentCell eq "" || $nameHier eq "" } {
##      puts "ERROR: create_hier_cell_nf_mbsys() - Empty argument(s)!"
##      return
##   }
## 
##   # Get object for parentCell
##   set parentObj [get_bd_cells $parentCell]
##   if { $parentObj == "" } {
##      puts "ERROR: Unable to find parent cell <$parentCell>!"
##      return
##   }
## 
##   # Make sure parentObj is hier blk
##   set parentType [get_property TYPE $parentObj]
##   if { $parentType ne "hier" } {
##      puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
##      return
##   }
## 
##   # Save current instance; Restore later
##   set oldCurInst [current_bd_instance .]
## 
##   # Set parent object as current
##   current_bd_instance $parentObj
## 
##   # Create cell and set as current instance
##   set hier_obj [create_bd_cell -type hier $nameHier]
##   current_bd_instance $hier_obj
## 
##   # Create interface pins
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart
## 
##   # Create pins
##   create_bd_pin -dir O -from 1 -to 0 iic_reset
##   create_bd_pin -dir I -type rst reset
##   create_bd_pin -dir I -type clk sysclk
## 
##   # Create instance: axi_iic_0, and set properties
##   set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ]
##   set_property -dict [ list CONFIG.C_GPO_WIDTH {2} CONFIG.C_SCL_INERTIAL_DELAY {5} CONFIG.C_SDA_INERTIAL_DELAY {5}  ] $axi_iic_0
## 
##   # Create instance: axi_uartlite_0, and set properties
##   set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
##   set_property -dict [ list CONFIG.C_BAUDRATE {115200}  ] $axi_uartlite_0
## 
##   # Create instance: clk_wiz_1, and set properties
##   set clk_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_1 ]
## #  set_property -dict [ list CONFIG.PRIM_IN_FREQ {200.000} CONFIG.PRIM_SOURCE {No_buffer}  ] $clk_wiz_1
##   
##   # config 100MHz input clk
##   set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} CONFIG.PRIM_SOURCE {No_buffer} \
##   CONFIG.CLKIN1_JITTER_PS {100.0} CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \
##   CONFIG.MMCM_CLKIN1_PERIOD {10.0} CONFIG.CLKOUT1_JITTER {130.958} \
##   CONFIG.CLKOUT1_PHASE_ERROR {98.575}] $clk_wiz_1 
##   
## 
##   # Create instance: mbsys
##   create_hier_cell_mbsys $hier_obj mbsys
## 
##   # Create interface connections
##   connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_pins iic_fpga] [get_bd_intf_pins axi_iic_0/IIC]
##   connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_pins uart] [get_bd_intf_pins axi_uartlite_0/UART]
##   connect_bd_intf_net -intf_net mbsys_M01_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins mbsys/M01_AXI]
##   connect_bd_intf_net -intf_net mbsys_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins mbsys/M02_AXI]
## 
##   # Create port connections
##   connect_bd_net -net axi_iic_0_gpo [get_bd_pins iic_reset] [get_bd_pins axi_iic_0/gpo]
##   connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins mbsys/In0]
##   connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins mbsys/In1]
##   connect_bd_net -net clk_wiz_1_locked [get_bd_pins clk_wiz_1/locked] [get_bd_pins mbsys/dcm_locked]
##   connect_bd_net -net mbsys_peripheral_aresetn [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins mbsys/peripheral_aresetn]
##   connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins clk_wiz_1/clk_out1] [get_bd_pins mbsys/Clk]
##   connect_bd_net -net reset_1 [get_bd_pins reset] [get_bd_pins clk_wiz_1/reset] [get_bd_pins mbsys/ext_reset_in]
##   connect_bd_net -net sysclk_1 [get_bd_pins sysclk] [get_bd_pins clk_wiz_1/clk_in1]
##   
##   # Restore current instance
##   current_bd_instance $oldCurInst
## }
## proc create_hier_cell_dma_sub { parentCell nameHier } {
## 
##   if { $parentCell eq "" || $nameHier eq "" } {
##      puts "ERROR: create_hier_cell_dma_sub() - Empty argument(s)!"
##      return
##   }
## 
##   # Get object for parentCell
##   set parentObj [get_bd_cells $parentCell]
##   if { $parentObj == "" } {
##      puts "ERROR: Unable to find parent cell <$parentCell>!"
##      return
##   }
## 
##   # Make sure parentObj is hier blk
##   set parentType [get_property TYPE $parentObj]
##   if { $parentType ne "hier" } {
##      puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
##      return
##   }
## 
##   # Save current instance; Restore later
##   set oldCurInst [current_bd_instance .]
## 
##   # Set parent object as current
##   current_bd_instance $parentObj
## 
##   # Create cell and set as current instance
##   set hier_obj [create_bd_cell -type hier $nameHier]
##   current_bd_instance $hier_obj
## 
##   # Create interface pins
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma_tx
##   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_7x_mgt
##   create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma_rx
## 
##   # Create pins
##   create_bd_pin -dir I -type clk axi_lite_aclk
##   create_bd_pin -dir I -type rst axi_lite_aresetn
##   create_bd_pin -dir I -type clk axis_datapath_aclk
##   create_bd_pin -dir I -type rst axis_datapath_aresetn
##   create_bd_pin -dir I -type clk sys_clk
##   create_bd_pin -dir I -type rst sys_reset
##   
##   create_bd_pin -dir I -type clk M00_ACLK
##   create_bd_pin -dir I -type rst M00_ARESETN
##   create_bd_pin -dir I -type clk M01_ACLK
##   create_bd_pin -dir I -type rst M01_ARESETN
##   create_bd_pin -dir I -type clk M02_ACLK
##   create_bd_pin -dir I -type rst M02_ARESETN
##   create_bd_pin -dir I -type clk M03_ACLK
##   create_bd_pin -dir I -type rst M03_ARESETN
##   create_bd_pin -dir I -type clk M04_ACLK
##   create_bd_pin -dir I -type rst M04_ARESETN
##   create_bd_pin -dir I -type clk M05_ACLK
##   create_bd_pin -dir I -type rst M05_ARESETN
##   create_bd_pin -dir I -type clk M06_ACLK
##   create_bd_pin -dir I -type rst M06_ARESETN
##   create_bd_pin -dir I -type clk M07_ACLK
##   create_bd_pin -dir I -type rst M07_ARESETN
##   
##   # Create instance: axi_interconnect_0, and set properties
##   set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
##   set_property -dict [ list CONFIG.NUM_MI {9}  ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0              
##   set_property -dict [list CONFIG.M08_HAS_REGSLICE {3} CONFIG.M08_HAS_DATA_FIFO {1} ] $axi_interconnect_0
##   set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
## 
##   # AXIS: clock domain crossing FIFO, TX (PCIe->FPGA) user_fifo_reset (user_clk)
##   set pcie_reset_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic pcie_reset_inv]
##   set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {not}] [get_bd_cells pcie_reset_inv]
## 
##   # Create instance: axis_dwidth_converter
##   set axis_dwidth_dma_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_dma_tx]
##   set_property -dict [list CONFIG.HAS_TKEEP.VALUE_SRC USER CONFIG.HAS_TLAST.VALUE_SRC USER \
##            CONFIG.HAS_TSTRB.VALUE_SRC USER CONFIG.S_TDATA_NUM_BYTES.VALUE_SRC USER \
## 	   CONFIG.TUSER_BITS_PER_BYTE.VALUE_SRC USER] $axis_dwidth_dma_tx
## 
##   set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {16} CONFIG.M_TDATA_NUM_BYTES {32} \
## 	   CONFIG.TUSER_BITS_PER_BYTE {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TSTRB {0} \
## 	   CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1}] $axis_dwidth_dma_tx
## 
## 
## 
##   set axis_dwidth_dma_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_dma_rx]	    
##  
##   set_property -dict [list CONFIG.HAS_TKEEP.VALUE_SRC USER CONFIG.HAS_TLAST.VALUE_SRC USER \
##              CONFIG.HAS_TSTRB.VALUE_SRC USER CONFIG.S_TDATA_NUM_BYTES.VALUE_SRC USER \
##              CONFIG.TUSER_BITS_PER_BYTE.VALUE_SRC USER] $axis_dwidth_dma_rx
## 
##   set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {32} CONFIG.M_TDATA_NUM_BYTES {16} \
##              CONFIG.TUSER_BITS_PER_BYTE {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TSTRB {0} \
## 	     CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1}] $axis_dwidth_dma_rx
## 
##  # Create instance: axis_fifo_10g_rx, and set properties
##  set axis_fifo_10g_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_fifo_10g_rx]
##  set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.TUSER_WIDTH {128} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32}] $axis_fifo_10g_rx
## 
##   # Create instance: axis_fifo_10g_tx, and set properties
##  set axis_fifo_10g_tx [create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_fifo_10g_tx]
##  set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.TUSER_WIDTH {128} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32}] $axis_fifo_10g_tx	 
##   
##   # Create instance: nf_riffa_dma_1, and set properties
##   set nf_riffa_dma_1 [ create_bd_cell -type ip -vlnv NetFPGA:NetFPGA:nf_riffa_dma:1.0 nf_riffa_dma_1 ]
##   
##   # Create instance: axi_clock_converter_0, and set properties
##   set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ] 
## 
##   # Create instance: pcie3_7x_1, and set properties
##   set pcie3_7x_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:pcie3_7x:4.3 pcie3_7x_1 ]
##   set_property -dict [ list CONFIG.PF0_DEVICE_ID {7028} \
## CONFIG.PF0_INTERRUPT_PIN {NONE} CONFIG.PF1_DEVICE_ID {7011} \
## CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {5.0_GT/s} CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
## CONFIG.axisten_freq {250} CONFIG.axisten_if_enable_client_tag {false} \
## CONFIG.axisten_if_width {128_bit} CONFIG.cfg_ctl_if {false} \
## CONFIG.cfg_ext_if {false} CONFIG.cfg_mgmt_if {false} \
## CONFIG.cfg_tx_msg_if {false} CONFIG.en_ext_clk {false} \
## CONFIG.extended_tag_field {true} CONFIG.gen_x0y0 {false} \
## CONFIG.mode_selection {Advanced} CONFIG.pcie_blk_locn {X0Y1} \
## CONFIG.per_func_status_if {false} CONFIG.pf0_bar0_size {1} \
## CONFIG.pf0_dev_cap_max_payload {128_bytes} CONFIG.rcv_msg_if {false} \
## CONFIG.tx_fc_if {false} CONFIG.xlnx_ref_board {None} \
##  ] $pcie3_7x_1
## 
##   # Create interface connections
##   connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI]
## 
##   connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_dma_rx [get_bd_intf_pins s_axis_dma_rx] [get_bd_intf_pins axis_dwidth_dma_rx/S_AXIS]
##   connect_bd_intf_net -intf_net nf_riffa_dma_1_fifo_dwidth_rx [get_bd_intf_pins axis_fifo_10g_rx/S_AXIS] [get_bd_intf_pins axis_dwidth_dma_rx/M_AXIS]
##   connect_bd_intf_net -intf_net axis_fifo_10g_rx_M_AXIS [get_bd_intf_pins axis_fifo_10g_rx/M_AXIS] [get_bd_intf_pins nf_riffa_dma_1/s_axis_xge_rx]
## 
## 
##   connect_bd_intf_net -intf_net nf_riffa_dma_1_m_axis_dma_tx [get_bd_intf_pins m_axis_dma_tx] [get_bd_intf_pins axis_dwidth_dma_tx/M_AXIS]
##   connect_bd_intf_net -intf_net nf_riffa_dma_1_fifo_dwidth_tx [get_bd_intf_pins axis_fifo_10g_tx/M_AXIS] [get_bd_intf_pins axis_dwidth_dma_tx/S_AXIS]
##   connect_bd_intf_net -intf_net nf_riffa_dma_1_dwidth_conv_tx [get_bd_intf_pins axis_fifo_10g_tx/S_AXIS] [get_bd_intf_pins nf_riffa_dma_1/m_axis_xge_tx]
## 	
##  
## 
##  connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_interrupt [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_interrupt]
##   connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_msi [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt_msi] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_msi]
##   connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_status [get_bd_intf_pins nf_riffa_dma_1/cfg] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_status]
##   connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie_cfg_fc [get_bd_intf_pins nf_riffa_dma_1/cfg_fc] [get_bd_intf_pins pcie3_7x_1/pcie_cfg_fc]
##   connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_cc [get_bd_intf_pins nf_riffa_dma_1/s_axis_cc] [get_bd_intf_pins pcie3_7x_1/s_axis_cc]
##   connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_rq [get_bd_intf_pins nf_riffa_dma_1/s_axis_rq] [get_bd_intf_pins pcie3_7x_1/s_axis_rq]
##   connect_bd_intf_net -intf_net pcie3_7x_1_m_axis_cq [get_bd_intf_pins nf_riffa_dma_1/m_axis_cq] [get_bd_intf_pins pcie3_7x_1/m_axis_cq]
##   connect_bd_intf_net -intf_net pcie3_7x_1_m_axis_rc [get_bd_intf_pins nf_riffa_dma_1/m_axis_rc] [get_bd_intf_pins pcie3_7x_1/m_axis_rc]
##   connect_bd_intf_net -intf_net pcie3_7x_1_pcie_7x_mgt [get_bd_intf_pins pcie_7x_mgt] [get_bd_intf_pins pcie3_7x_1/pcie_7x_mgt]
##   connect_bd_intf_net -intf_net s00_axi_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins nf_riffa_dma_1/m_axi_lite]
##   
##   #Clock converter connections
##   connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins nf_riffa_dma_1/s_axi_lite]
##   connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M08_AXI]
## set_property -dict [ list CONFIG.FREQ_HZ {250000000}  ] [get_bd_intf_pins nf_riffa_dma_1/s_axi_lite]
## 
##   
## 
##   # Create port connections
##   connect_bd_net -net axi_lite_clk_1 [get_bd_pins axi_lite_aclk]  [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins nf_riffa_dma_1/m_axi_lite_aclk]
## 
## 
## connect_bd_net -net M00_ACLK_i [get_bd_pins M00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] 
## connect_bd_net -net M01_ACLK_i [get_bd_pins M01_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] 
## connect_bd_net -net M02_ACLK_i [get_bd_pins M02_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK]
## connect_bd_net -net M03_ACLK_i [get_bd_pins M03_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK]
## connect_bd_net -net M04_ACLK_i [get_bd_pins M04_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] 
## connect_bd_net -net M05_ACLK_i [get_bd_pins M05_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] 
## connect_bd_net -net M06_ACLK_i [get_bd_pins M06_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] 
## connect_bd_net -net M07_ACLK_i [get_bd_pins M07_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] 
## 
##   connect_bd_net -net axi_lite_rstn_1  [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_lite_aresetn] [get_bd_pins nf_riffa_dma_1/m_axi_lite_aresetn]
## 
## 
## connect_bd_net -net M00_ARESETN_i [get_bd_pins M00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] 
## connect_bd_net -net M01_ARESETN_i [get_bd_pins M01_ARESETN]  [get_bd_pins axi_interconnect_0/M01_ARESETN]
## connect_bd_net -net M02_ARESETN_i [get_bd_pins M02_ARESETN]  [get_bd_pins axi_interconnect_0/M02_ARESETN]
## connect_bd_net -net M03_ARESETN_i [get_bd_pins M03_ARESETN]  [get_bd_pins axi_interconnect_0/M03_ARESETN]
## connect_bd_net -net M04_ARESETN_i [get_bd_pins M04_ARESETN]  [get_bd_pins axi_interconnect_0/M04_ARESETN]
## connect_bd_net -net M05_ARESETN_i [get_bd_pins M05_ARESETN]  [get_bd_pins axi_interconnect_0/M05_ARESETN]
## connect_bd_net -net M06_ARESETN_i [get_bd_pins M06_ARESETN]  [get_bd_pins axi_interconnect_0/M06_ARESETN] 
## connect_bd_net -net M07_ARESETN_i [get_bd_pins M07_ARESETN]  [get_bd_pins axi_interconnect_0/M07_ARESETN]
## 
##   connect_bd_net -net axis_10g_clk_1 [get_bd_pins axis_datapath_aclk] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axis_dwidth_dma_rx/aclk] [get_bd_pins axis_dwidth_dma_tx/aclk] [get_bd_pins axis_fifo_10g_rx/s_axis_aclk] [get_bd_pins axis_fifo_10g_tx/m_axis_aclk]
##   
##   connect_bd_net -net axis_rx_sys_reset_0_peripheral_aresetn [get_bd_pins axis_datapath_aresetn] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axis_dwidth_dma_rx/aresetn] [get_bd_pins axis_dwidth_dma_tx/aresetn] [get_bd_pins axis_fifo_10g_rx/s_axis_aresetn] [get_bd_pins axis_fifo_10g_tx/m_axis_aresetn]
##   
##   connect_bd_net -net axis_tx_sys_reset_0_peripheral_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axis_fifo_10g_rx/m_axis_aresetn] [get_bd_pins axis_fifo_10g_tx/s_axis_aresetn] [get_bd_pins pcie_reset_inv/Res]
## 
##   connect_bd_net -net pcie3_7x_1_user_clk [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axis_fifo_10g_rx/m_axis_aclk] [get_bd_pins axis_fifo_10g_tx/s_axis_aclk] [get_bd_pins nf_riffa_dma_1/user_clk] [get_bd_pins pcie3_7x_1/user_clk]
##   
##   connect_bd_net -net pcie3_7x_1_user_lnk_up [get_bd_pins nf_riffa_dma_1/user_lnk_up] [get_bd_pins pcie3_7x_1/user_lnk_up]
##   connect_bd_net -net pcie3_7x_1_user_reset [get_bd_pins pcie_reset_inv/Op1] [get_bd_pins nf_riffa_dma_1/user_reset] [get_bd_pins pcie3_7x_1/user_reset]
##   connect_bd_net -net sys_clk_1 [get_bd_pins sys_clk] [get_bd_pins pcie3_7x_1/sys_clk]
##   connect_bd_net -net sys_reset_1 [get_bd_pins sys_reset] [get_bd_pins pcie3_7x_1/sys_reset]
##   
##   # Restore current instance
##   current_bd_instance $oldCurInst
## }
## proc create_root_design { parentCell } {
## 
##   if { $parentCell eq "" } {
##      set parentCell [get_bd_cells /]
##   }
## 
##   # Get object for parentCell
##   set parentObj [get_bd_cells $parentCell]
##   if { $parentObj == "" } {
##      puts "ERROR: Unable to find parent cell <$parentCell>!"
##      return
##   }
## 
##   # Make sure parentObj is hier blk
##   set parentType [get_property TYPE $parentObj]
##   if { $parentType ne "hier" } {
##      puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
##      return
##   }
## 
##   # Save current instance; Restore later
##   set oldCurInst [current_bd_instance .]
## 
##   # Set parent object as current
##   current_bd_instance $parentObj
## 
## 
##   # Create interface ports
##   set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M00_AXI
##   set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M01_AXI
##   set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M02_AXI
##   set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M03_AXI
##   set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M04_AXI
##   set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M05_AXI
##   set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M06_AXI
##   set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ]
##   set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE}  ] $M07_AXI
##   set iic_fpga [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga ]
##   set m_axis_dma_tx [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma_tx ]
##   set pcie_7x_mgt [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_7x_mgt ]
##   set s_axis_dma_rx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma_rx ]
##   set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} CONFIG.HAS_TREADY {1} CONFIG.HAS_TSTRB {0} CONFIG.LAYERED_METADATA {undef} CONFIG.PHASE {0.000} CONFIG.TDATA_NUM_BYTES {32} CONFIG.TDEST_WIDTH {0} CONFIG.TID_WIDTH {0} CONFIG.TUSER_WIDTH {128}  ] $s_axis_dma_rx
##   set uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart ]
## 
##   # Create ports
##   set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ]
##   set axi_lite_aresetn [ create_bd_port -dir I -type rst axi_lite_aresetn ]
##   set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}] $axi_lite_aresetn 
##   set axis_datapath_aclk [ create_bd_port -dir I -type clk axis_datapath_aclk ]
##   set axis_datapath_aresetn [ create_bd_port -dir I -type rst axis_datapath_aresetn ]
##   set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $axis_datapath_aresetn
##   set iic_reset [ create_bd_port -dir O -from 1 -to 0 iic_reset ]
##   set sys_clk [ create_bd_port -dir I -type clk sys_clk ]
##   set_property -dict [ list CONFIG.FREQ_HZ {100000000}  ] $sys_clk
##   set sys_reset [ create_bd_port -dir I -type rst sys_reset ]
##   set_property -dict [ list CONFIG.POLARITY {ACTIVE_HIGH}  ] $sys_reset
## 
## 
## 
##   # Create instance: dma_sub
##   create_hier_cell_dma_sub [current_bd_instance .] dma_sub
## 
##   # Create instance: nf_mbsys
##   create_hier_cell_nf_mbsys [current_bd_instance .] nf_mbsys
## 
##   # Create interface connections
##   connect_bd_intf_net -intf_net dma_sub_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins dma_sub/M00_AXI]
##   connect_bd_intf_net -intf_net dma_sub_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins dma_sub/M01_AXI]
##   connect_bd_intf_net -intf_net dma_sub_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins dma_sub/M02_AXI]
##   connect_bd_intf_net -intf_net dma_sub_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins dma_sub/M03_AXI]
##   connect_bd_intf_net -intf_net dma_sub_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins dma_sub/M04_AXI]
##   connect_bd_intf_net -intf_net dma_sub_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins dma_sub/M05_AXI]
##   connect_bd_intf_net -intf_net dma_sub_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins dma_sub/M06_AXI]
##   connect_bd_intf_net -intf_net dma_sub_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins dma_sub/M07_AXI]
##   connect_bd_intf_net -intf_net dma_sub_m_axis_dma_tx [get_bd_intf_ports m_axis_dma_tx] [get_bd_intf_pins dma_sub/m_axis_dma_tx]
##   connect_bd_intf_net -intf_net dma_sub_pcie_7x_mgt [get_bd_intf_ports pcie_7x_mgt] [get_bd_intf_pins dma_sub/pcie_7x_mgt]
##   connect_bd_intf_net -intf_net nf_mbsys_iic_fpga [get_bd_intf_ports iic_fpga] [get_bd_intf_pins nf_mbsys/iic_fpga]
##   connect_bd_intf_net -intf_net nf_mbsys_uart [get_bd_intf_ports uart] [get_bd_intf_pins nf_mbsys/uart]
##   connect_bd_intf_net -intf_net s_axis_dma_rx_1 [get_bd_intf_ports s_axis_dma_rx] [get_bd_intf_pins dma_sub/s_axis_dma_rx]
## 
##   # Create port connections
##   connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk] [get_bd_pins dma_sub/axi_lite_aclk]
##   connect_bd_net -net axi_lite_aresetn_1 [get_bd_ports axi_lite_aresetn] [get_bd_pins dma_sub/axi_lite_aresetn]
##   connect_bd_net -net axis_datapath_aclk_1 [get_bd_ports axis_datapath_aclk] [get_bd_pins dma_sub/axis_datapath_aclk] [get_bd_pins dma_sub/M00_ACLK] [get_bd_pins dma_sub/M01_ACLK] [get_bd_pins dma_sub/M02_ACLK] [get_bd_pins dma_sub/M03_ACLK] [get_bd_pins dma_sub/M04_ACLK] [get_bd_pins dma_sub/M05_ACLK] [get_bd_pins dma_sub/M06_ACLK] [get_bd_pins dma_sub/M07_ACLK] 
##   connect_bd_net -net axis_datapath_aresetn_1 [get_bd_ports axis_datapath_aresetn] [get_bd_pins dma_sub/axis_datapath_aresetn]  [get_bd_pins dma_sub/M00_ARESETN] [get_bd_pins dma_sub/M01_ARESETN] [get_bd_pins dma_sub/M02_ARESETN] [get_bd_pins dma_sub/M03_ARESETN] [get_bd_pins dma_sub/M04_ARESETN] [get_bd_pins dma_sub/M05_ARESETN] [get_bd_pins dma_sub/M06_ARESETN] [get_bd_pins dma_sub/M07_ARESETN]
##   connect_bd_net -net nf_mbsys_iic_reset [get_bd_ports iic_reset] [get_bd_pins nf_mbsys/iic_reset]
##   connect_bd_net -net sys_clk_1 [get_bd_ports sys_clk] [get_bd_pins dma_sub/sys_clk] [get_bd_pins nf_mbsys/sysclk]
##   connect_bd_net -net sys_reset_1 [get_bd_ports sys_reset] [get_bd_pins dma_sub/sys_reset] [get_bd_pins nf_mbsys/reset]
## 
## 
##   # Create address segments
##   source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl
##   create_bd_addr_seg -range $M00_SIZEADDR -offset $M00_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg
##   create_bd_addr_seg -range $M01_SIZEADDR -offset $M01_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M01_AXI/Reg] SEG_M01_AXI_Reg
##   create_bd_addr_seg -range $M02_SIZEADDR -offset $M02_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M02_AXI/Reg] SEG_M02_AXI_Reg
##   create_bd_addr_seg -range $M03_SIZEADDR -offset $M03_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M03_AXI/Reg] SEG_M03_AXI_Reg
##   create_bd_addr_seg -range $M04_SIZEADDR -offset $M04_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M04_AXI/Reg] SEG_M04_AXI_Reg
##   create_bd_addr_seg -range $M05_SIZEADDR -offset $M05_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M05_AXI/Reg] SEG_M05_AXI_Reg
##   create_bd_addr_seg -range $M06_SIZEADDR -offset $M06_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M06_AXI/Reg] SEG_M06_AXI_Reg
##   create_bd_addr_seg -range $M07_SIZEADDR -offset $M07_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M07_AXI/Reg] SEG_M07_AXI_Reg
##   create_bd_addr_seg -range $M08_SIZEADDR -offset $M08_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs  dma_sub/nf_riffa_dma_1/s_axi_lite/reg0] SEG_nf_riffa_dma_1_reg0
##   
##   create_bd_addr_seg -range $MICROBLAZE_AXI_IIC_SIZEADDR -offset $MICROBLAZE_AXI_IIC_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg
##   create_bd_addr_seg -range $MICROBLAZE_UARTLITE_SIZEADDR -offset $MICROBLAZE_UARTLITE_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
##   create_bd_addr_seg -range $MICROBLAZE_DLMB_BRAM_SIZEADDR -offset $MICROBLAZE_DLMB_BRAM_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem
##   create_bd_addr_seg -range $MICROBLAZE_ILMB_BRAM_SIZEADDR -offset $MICROBLAZE_ILMB_BRAM_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Instruction] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem
##   create_bd_addr_seg -range $MICROBLAZE_AXI_INTC_SIZEADDR -offset $MICROBLAZE_AXI_INTC_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_axi_intc/s_axi/Reg] SEG_microblaze_0_axi_intc_Reg
##   
## 
##   # Restore current instance
##   current_bd_instance $oldCurInst
## 
##   save_bd_design
## }
## create_root_design ""
CRITICAL WARNING: [BD 41-737] Cannot set the parameter FREQ_HZ on /dma_sub/nf_riffa_dma_1/s_axi_lite. It is read-only.
create_bd_cell: Time (s): cpu = 00:00:22 ; elapsed = 00:00:58 . Memory (MB): peak = 1703.020 ; gain = 287.730 ; free physical = 7629 ; free virtual = 15272
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '10.000' to '10.0' has been ignored for IP 'nf_mbsys/clk_wiz_1'
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
### set M00_BASEADDR 0x44000000
### set M00_HIGHADDR 0x44000FFF
### set M00_SIZEADDR 0x1000
### set M01_BASEADDR 0x44010000
### set M01_HIGHADDR 0x44010FFF
### set M01_SIZEADDR 0x1000
### set M02_BASEADDR 0x44020000
### set M02_HIGHADDR 0x44020FFF
### set M02_SIZEADDR 0x1000
### set M03_BASEADDR 0x44030000
### set M03_HIGHADDR 0x44030FFF
### set M03_SIZEADDR 0x1000
### set M04_BASEADDR 0x44040000
### set M04_HIGHADDR 0x44040FFF
### set M04_SIZEADDR 0x1000
### set M05_BASEADDR 0x44050000
### set M05_HIGHADDR 0x44050FFF
### set M05_SIZEADDR 0x1000
### set M06_BASEADDR 0x44060000
### set M06_HIGHADDR 0x44060FFF
### set M06_SIZEADDR 0x1000
### set M07_BASEADDR 0x44070000
### set M07_HIGHADDR 0x44070FFF
### set M07_SIZEADDR 0x1000
### set M08_BASEADDR 0x44080000
### set M08_HIGHADDR 0x44080FFF
### set M08_SIZEADDR 0x1000
### set IDENTIFIER_BASEADDR $M00_BASEADDR
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
Wrote  : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd> 
# create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
# set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci]
# reset_target all [get_ips nf_sume_sdnet_ip]
# generate_target all [get_ips nf_sume_sdnet_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_sume_sdnet_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_sume_sdnet_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_sume_sdnet_ip'...
# source ./create_ip/nf_10ge_interface.tcl
## set sharedLogic          "FALSE"
## set tdataWidth           256
## set convWidth [expr $tdataWidth/8]
## if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } {
##    set supportLevel 1
## } else {
##    set supportLevel 0
## }
## create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_nonshared
WARNING: [IP_Flow 19-4832] The IP name 'axi_10g_ethernet_nonshared' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues.
## set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_nonshared]
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
## set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_nonshared]
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
## set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_nonshared]
## set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_nonshared]
## set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_nonshared]
## set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_nonshared]
## set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_nonshared.xci]
## reset_target all [get_ips axi_10g_ethernet_nonshared]
## generate_target all [get_ips axi_10g_ethernet_nonshared]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_10g_ethernet_nonshared'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_10g_ethernet_nonshared'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_10g_ethernet_nonshared'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_10g_ethernet_nonshared'...
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/hw_handoff/axi_10g_ethernet_nonshared.hwh
Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/hw_handoff/axi_10g_ethernet_nonshared_bd.tcl
Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/synth/axi_10g_ethernet_nonshared.hwdef
generate_target: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1942.414 ; gain = 43.977 ; free physical = 7369 ; free virtual = 15056
## create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_status
## set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Performance_Options {First_Word_Fall_Through}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Input_Data_Width {458} CONFIG.Input_Depth {16}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Reset_Pin {false}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Output_Data_Width {458} CONFIG.Output_Depth {16}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Full_Flags_Reset_Value {0}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Use_Dout_Reset {false}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Data_Count_Width {4}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Write_Data_Count_Width {4}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Read_Data_Count_Width {4}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Full_Threshold_Assert_Value {15}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Full_Threshold_Negate_Value {14}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Empty_Threshold_Assert_Value {4}] [get_ips fifo_generator_status]
## set_property -dict [list CONFIG.Empty_Threshold_Negate_Value {5}] [get_ips fifo_generator_status]
## set_property generate_synth_checkpoint false [get_files fifo_generator_status.xci]
## reset_target all [get_ips fifo_generator_status]
## generate_target all [get_ips fifo_generator_status]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fifo_generator_status'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_generator_status'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fifo_generator_status'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fifo_generator_status'...
## create_ip -name util_vector_logic -vendor xilinx.com -library ip -version 2.0 -module_name inverter_0
WARNING: [Coretcl 2-1618] The 'xilinx.com:ip:util_vector_logic:2.0' IP is intended for use in IPI only.
## set_property -dict [list CONFIG.C_SIZE {1}] [get_ips inverter_0]
## set_property -dict [list CONFIG.C_OPERATION {not}] [get_ips inverter_0]
## set_property generate_synth_checkpoint false [get_files inverter_0.xci]
## reset_target all [get_ips inverter_0]
## generate_target all [get_ips inverter_0]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'inverter_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'inverter_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'inverter_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'inverter_0'...
## create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_1_9
## set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM} CONFIG.Performance_Options {First_Word_Fall_Through} CONFIG.Input_Data_Width {1} CONFIG.Input_Depth {16} CONFIG.Output_Data_Width {1} CONFIG.Output_Depth {16} CONFIG.Data_Count_Width {4} CONFIG.Write_Data_Count_Width {4} CONFIG.Read_Data_Count_Width {4} CONFIG.Full_Threshold_Assert_Value {13} CONFIG.Full_Threshold_Negate_Value {12}] [get_ips fifo_generator_1_9]
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Assert_Value' from '15' to '13' has been ignored for IP 'fifo_generator_1_9'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Negate_Value' from '14' to '12' has been ignored for IP 'fifo_generator_1_9'
## set_property generate_synth_checkpoint false [get_files fifo_generator_1_9.xci]
## reset_target all [get_ips fifo_generator_1_9]
## generate_target all [get_ips fifo_generator_1_9]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fifo_generator_1_9'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_generator_1_9'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fifo_generator_1_9'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fifo_generator_1_9'...
# create_ip -name nf_10ge_interface -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_ip
# set_property generate_synth_checkpoint false [get_files nf_10g_interface_ip.xci]
# reset_target all [get_ips nf_10g_interface_ip]
# generate_target all [get_ips nf_10g_interface_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_10g_interface_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_10g_interface_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_10g_interface_ip'...
generate_target: Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1987.223 ; gain = 38.785 ; free physical = 7304 ; free virtual = 15049
# source ./create_ip/nf_10ge_interface_shared.tcl
## set sharedLogic         "TRUE"
## set tdataWidth          256
## set convWidth [expr $tdataWidth/8]
## if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } {
##    set supportLevel 1
## } else {
##    set supportLevel 0
## }
## create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_shared
## set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_shared]
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
## set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_shared]
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
## set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_shared]
WARNING: [BD 41-1306] The connection to interface pin /xpcs/refclk_p is being overridden by the user. This pin will not be connected as a part of interface connection refclk_diff_port
WARNING: [BD 41-1306] The connection to interface pin /xpcs/refclk_n is being overridden by the user. This pin will not be connected as a part of interface connection refclk_diff_port
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
## set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_shared]
## set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_shared]
## set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_shared]
## set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_shared.xci]
## reset_target all [get_ips axi_10g_ethernet_shared]
## generate_target all [get_ips axi_10g_ethernet_shared]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_10g_ethernet_shared'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_10g_ethernet_shared'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_10g_ethernet_shared'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_10g_ethernet_shared'...
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/hw_handoff/axi_10g_ethernet_shared.hwh
Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/hw_handoff/axi_10g_ethernet_shared_bd.tcl
Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/synth/axi_10g_ethernet_shared.hwdef
generate_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2002.555 ; gain = 15.328 ; free physical = 7245 ; free virtual = 14996
# create_ip -name nf_10ge_interface_shared -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_shared_ip
WARNING: [IP_Flow 19-4832] The IP name 'nf_10g_interface_shared_ip' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues.
# set_property generate_synth_checkpoint false [get_files nf_10g_interface_shared_ip.xci]
# reset_target all [get_ips nf_10g_interface_shared_ip]
# generate_target all [get_ips nf_10g_interface_shared_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_10g_interface_shared_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_10g_interface_shared_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_10g_interface_shared_ip'...
generate_target: Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 2040.082 ; gain = 37.527 ; free physical = 7228 ; free virtual = 14997
# create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip
# set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip]
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '5.000' to '5.0' has been ignored for IP 'clk_wiz_ip'
# set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci]
# reset_target all [get_ips clk_wiz_ip]
# generate_target all [get_ips clk_wiz_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_ip'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_ip'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_ip'...
# create_ip -name proc_sys_reset -vendor xilinx.com -library ip -version 5.0 -module_name proc_sys_reset_ip
# set_property -dict [list CONFIG.C_EXT_RESET_HIGH {0} CONFIG.C_AUX_RESET_HIGH {0}] [get_ips proc_sys_reset_ip]
# set_property -dict [list CONFIG.C_NUM_PERP_RST {1} CONFIG.C_NUM_PERP_ARESETN {1}] [get_ips proc_sys_reset_ip]
# set_property generate_synth_checkpoint false [get_files proc_sys_reset_ip.xci]
# reset_target all [get_ips proc_sys_reset_ip]
# generate_target all [get_ips proc_sys_reset_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'proc_sys_reset_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'proc_sys_reset_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'proc_sys_reset_ip'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'proc_sys_reset_ip'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'proc_sys_reset_ip'...
# create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip
# set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {4096} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip]
# set_property generate_synth_checkpoint false [get_files identifier_ip.xci]
# reset_target all [get_ips identifier_ip]
# generate_target all [get_ips identifier_ip]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'identifier_ip'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'identifier_ip'...
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'identifier_ip'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'identifier_ip'...
# read_verilog "./hdl/axi_clocking.v"
# read_verilog "./hdl/nf_datapath.v"
# read_verilog "./hdl/top.v"
# create_run -flow {Vivado Synthesis 2018} synth
Run is defaulting to srcset: sources_1
Run is defaulting to constrset: constraints
Run is defaulting to part: xc7vx690tffg1761-3
# create_run impl -parent_run synth -flow {Vivado Implementation 2018} 
Run is defaulting to parent run srcset: sources_1
Run is defaulting to parent run constrset: constraints
Run is defaulting to parent run part: xc7vx690tffg1761-3
# set_property steps.phys_opt_design.is_enabled true [get_runs impl_1]
# set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE ExploreWithHoldFix [get_runs impl_1]
# set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
# set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.is_enabled true [get_runs impl_1]
# set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
# set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
# launch_runs synth
INFO: [xilinx.com:ip:axi_intc:4.1-1] /nf_mbsys/mbsys/microblaze_0_axi_intc: The AXI INTC core has been configured to operate with synchronous clocks.
INFO: [xilinx.com:ip:axi_intc:4.1-1] /nf_mbsys/mbsys/microblaze_0_axi_intc: The AXI INTC core has been configured to operate with synchronous clocks.
Wrote  : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd> 
VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v
VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/sim/control_sub.v
VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hdl/control_sub_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/axi_iic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/axi_uartlite_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/clk_wiz_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/mdm_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_axi_intc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_xlconcat .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/rst_clk_wiz_1_100M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/pcie_reset_inv .
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_dwidth_dma_tx .
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_dwidth_dma_rx .
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_fifo_10g_rx .
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_fifo_10g_tx .
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/nf_riffa_dma_1 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_clock_converter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/pcie3_7x_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/s00_couplers/auto_cc .
Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hw_handoff/control_sub.hwh
Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hw_handoff/control_sub_bd.tcl
Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.hwdef
[Wed Jul 24 22:49:27 2019] Launched control_sub_m08_data_fifo_0_synth_1, control_sub_m01_data_fifo_0_synth_1, control_sub_m00_data_fifo_0_synth_1, control_sub_mdm_1_0_synth_1, control_sub_clk_wiz_1_0_synth_1, control_sub_axi_uartlite_0_0_synth_1, control_sub_axi_iic_0_0_synth_1, control_sub_ilmb_v10_0_synth_1, control_sub_lmb_bram_0_synth_1, control_sub_xbar_1_synth_1, control_sub_pcie_reset_inv_0_synth_1, control_sub_axis_dwidth_dma_tx_0_synth_1, control_sub_axis_dwidth_dma_rx_0_synth_1, control_sub_axis_fifo_10g_rx_0_synth_1, control_sub_axis_fifo_10g_tx_0_synth_1, control_sub_nf_riffa_dma_1_0_synth_1, control_sub_axi_clock_converter_0_0_synth_1, control_sub_pcie3_7x_1_0_synth_1, control_sub_xbar_0_synth_1, control_sub_microblaze_0_0_synth_1, control_sub_microblaze_0_axi_intc_0_synth_1, control_sub_microblaze_0_xlconcat_0_synth_1, control_sub_rst_clk_wiz_1_100M_0_synth_1, control_sub_dlmb_bram_if_cntlr_0_synth_1, control_sub_dlmb_v10_0_synth_1, control_sub_ilmb_bram_if_cntlr_0_synth_1, control_sub_m06_data_fifo_0_synth_1, control_sub_m07_data_fifo_0_synth_1, control_sub_m02_data_fifo_0_synth_1, control_sub_m03_data_fifo_0_synth_1, control_sub_m04_data_fifo_0_synth_1, control_sub_m05_data_fifo_0_synth_1, control_sub_s00_data_fifo_0_synth_1, control_sub_auto_cc_0_synth_1...
Run output will be captured here:
control_sub_m08_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m08_data_fifo_0_synth_1/runme.log
control_sub_m01_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m01_data_fifo_0_synth_1/runme.log
control_sub_m00_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m00_data_fifo_0_synth_1/runme.log
control_sub_mdm_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_mdm_1_0_synth_1/runme.log
control_sub_clk_wiz_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_clk_wiz_1_0_synth_1/runme.log
control_sub_axi_uartlite_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_uartlite_0_0_synth_1/runme.log
control_sub_axi_iic_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_iic_0_0_synth_1/runme.log
control_sub_ilmb_v10_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_v10_0_synth_1/runme.log
control_sub_lmb_bram_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_lmb_bram_0_synth_1/runme.log
control_sub_xbar_1_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_1_synth_1/runme.log
control_sub_pcie_reset_inv_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie_reset_inv_0_synth_1/runme.log
control_sub_axis_dwidth_dma_tx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_tx_0_synth_1/runme.log
control_sub_axis_dwidth_dma_rx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_rx_0_synth_1/runme.log
control_sub_axis_fifo_10g_rx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_rx_0_synth_1/runme.log
control_sub_axis_fifo_10g_tx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_tx_0_synth_1/runme.log
control_sub_nf_riffa_dma_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_nf_riffa_dma_1_0_synth_1/runme.log
control_sub_axi_clock_converter_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_clock_converter_0_0_synth_1/runme.log
control_sub_pcie3_7x_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie3_7x_1_0_synth_1/runme.log
control_sub_xbar_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_0_synth_1/runme.log
control_sub_microblaze_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_0_synth_1/runme.log
control_sub_microblaze_0_axi_intc_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_axi_intc_0_synth_1/runme.log
control_sub_microblaze_0_xlconcat_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_xlconcat_0_synth_1/runme.log
control_sub_rst_clk_wiz_1_100M_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_rst_clk_wiz_1_100M_0_synth_1/runme.log
control_sub_dlmb_bram_if_cntlr_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_bram_if_cntlr_0_synth_1/runme.log
control_sub_dlmb_v10_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_v10_0_synth_1/runme.log
control_sub_ilmb_bram_if_cntlr_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_bram_if_cntlr_0_synth_1/runme.log
control_sub_m06_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m06_data_fifo_0_synth_1/runme.log
control_sub_m07_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m07_data_fifo_0_synth_1/runme.log
control_sub_m02_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log
control_sub_m03_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m03_data_fifo_0_synth_1/runme.log
control_sub_m04_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m04_data_fifo_0_synth_1/runme.log
control_sub_m05_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m05_data_fifo_0_synth_1/runme.log
control_sub_s00_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_s00_data_fifo_0_synth_1/runme.log
control_sub_auto_cc_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_auto_cc_0_synth_1/runme.log
[Wed Jul 24 22:49:27 2019] Launched synth...
Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log
launch_runs: Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2872.781 ; gain = 832.695 ; free physical = 7008 ; free virtual = 14853
# wait_on_run synth
[Wed Jul 24 22:49:27 2019] Waiting for synth to finish...

*** Running vivado
    with args -log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl


****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source top.tcl -notrace
Command: synth_design -top top -part xc7vx690tffg1761-3
Starting synth_design
WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/identifier_ip.xci

Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx690t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 339 
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_single [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_gray [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_handshake [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:469]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_pulse [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:715]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_array_single [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_sync_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_async_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1171]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_base [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_counter_updn [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_reg_vec [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_reg_bit [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_reg_pipe_bit [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1774]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_sync [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_async [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_axis [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2076]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_base [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
WARNING: [Synth 8-2490] overwriting previous definition of module asym_bwe_bb [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6541]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_dpdistram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6600]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_dprom [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6734]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_sdpram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6888]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_spram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7043]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_sprom [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7189]
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_tdpram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325]
WARNING: [Synth 8-2507] parameter declaration becomes local in small_fifo with formal parameter declaration list [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:67]
WARNING: [Synth 8-2507] parameter declaration becomes local in sss_small_fifo with formal parameter declaration list [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_small_fifo.v:69]
WARNING: [Synth 8-2306] macro REG_ID_DEFAULT redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues_cpu_regs_defines.v:44]
WARNING: [Synth 8-2306] macro REG_ID_DEFAULT redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:44]
WARNING: [Synth 8-2306] macro REG_PKTIN_ADDR redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:75]
WARNING: [Synth 8-2306] macro REG_PKTOUT_ADDR redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:80]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:23 . Memory (MB): peak = 1458.586 ; gain = 136.371 ; free physical = 6409 ; free virtual = 14391
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'top' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:43]
	Parameter C_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter IF_SFP0 bound to: 8'b00000001 
	Parameter IF_SFP1 bound to: 8'b00000100 
	Parameter IF_SFP2 bound to: 8'b00010000 
	Parameter IF_SFP3 bound to: 8'b01000000 
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:152]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:153]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:154]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:155]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:156]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:157]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:166]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:167]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:168]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:169]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:170]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:171]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:180]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:181]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:182]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:183]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:184]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:185]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:194]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:195]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:196]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:197]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:198]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:199]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:259]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:260]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:261]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:262]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:263]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:264]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:265]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:266]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:267]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:268]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:269]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:270]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:271]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:272]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:273]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:274]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:275]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:276]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:277]
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:431]
INFO: [Synth 8-6157] synthesizing module 'OBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:27275]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DRIVE bound to: 12 - type: integer 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-6155] done synthesizing module 'OBUF' (1#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:27275]
INFO: [Synth 8-6157] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19473]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: TRUE - type: string 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-6155] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19473]
INFO: [Synth 8-6157] synthesizing module 'IBUFDS_GTE2' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19625]
	Parameter CLKCM_CFG bound to: TRUE - type: string 
	Parameter CLKRCV_TRST bound to: TRUE - type: string 
	Parameter CLKSWING_CFG bound to: 2'b11 
INFO: [Synth 8-6155] done synthesizing module 'IBUFDS_GTE2' (3#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19625]
INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:22660]
	Parameter DRIVE bound to: 12 - type: integer 
	Parameter IBUF_LOW_PWR bound to: TRUE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (4#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:22660]
INFO: [Synth 8-6157] synthesizing module 'axi_clocking' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/axi_clocking.v:44]
INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: FALSE - type: string 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: TRUE - type: string 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (5#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488]
INFO: [Synth 8-6157] synthesizing module 'clk_wiz_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.v:70]
INFO: [Synth 8-6157] synthesizing module 'clk_wiz_ip_clk_wiz' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:68]
INFO: [Synth 8-5534] Detected attribute (* KEEP = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:126]
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:126]
INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762]
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
	Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: float 
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
	Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float 
	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 
	Parameter CLKOUT0_DIVIDE_F bound to: 5.000000 - type: float 
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT4_CASCADE bound to: FALSE - type: string 
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string 
	Parameter COMPENSATION bound to: ZHOLD - type: string 
	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
	Parameter IS_PSEN_INVERTED bound to: 1'b0 
	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
	Parameter IS_RST_INVERTED bound to: 1'b0 
	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
	Parameter REF_JITTER2 bound to: 0.010000 - type: float 
	Parameter SS_EN bound to: FALSE - type: string 
	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
	Parameter STARTUP_WAIT bound to: FALSE - type: string 
INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (6#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (7#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609]
INFO: [Synth 8-6157] synthesizing module 'BUFGCE' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:619]
	Parameter CE_TYPE bound to: SYNC - type: string 
	Parameter IS_CE_INVERTED bound to: 1'b0 
	Parameter IS_I_INVERTED bound to: 1'b0 
INFO: [Synth 8-6155] done synthesizing module 'BUFGCE' (8#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:619]
INFO: [Synth 8-6157] synthesizing module 'BUFH' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:808]
INFO: [Synth 8-6155] done synthesizing module 'BUFH' (9#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:808]
INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_ip_clk_wiz' (10#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:68]
INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_ip' (11#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.v:70]
INFO: [Synth 8-6155] done synthesizing module 'axi_clocking' (12#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/axi_clocking.v:44]
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:74]
	Parameter C_FAMILY bound to: virtex7 - type: string 
	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:129]
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
	Parameter C_FAMILY bound to: virtex7 - type: string 
	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
	Parameter IS_C_INVERTED bound to: 1'b0 
	Parameter IS_D_INVERTED bound to: 1'b0 
	Parameter IS_R_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1392]
	Parameter INIT bound to: 1'b1 
	Parameter IS_C_INVERTED bound to: 1'b0 
	Parameter IS_D_INVERTED bound to: 1'b0 
	Parameter IS_R_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1408]
	Parameter INIT bound to: 1'b0 
	Parameter IS_C_INVERTED bound to: 1'b0 
	Parameter IS_D_INVERTED bound to: 1'b0 
	Parameter IS_R_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1434]
	Parameter INIT bound to: 1'b1 
	Parameter IS_C_INVERTED bound to: 1'b0 
	Parameter IS_D_INVERTED bound to: 1'b0 
	Parameter IS_R_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1457]
	Parameter INIT bound to: 1'b0 
	Parameter IS_C_INVERTED bound to: 1'b0 
	Parameter IS_D_INVERTED bound to: 1'b0 
	Parameter IS_R_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1481]
INFO: [Synth 8-638] synthesizing module 'lpf' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
INFO: [Synth 8-3491] module 'SRL16' declared at '/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:868]
INFO: [Synth 8-6157] synthesizing module 'SRL16' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695]
	Parameter INIT bound to: 16'b0000000000000000 
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (13#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:106]
	Parameter C_CDC_TYPE bound to: 1 - type: integer 
	Parameter C_RESET_STATE bound to: 0 - type: integer 
	Parameter C_SINGLE_BIT bound to: 1 - type: integer 
	Parameter C_FLOP_INPUT bound to: 0 - type: integer 
	Parameter C_VECTOR_WIDTH bound to: 2 - type: integer 
	Parameter C_MTBF_STAGES bound to: 4 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:514]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:545]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:554]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:564]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:574]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:584]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (14#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-256] done synthesizing module 'lpf' (15#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
	Parameter C_SIZE bound to: 6 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (16#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (17#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (18#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset_ip' (19#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:74]
INFO: [Synth 8-6157] synthesizing module 'nf_datapath' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:44]
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer 
	Parameter C_BASEADDR bound to: 0 - type: integer 
	Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter NUM_QUEUES bound to: 5 - type: integer 
	Parameter DIGEST_WIDTH bound to: 80 - type: integer 
	Parameter C_AXIS_TUSER_DIGEST_WIDTH bound to: 304 - type: integer 
	Parameter Q_SIZE_WIDTH bound to: 16 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:194]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:195]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:196]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:197]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:198]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:199]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:201]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:202]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:203]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:204]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:205]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:206]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:209]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:210]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:211]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:212]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:213]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:321]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:322]
INFO: [Synth 8-6157] synthesizing module 'input_arbiter_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/synth/input_arbiter_ip.v:57]
INFO: [Synth 8-6157] synthesizing module 'input_arbiter' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:55]
	Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter NUM_QUEUES bound to: 5 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer 
	Parameter C_BASEADDR bound to: 0 - type: integer 
	Parameter NUM_QUEUES_WIDTH bound to: 3 - type: integer 
	Parameter NUM_STATES bound to: 1 - type: integer 
	Parameter IDLE bound to: 0 - type: integer 
	Parameter WR_PKT bound to: 1 - type: integer 
	Parameter MAX_PKT_SIZE bound to: 2000 - type: integer 
	Parameter IN_FIFO_DEPTH_BIT bound to: 6 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'fallthrough_small_fifo' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/fallthrough_small_fifo.v:46]
	Parameter WIDTH bound to: 417 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 6 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'small_fifo' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:44]
	Parameter WIDTH bound to: 417 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 6 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer 
	Parameter MAX_DEPTH bound to: 64 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'small_fifo' (20#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:44]
INFO: [Synth 8-6155] done synthesizing module 'fallthrough_small_fifo' (21#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/fallthrough_small_fifo.v:46]
INFO: [Synth 8-6157] synthesizing module 'input_arbiter_cpu_regs' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:42]
	Parameter C_BASE_ADDRESS bound to: 0 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer 
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:305]
INFO: [Synth 8-6155] done synthesizing module 'input_arbiter_cpu_regs' (22#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:42]
INFO: [Synth 8-6155] done synthesizing module 'input_arbiter' (23#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:55]
INFO: [Synth 8-6155] done synthesizing module 'input_arbiter_ip' (24#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/synth/input_arbiter_ip.v:57]
INFO: [Synth 8-6157] synthesizing module 'nf_sume_sdnet_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/synth/nf_sume_sdnet_ip.v:57]
INFO: [Synth 8-6157] synthesizing module 'nf_sume_sdnet' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:44]
	Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 304 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer 
	Parameter SDNET_ADDR_WIDTH bound to: 12 - type: integer 
	Parameter DIGEST_WIDTH bound to: 256 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'sume_to_sdnet' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:41]
	Parameter FIRST bound to: 0 - type: integer 
	Parameter WAIT bound to: 1 - type: integer 
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:72]
INFO: [Synth 8-6155] done synthesizing module 'sume_to_sdnet' (25#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:41]
INFO: [Synth 8-6157] synthesizing module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:36]
INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_line' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v:40]
INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_line' (26#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v:40]
INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_lookup' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v:40]
INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_lookup' (27#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v:40]
INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_control' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v:40]
INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_control' (28#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v:40]
INFO: [Synth 8-6157] synthesizing module 'TopParser_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v:282]
INFO: [Synth 8-6155] done synthesizing module 'TopParser_t' (182#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v:282]
INFO: [Synth 8-6157] synthesizing module 'TopPipe_lvl_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v:178]
INFO: [Synth 8-6155] done synthesizing module 'TopPipe_lvl_t' (189#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v:178]
INFO: [Synth 8-6157] synthesizing module 'realmain_nat64_0_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/realmain_nat64_0_t.v:36]
	Parameter K bound to: 128 - type: integer 
	Parameter V bound to: 307 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_tdpram' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325]
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:467]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (191#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_tdpram' (192#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 

Warning: Trying to implement RAM in registers. Block RAM or DRAM implementation is not possible for one or more of the following reasons :
	1: Invalid write to RAM. 
	2: Unable to determine number of words or word size in RAM. 
	3: No valid read/write found for RAM. 
RAM dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'CamPtrBck_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
	1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process. 
	2: Unable to determine number of words or word size in RAM. 
	3: No valid read/write found for RAM. 
RAM "CamPtrBck_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'CamPtrFwd_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
	1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process. 
	2: Unable to determine number of words or word size in RAM. 
	3: No valid read/write found for RAM. 
RAM "CamPtrFwd_reg" dissolved into registers
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-6155] done synthesizing module 'realmain_nat64_0_t' (205#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_nat64_0_t.HDL/realmain_nat64_0_t.v:36]
INFO: [Synth 8-6157] synthesizing module 'TopPipe_lvl_0_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v:186]
INFO: [Synth 8-6155] done synthesizing module 'TopPipe_lvl_0_t' (319#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v:186]
INFO: [Synth 8-6157] synthesizing module 'realmain_lookup_table_0_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/realmain_lookup_table_0_t.v:36]
	Parameter K bound to: 48 - type: integer 
	Parameter V bound to: 3 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_tdpram__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325]
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:467]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized0' (320#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
INFO: [Common 17-14] Message 'Synth 8-5772' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_tdpram__parameterized0' (320#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325]

Warning: Trying to implement RAM in registers. Block RAM or DRAM implementation is not possible for one or more of the following reasons :
	1: Invalid write to RAM. 
	2: Unable to determine number of words or word size in RAM. 
	3: No valid read/write found for RAM. 
RAM dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'CamPtrBck_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
	1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process. 
	2: Unable to determine number of words or word size in RAM. 
	3: No valid read/write found for RAM. 
RAM "CamPtrBck_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'CamPtrFwd_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
	1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process. 
	2: Unable to determine number of words or word size in RAM. 
	3: No valid read/write found for RAM. 
RAM "CamPtrFwd_reg" dissolved into registers
INFO: [Synth 8-6155] done synthesizing module 'realmain_lookup_table_0_t' (333#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_lookup_table_0_t.HDL/realmain_lookup_table_0_t.v:36]
INFO: [Synth 8-6157] synthesizing module 'TopPipe_lvl_1_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_1_t.HDL/TopPipe_lvl_1_t.v:187]
INFO: [Synth 8-6155] done synthesizing module 'TopPipe_lvl_1_t' (366#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_1_t.HDL/TopPipe_lvl_1_t.v:187]
INFO: [Synth 8-6157] synthesizing module 'TopDeparser_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v:169]
INFO: [Synth 8-6155] done synthesizing module 'TopDeparser_t' (437#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v:169]
INFO: [Synth 8-6157] synthesizing module 'S_BRIDGER_for_realmain_nat64_0_tuple_in_request' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat64_0_tuple_in_request.v:36]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
	Parameter FIFO_MEMORY_TYPE bound to: 1651663213 - type: integer 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 128 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: std - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 128 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 3 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 48 - type: integer 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 128 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 128 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 3 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 48 - type: integer 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 32768 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 128 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 3 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 32768 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 128 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 128 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 128 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 128 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 128 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 128 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 48 - type: integer 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 2 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 128 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 128 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 128 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 128 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 128 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 128 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 128 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized1' (437#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
	Parameter DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
	Parameter REG_OUTPUT bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358]
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (438#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
	Parameter REG_WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (439#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
	Parameter DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
	Parameter REG_OUTPUT bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter WIDTH bound to: 9 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (439#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
	Parameter REG_WIDTH bound to: 9 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (439#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1638]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1663]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055]
	Parameter DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter INIT bound to: 32'sb00000000000000000000000000000000 
	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter DEF_VAL bound to: 1'b0 
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1107]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (440#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (441#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755]
	Parameter RST_VALUE bound to: 0 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (442#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
	Parameter COUNTER_WIDTH bound to: 9 - type: integer 
	Parameter RESET_VALUE bound to: 0 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (443#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
	Parameter COUNTER_WIDTH bound to: 8 - type: integer 
	Parameter RESET_VALUE bound to: 1 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (443#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
	Parameter COUNTER_WIDTH bound to: 8 - type: integer 
	Parameter RESET_VALUE bound to: 2 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (443#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (444#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async' (445#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
INFO: [Synth 8-6155] done synthesizing module 'S_BRIDGER_for_realmain_nat64_0_tuple_in_request' (446#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat64_0_tuple_in_request.v:36]
INFO: [Synth 8-6157] synthesizing module 'S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request.v:36]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
	Parameter FIFO_MEMORY_TYPE bound to: 1651663213 - type: integer 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 48 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 128 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: std - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 48 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 3 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 48 - type: integer 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
INFO: [Common 17-14] Message 'Synth 8-6104' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 48 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 128 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 48 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 3 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 48 - type: integer 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 12288 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 128 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 3 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 12288 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 48 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 48 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 48 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 48 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 48 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 48 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 48 - type: integer 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 2 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 48 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 48 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 48 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 48 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 48 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 48 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 48 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized2' (446#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized0' (446#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized0' (446#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
INFO: [Synth 8-6155] done synthesizing module 'S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request' (447#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request.v:36]
INFO: [Synth 8-6157] synthesizing module 'S_PROTOCOL_ADAPTER_INGRESS' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:36]
	Parameter IDLE bound to: 1 - type: integer 
	Parameter RX_SOF bound to: 2 - type: integer 
	Parameter RX_SOF_EOF bound to: 3 - type: integer 
	Parameter RX_PKT bound to: 4 - type: integer 
INFO: [Synth 8-4471] merging register 'tuple_out_control_VALID_reg' into 'packet_out_SOF_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:182]
WARNING: [Synth 8-6014] Unused sequential element tuple_out_control_VALID_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:182]
INFO: [Synth 8-6155] done synthesizing module 'S_PROTOCOL_ADAPTER_INGRESS' (448#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:36]
INFO: [Synth 8-6157] synthesizing module 'S_PROTOCOL_ADAPTER_EGRESS' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v:36]
INFO: [Synth 8-6155] done synthesizing module 'S_PROTOCOL_ADAPTER_EGRESS' (449#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v:36]
INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_TopParser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:40]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 129 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 266 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 1 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 129 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 266 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 512 - type: integer 
	Parameter FIFO_SIZE bound to: 136192 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 129 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 129 - type: integer 
	Parameter PF_THRESH_MIN bound to: 3 - type: integer 
	Parameter PF_THRESH_MAX bound to: 509 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 509 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 136192 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
	Parameter CLOCKING_MODE bound to: 0 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 266 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 266 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 266 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 9 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 266 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 266 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 266 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 9 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 2 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 266 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 266 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 266 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 266 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 266 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 266 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 266 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized3' (449#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst__parameterized0' (449#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
	Parameter COUNTER_WIDTH bound to: 10 - type: integer 
	Parameter RESET_VALUE bound to: 0 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (449#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
	Parameter COUNTER_WIDTH bound to: 9 - type: integer 
	Parameter RESET_VALUE bound to: 1 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (449#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
	Parameter COUNTER_WIDTH bound to: 9 - type: integer 
	Parameter RESET_VALUE bound to: 2 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized4' (449#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized1' (449#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync' (450#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 129 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: FWFT - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 1 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 1 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 129 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 1 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 1 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 512 - type: integer 
	Parameter FIFO_SIZE bound to: 512 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 127 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 127 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 507 - type: integer 
	Parameter PE_THRESH_MIN bound to: 5 - type: integer 
	Parameter PE_THRESH_MAX bound to: 507 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_LATENCY bound to: 2 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 512 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer 
	Parameter CLOCKING_MODE bound to: 0 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 1 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 1 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 9 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 1 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 1 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 9 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 2 - type: integer 
	Parameter WRITE_MODE_B bound to: 1 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 1 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 1 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 1 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 1 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 1 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: yes - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 5 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 1 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
WARNING: [Synth 8-6014] Unused sequential element gen_rd_b.gen_doutb_pipe.enb_pipe_reg[0] was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:2588]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized4' (450#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
	Parameter COUNTER_WIDTH bound to: 2 - type: integer 
	Parameter RESET_VALUE bound to: 0 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized5' (450#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized2' (450#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized0' (450#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 66 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 128 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 66 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 128 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 32768 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 66 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 66 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 32768 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 128 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 128 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 128 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 128 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 128 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 128 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 2 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 128 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 128 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 128 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 128 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 128 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 128 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 128 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized5' (450#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized3' (450#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized1' (450#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 21 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 21 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 21 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 21 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 5376 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 5376 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 21 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 21 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 21 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 21 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 21 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 21 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 1 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 21 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 21 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 21 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 21 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 21 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 21 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: yes - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 21 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized6' (450#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized4' (450#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized2' (450#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
WARNING: [Synth 8-6014] Unused sequential element h6yh8s25s00eto4748vc2qg_238_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:353]
WARNING: [Synth 8-6014] Unused sequential element fj7voukejze3zml5n3_451_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:341]
WARNING: [Synth 8-6014] Unused sequential element rto9gapnc0esfmfaalfney7_844_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:355]
WARNING: [Synth 8-6014] Unused sequential element u1r4n2lms757pwoemv9me7_694_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:292]
INFO: [Synth 8-6155] done synthesizing module 'S_SYNCER_for_TopParser' (451#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:40]
INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 135 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 266 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 1 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 135 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 266 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 512 - type: integer 
	Parameter FIFO_SIZE bound to: 136192 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 135 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 135 - type: integer 
	Parameter PF_THRESH_MIN bound to: 3 - type: integer 
	Parameter PF_THRESH_MAX bound to: 509 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 509 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized5' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized1' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 135 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: FWFT - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 1 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 1 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 135 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 1 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 1 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 512 - type: integer 
	Parameter FIFO_SIZE bound to: 512 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 133 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 133 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 507 - type: integer 
	Parameter PE_THRESH_MIN bound to: 5 - type: integer 
	Parameter PE_THRESH_MAX bound to: 507 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_LATENCY bound to: 2 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized6' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized2' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1403 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1403 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 359168 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 359168 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 1403 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 1403 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 1403 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 1403 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 1403 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 1403 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 2 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 1403 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 1403 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 1403 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 1403 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 1403 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 1403 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 1403 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized7' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized7' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized3' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 160 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized8' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 160 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 40960 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized8' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 40960 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 160 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 160 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 160 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 160 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 160 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 160 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 2 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 160 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 160 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 160 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 160 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 160 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 160 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 160 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized8' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized8' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized4' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 256 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized9' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 256 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 65536 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized9' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 65536 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 256 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 256 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 256 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 256 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 256 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 256 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 2 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 256 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 256 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 256 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 256 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 256 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 256 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 256 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized9' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized9' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized5' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 128 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized10' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 128 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 32768 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized10' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized6' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 32 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized11' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 65 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 32 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 8192 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 65 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized10' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 8192 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 1 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: yes - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized10' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized11' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized7' (451#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
WARNING: [Synth 8-6014] Unused sequential element jgznbtsgeb58d21kc7d1q_96_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:557]
WARNING: [Synth 8-6014] Unused sequential element gtl1ruzhusy2m1rri3kfdqlph3ik_623_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:545]
WARNING: [Synth 8-6014] Unused sequential element tvbxb9iw5bm134gq_436_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:559]
WARNING: [Synth 8-6014] Unused sequential element bm5tn9h4xzyi2xrso_324_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:452]
INFO: [Synth 8-6155] done synthesizing module 'S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser' (452#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40]
INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 167 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 266 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 1 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized12' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 167 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 266 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 512 - type: integer 
	Parameter FIFO_SIZE bound to: 136192 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 167 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 167 - type: integer 
	Parameter PF_THRESH_MIN bound to: 3 - type: integer 
	Parameter PF_THRESH_MAX bound to: 509 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 509 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized12' (452#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized3' (452#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 167 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: FWFT - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 1 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 1 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized13' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 167 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 1 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 1 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 512 - type: integer 
	Parameter FIFO_SIZE bound to: 512 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 165 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 165 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 507 - type: integer 
	Parameter PE_THRESH_MIN bound to: 5 - type: integer 
	Parameter PE_THRESH_MAX bound to: 507 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_LATENCY bound to: 2 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized13' (452#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized4' (452#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 113 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 113 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 113 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 113 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 28928 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 28928 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 113 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 113 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 113 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 113 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 113 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 113 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 2 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 113 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 113 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 113 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 113 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 113 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 113 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 113 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized11' (452#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized14' (452#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized8' (452#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 256 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 256 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 65536 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized15' (452#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized9' (452#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 16 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 16 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 16 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 16 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 4096 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 4096 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 16 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 16 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 16 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 16 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 16 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 16 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 1 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 16 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 16 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 16 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 16 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 16 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 16 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: yes - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 16 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized12' (452#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1403 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1403 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 359168 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 128 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 128 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 32768 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 160 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 160 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 40960 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 308 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 33 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 308 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 33 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 308 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 33 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 308 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 33 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 128 - type: integer 
	Parameter FIFO_SIZE bound to: 39424 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 7 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 7 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 33 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 33 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 125 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 125 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 8 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 8 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 39424 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 308 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 308 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 308 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 7 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 308 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 308 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 308 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 7 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 2 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 308 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 308 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 308 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 308 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 128 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 308 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 308 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 7 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 7 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 7 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 7 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 308 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
	Parameter DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
	Parameter REG_OUTPUT bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter WIDTH bound to: 7 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
	Parameter REG_WIDTH bound to: 7 - type: integer 
	Parameter COUNTER_WIDTH bound to: 8 - type: integer 
	Parameter RESET_VALUE bound to: 0 - type: integer 
	Parameter COUNTER_WIDTH bound to: 7 - type: integer 
	Parameter RESET_VALUE bound to: 1 - type: integer 
	Parameter COUNTER_WIDTH bound to: 7 - type: integer 
	Parameter RESET_VALUE bound to: 2 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 21 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 84 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 21 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 21 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 84 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 21 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 5376 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 84 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 84 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 84 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 32 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 84 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 32 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 8192 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 84 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 84 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
WARNING: [Synth 8-6014] Unused sequential element jfa285j8hyoegyo20_772_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:710]
WARNING: [Synth 8-6014] Unused sequential element l5psicktywzbzv5dwbndb65z41d45_609_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:698]
WARNING: [Synth 8-6014] Unused sequential element na8s0cjjwo42uoiaw_55_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:712]
WARNING: [Synth 8-6014] Unused sequential element e1jycph4ynvk6z1j2t_656_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:572]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 215 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 266 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 215 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 1 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 215 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 266 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 215 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 512 - type: integer 
	Parameter FIFO_SIZE bound to: 136192 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 215 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 215 - type: integer 
	Parameter PF_THRESH_MIN bound to: 3 - type: integer 
	Parameter PF_THRESH_MAX bound to: 509 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 509 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 215 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: FWFT - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 215 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 1 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 1 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 215 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 1 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 215 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 1 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 512 - type: integer 
	Parameter FIFO_SIZE bound to: 512 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 213 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 213 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 507 - type: integer 
	Parameter PE_THRESH_MIN bound to: 5 - type: integer 
	Parameter PE_THRESH_MAX bound to: 507 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_LATENCY bound to: 2 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 308 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 308 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 308 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 81 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 308 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 78848 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 81 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 78848 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 308 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 308 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 308 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 308 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 308 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 308 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 8 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 2 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 308 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 308 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 308 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 308 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 308 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 308 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 308 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 4 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 33 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 4 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 33 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 4 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 33 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 4 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 33 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 128 - type: integer 
	Parameter FIFO_SIZE bound to: 512 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 7 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 7 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 33 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 33 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 125 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 125 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 8 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 8 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 512 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer 
	Parameter CLOCKING_MODE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 4 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 4 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 4 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 7 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 4 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 4 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 4 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 7 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 1 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 4 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 4 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 4 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 4 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 128 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 4 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 4 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 7 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 7 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 7 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 7 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: yes - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 5 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 21 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 108 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 21 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 108 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 21 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 108 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 21 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 108 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 5376 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 108 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 108 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 108 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 32 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 108 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 108 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 32 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 108 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 8192 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 108 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 108 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
WARNING: [Synth 8-6014] Unused sequential element zkbdcs3wi927neyjrite2ti5e61_553_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:761]
WARNING: [Synth 8-6014] Unused sequential element ww17toxwogc6pyzup9ss0gdalto_896_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:749]
WARNING: [Synth 8-6014] Unused sequential element q3v3adxkb65h23d6gy9bomxhty4ts4vb_277_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:763]
WARNING: [Synth 8-6014] Unused sequential element zvr3culz566k1xgfzjjdvn4x073_516_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:612]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 147 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 266 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 147 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 1 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 147 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 266 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 147 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 512 - type: integer 
	Parameter FIFO_SIZE bound to: 136192 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 147 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 147 - type: integer 
	Parameter PF_THRESH_MIN bound to: 3 - type: integer 
	Parameter PF_THRESH_MAX bound to: 509 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 509 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 147 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: FWFT - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 147 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 1 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 1 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 147 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 1 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 1 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 147 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 1 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 512 - type: integer 
	Parameter FIFO_SIZE bound to: 512 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 145 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 145 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 507 - type: integer 
	Parameter PE_THRESH_MIN bound to: 5 - type: integer 
	Parameter PE_THRESH_MAX bound to: 507 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_LATENCY bound to: 2 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 21 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 74 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 21 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 74 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 21 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 74 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 21 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 74 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 5376 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 74 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 74 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 74 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 32 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 74 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 74 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 32 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 74 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 1 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 8192 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 74 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 74 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
WARNING: [Synth 8-6014] Unused sequential element ax7ap9imq0u5n7olp535mp1w0_790_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:557]
WARNING: [Synth 8-6014] Unused sequential element j24yhugsnp6q9udef8zlqo6qvzept41f_378_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:545]
WARNING: [Synth 8-6014] Unused sequential element gi7iudytiiwupbu53o677gbvr3_770_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:559]
WARNING: [Synth 8-6014] Unused sequential element wo86c3jzwco3x89wph03_31_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:452]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 290 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 135 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 290 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 1 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 1 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 290 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 135 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 290 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 512 - type: integer 
	Parameter FIFO_SIZE bound to: 148480 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 9 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 135 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 135 - type: integer 
	Parameter PF_THRESH_MIN bound to: 3 - type: integer 
	Parameter PF_THRESH_MAX bound to: 509 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 509 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
	Parameter MEMORY_TYPE bound to: 1 - type: integer 
	Parameter MEMORY_SIZE bound to: 148480 - type: integer 
	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
	Parameter CLOCKING_MODE bound to: 0 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter MEMORY_INIT_FILE bound to: none - type: string 
	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
	Parameter USE_MEM_INIT bound to: 1 - type: integer 
	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
	Parameter WRITE_DATA_WIDTH_A bound to: 290 - type: integer 
	Parameter READ_DATA_WIDTH_A bound to: 290 - type: integer 
	Parameter BYTE_WRITE_WIDTH_A bound to: 290 - type: integer 
	Parameter ADDR_WIDTH_A bound to: 9 - type: integer 
	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
	Parameter READ_LATENCY_A bound to: 2 - type: integer 
	Parameter WRITE_MODE_A bound to: 2 - type: integer 
	Parameter WRITE_DATA_WIDTH_B bound to: 290 - type: integer 
	Parameter READ_DATA_WIDTH_B bound to: 290 - type: integer 
	Parameter BYTE_WRITE_WIDTH_B bound to: 290 - type: integer 
	Parameter ADDR_WIDTH_B bound to: 9 - type: integer 
	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
	Parameter READ_LATENCY_B bound to: 1 - type: integer 
	Parameter WRITE_MODE_B bound to: 2 - type: integer 
	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
	Parameter P_MIN_WIDTH_DATA_A bound to: 290 - type: integer 
	Parameter P_MIN_WIDTH_DATA_B bound to: 290 - type: integer 
	Parameter P_MIN_WIDTH_DATA bound to: 290 - type: integer 
	Parameter P_MIN_WIDTH_DATA_ECC bound to: 290 - type: integer 
	Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer 
	Parameter P_ECC_MODE bound to: no_ecc - type: string 
	Parameter P_MEMORY_OPT bound to: yes - type: string 
	Parameter P_WIDTH_COL_WRITE_A bound to: 290 - type: integer 
	Parameter P_WIDTH_COL_WRITE_B bound to: 290 - type: integer 
	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 290 - type: integer 
	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's.   [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
	Parameter FIFO_MEMORY_TYPE bound to: bram - type: string 
	Parameter ECC_MODE bound to: no_ecc - type: string 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 66 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: STD - type: string 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 256 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_SYNC_STAGES bound to: 2 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter P_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter P_ECC_MODE bound to: 0 - type: integer 
	Parameter P_READ_MODE bound to: 0 - type: integer 
	Parameter P_WAKEUP_TIME bound to: 2 - type: integer 
	Parameter COMMON_CLOCK bound to: 0 - type: integer 
	Parameter RELATED_CLOCKS bound to: 0 - type: integer 
	Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer 
	Parameter ECC_MODE bound to: 0 - type: integer 
	Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer 
	Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer 
	Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESH bound to: 66 - type: integer 
	Parameter USE_ADV_FEATURES bound to: 0707 - type: string 
	Parameter READ_MODE bound to: 0 - type: integer 
	Parameter FIFO_READ_LATENCY bound to: 1 - type: integer 
	Parameter READ_DATA_WIDTH bound to: 256 - type: integer 
	Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer 
	Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer 
	Parameter DOUT_RESET_VALUE bound to: 0 - type: string 
	Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer 
	Parameter FULL_RESET_VALUE bound to: 0 - type: integer 
	Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer 
	Parameter WAKEUP_TIME bound to: 0 - type: integer 
	Parameter VERSION bound to: 0 - type: integer 
	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
	Parameter FIFO_MEM_TYPE bound to: 2 - type: integer 
	Parameter RD_MODE bound to: 0 - type: integer 
	Parameter ENABLE_ECC bound to: 0 - type: integer 
	Parameter FIFO_READ_DEPTH bound to: 256 - type: integer 
	Parameter FIFO_SIZE bound to: 65536 - type: integer 
	Parameter WR_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter RD_PNTR_WIDTH bound to: 8 - type: integer 
	Parameter FULL_RST_VAL bound to: 1'b0 
	Parameter WR_RD_RATIO bound to: 0 - type: integer 
	Parameter PF_THRESH_ADJ bound to: 66 - type: integer 
	Parameter PE_THRESH_ADJ bound to: 66 - type: integer 
	Parameter PF_THRESH_MIN bound to: 5 - type: integer 
	Parameter PF_THRESH_MAX bound to: 253 - type: integer 
	Parameter PE_THRESH_MIN bound to: 3 - type: integer 
	Parameter PE_THRESH_MAX bound to: 253 - type: integer 
	Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer 
	Parameter RD_LATENCY bound to: 1 - type: integer 
	Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 
	Parameter EN_OF bound to: 1'b1 
	Parameter EN_PF bound to: 1'b1 
	Parameter EN_WDC bound to: 1'b1 
	Parameter EN_AF bound to: 1'b0 
	Parameter EN_WACK bound to: 1'b0 
	Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 
	Parameter EN_UF bound to: 1'b1 
	Parameter EN_PE bound to: 1'b1 
	Parameter EN_RDC bound to: 1'b1 
	Parameter EN_AE bound to: 1'b0 
	Parameter EN_DVLD bound to: 1'b0 
WARNING: [Synth 8-6014] Unused sequential element ausy47odz6bnijo3i_654_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:302]
WARNING: [Synth 8-6014] Unused sequential element tqmmzdwfn0buy9fa38v3lhh_331_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:300]
WARNING: [Synth 8-6014] Unused sequential element v14oitvrprilkg4jv0hs_859_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:337]
WARNING: [Synth 8-689] width (12) of port connection 'control_S_AXI_AWADDR' does not match port width (9) of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:189]
WARNING: [Synth 8-689] width (12) of port connection 'control_S_AXI_ARADDR' does not match port width (9) of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:199]
	Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 304 - type: integer 
	Parameter NUM_QUEUES bound to: 5 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer 
	Parameter C_BASEADDR bound to: 0 - type: integer 
	Parameter QUEUE_DEPTH_BITS bound to: 16 - type: integer 
	Parameter NUM_QUEUES_WIDTH bound to: 3 - type: integer 
	Parameter DMA_QUEUE bound to: 4 - type: integer 
	Parameter BUFFER_SIZE bound to: 131072 - type: integer 
	Parameter BUFFER_SIZE_WIDTH bound to: 12 - type: integer 
	Parameter MAX_PACKET_SIZE bound to: 1600 - type: integer 
	Parameter BUFFER_THRESHOLD bound to: 4046 - type: integer 
	Parameter NUM_STATES bound to: 3 - type: integer 
	Parameter IDLE bound to: 0 - type: integer 
	Parameter WR_PKT bound to: 1 - type: integer 
	Parameter DROP bound to: 2 - type: integer 
	Parameter NUM_METADATA_STATES bound to: 2 - type: integer 
	Parameter WAIT_HEADER bound to: 0 - type: integer 
	Parameter WAIT_EOP bound to: 1 - type: integer 
	Parameter MIN_PACKET_SIZE bound to: 64 - type: integer 
	Parameter META_BUFFER_WIDTH bound to: 11 - type: integer 
	Parameter DIGEST_WIDTH bound to: 256 - type: integer 
	Parameter DST_POS bound to: 24 - type: integer 
	Parameter SEND_DIG_POS bound to: 40 - type: integer 
	Parameter WIDTH bound to: 289 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 12 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 4046 - type: integer 
	Parameter WIDTH bound to: 289 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 12 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 4046 - type: integer 
	Parameter MAX_DEPTH bound to: 4096 - type: integer 
	Parameter WIDTH bound to: 128 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 11 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 2047 - type: integer 
	Parameter WIDTH bound to: 128 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 11 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 2047 - type: integer 
	Parameter MAX_DEPTH bound to: 2048 - type: integer 
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420]
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420]
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420]
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420]
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420]
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:489]
	Parameter C_BASE_ADDRESS bound to: 0 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer 
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues_cpu_regs.v:414]
WARNING: [Synth 8-689] width (16) of port connection 'nf0_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:372]
WARNING: [Synth 8-689] width (16) of port connection 'nf1_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:373]
WARNING: [Synth 8-689] width (16) of port connection 'nf2_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:374]
WARNING: [Synth 8-689] width (16) of port connection 'nf3_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:375]
WARNING: [Synth 8-689] width (16) of port connection 'dma_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:376]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_sume_sdnet_wrapper_1'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:282]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'bram_output_queues_1'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:332]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_arbiter_v1_0'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:217]
WARNING: [Synth 8-350] instance 'axi_clock_converter_0' of module 'control_sub_axi_clock_converter_0_0' requires 42 connections, but only 40 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:3986]
WARNING: [Synth 8-350] instance 'axis_fifo_10g_rx' of module 'control_sub_axis_fifo_10g_rx_0' requires 19 connections, but only 16 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4270]
WARNING: [Synth 8-350] instance 'axis_fifo_10g_tx' of module 'control_sub_axis_fifo_10g_tx_0' requires 19 connections, but only 16 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4287]
WARNING: [Synth 8-350] instance 'nf_riffa_dma_1' of module 'control_sub_nf_riffa_dma_1_0' requires 133 connections, but only 132 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4304]
WARNING: [Synth 8-350] instance 'pcie3_7x_1' of module 'control_sub_pcie3_7x_1_0' requires 90 connections, but only 88 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4437]
WARNING: [Synth 8-350] instance 'xbar' of module 'control_sub_xbar_1' requires 40 connections, but only 38 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:3020]
WARNING: [Synth 8-350] instance 'dlmb_v10' of module 'control_sub_dlmb_v10_0' requires 25 connections, but only 24 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7409]
WARNING: [Synth 8-350] instance 'ilmb_v10' of module 'control_sub_ilmb_v10_0' requires 25 connections, but only 24 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7455]
WARNING: [Synth 8-350] instance 'lmb_bram' of module 'control_sub_lmb_bram_0' requires 16 connections, but only 14 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7480]
WARNING: [Synth 8-350] instance 'rst_clk_wiz_1_100M' of module 'control_sub_rst_clk_wiz_1_100M_0' requires 10 connections, but only 9 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7251]
WARNING: [Synth 8-689] width (12) of port connection 'M00_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:698]
WARNING: [Synth 8-689] width (12) of port connection 'M00_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:702]
WARNING: [Synth 8-689] width (12) of port connection 'M01_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:718]
WARNING: [Synth 8-689] width (12) of port connection 'M01_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:722]
WARNING: [Synth 8-689] width (12) of port connection 'M02_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:738]
WARNING: [Synth 8-689] width (12) of port connection 'M02_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:742]
WARNING: [Synth 8-689] width (12) of port connection 'M03_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:758]
WARNING: [Synth 8-689] width (12) of port connection 'M03_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:762]
WARNING: [Synth 8-689] width (12) of port connection 'M04_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:778]
WARNING: [Synth 8-689] width (12) of port connection 'M04_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:782]
WARNING: [Synth 8-689] width (12) of port connection 'M05_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:798]
WARNING: [Synth 8-689] width (12) of port connection 'M05_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:802]
WARNING: [Synth 8-689] width (12) of port connection 'M06_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:818]
WARNING: [Synth 8-689] width (12) of port connection 'M06_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:822]
WARNING: [Synth 8-689] width (12) of port connection 'M07_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:838]
WARNING: [Synth 8-689] width (12) of port connection 'M07_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:842]
	Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_BASE_ADDRESS bound to: 0 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer 
	Parameter tuser_bits_per_byte bound to: 16 - type: integer 
	Parameter interface_byte_width bound to: 32 - type: integer 
	Parameter tuser_width_intern bound to: 512 - type: integer 
	Parameter tuser_width_remain bound to: 384 - type: integer 
	Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_AXIS_DATA_INTERNAL_WIDTH bound to: 64 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:102]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:103]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:104]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:105]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:106]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:107]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:109]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:110]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:111]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:112]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:113]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:116]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:117]
	Parameter CONST_VAL bound to: 1 - type: integer 
	Parameter CONST_WIDTH bound to: 1 - type: integer 
	Parameter CONST_VAL bound to: 5 - type: integer 
	Parameter CONST_WIDTH bound to: 3 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:70]
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:72]
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:74]
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:76]
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:79]
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:81]
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:88]
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:90]
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:92]
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:94]
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:96]
	Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 
	Parameter QPLL_FBDIV_TOP bound to: 66 - type: integer 
	Parameter QPLL_FBDIV_IN bound to: 10'b0101000000 
	Parameter QPLL_FBDIV_RATIO bound to: 1'b0 
	Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 
	Parameter COMMON_CFG bound to: 92 - type: integer 
	Parameter IS_DRPCLK_INVERTED bound to: 1'b0 
	Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 
	Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 
	Parameter QPLL_CFG bound to: 27'b000010010000000000111000111 
	Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 
	Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 
	Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 
	Parameter QPLL_CP bound to: 10'b0000011111 
	Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 
	Parameter QPLL_DMONITOR_SEL bound to: 1'b0 
	Parameter QPLL_FBDIV bound to: 10'b0101000000 
	Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 
	Parameter QPLL_FBDIV_RATIO bound to: 1'b0 
	Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 
	Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 
	Parameter QPLL_LPF bound to: 4'b1111 
	Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer 
	Parameter QPLL_RP_COMP bound to: 1'b0 
	Parameter QPLL_VTRL_RESET bound to: 2'b00 
	Parameter RCAL_CFG bound to: 2'b00 
	Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 
	Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 
	Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 
	Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string 
	Parameter SIM_VERSION bound to: 2.0 - type: string 
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: FALSE - type: string 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter CLKCM_CFG bound to: TRUE - type: string 
	Parameter CLKRCV_TRST bound to: TRUE - type: string 
	Parameter CLKSWING_CFG bound to: 2'b11 
	Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer 
	Parameter C_RVAL bound to: 1'b1 
INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer_rst.v:72]
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer_rst.v:72]
	Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer 
	Parameter C_RVAL bound to: 1'b0 
	Parameter MASTER_WATCHDOG_TIMER_RESET bound to: 29'b00110111111000010010110100000 
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "yes" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_block.v:202]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "yes" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_block.v:204]
	Parameter RXRESETTIME_NOM bound to: 24'b000000000000011000011011 
	Parameter RXRESETTIME_MAX bound to: 24'b000100011010010010100110 
	Parameter SYNTH_VALUE bound to: 24'b000100011010010010100110 
	Parameter SIM_VALUE bound to: 24'b000000000000011000011011 
	Parameter INIT bound to: 2'b10 
	Parameter INIT bound to: 1'b0 
	Parameter IS_CLR_INVERTED bound to: 1'b0 
	Parameter IS_G_INVERTED bound to: 1'b0 
	Parameter C_NUM_SYNC_REGS bound to: 7 - type: integer 
	Parameter C_RVAL bound to: 1'b1 
	Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer.v:68]
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer.v:68]
	Parameter CABLE_PULL_WATCHDOG_RESET bound to: 20'b00100000000000000000 
	Parameter CABLE_UNPULL_WATCHDOG_RESET bound to: 20'b00100000000000000000 
	Parameter GEARBOXSLIP_IGNORE_COUNT bound to: 4'b1111 
	Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 
	Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 
	Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 
	Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 
	Parameter TXSYNC_OVRD_IN bound to: 1'b0 
	Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 
	Parameter ACJTAG_DEBUG_MODE bound to: 1'b0 
	Parameter ACJTAG_MODE bound to: 1'b0 
	Parameter ACJTAG_RESET bound to: 1'b0 
	Parameter ADAPT_CFG0 bound to: 20'b00000000110000010000 
	Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string 
	Parameter ALIGN_COMMA_ENABLE bound to: 10'b0001111111 
	Parameter ALIGN_COMMA_WORD bound to: 1 - type: integer 
	Parameter ALIGN_MCOMMA_DET bound to: FALSE - type: string 
	Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011 
	Parameter ALIGN_PCOMMA_DET bound to: FALSE - type: string 
	Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100 
	Parameter A_RXOSCALRESET bound to: 1'b0 
	Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string 
	Parameter CFOK_CFG bound to: 42'b100100100000000000000001000000111010000000 
	Parameter CFOK_CFG2 bound to: 6'b100000 
	Parameter CFOK_CFG3 bound to: 6'b100000 
	Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string 
	Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer 
	Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000 
	Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000 
	Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000 
	Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000 
	Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111 
	Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000 
	Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000 
	Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000 
	Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000 
	Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111 
	Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string 
	Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer 
	Parameter CLK_CORRECT_USE bound to: FALSE - type: string 
	Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string 
	Parameter CLK_COR_MAX_LAT bound to: 19 - type: integer 
	Parameter CLK_COR_MIN_LAT bound to: 15 - type: integer 
	Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string 
	Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer 
	Parameter CLK_COR_SEQ_1_1 bound to: 10'b0000000000 
	Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000 
	Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000 
	Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000 
	Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111 
	Parameter CLK_COR_SEQ_2_1 bound to: 10'b0000000000 
	Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000 
	Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000 
	Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000 
	Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111 
	Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string 
	Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer 
	Parameter CPLL_CFG bound to: 29'b00000101111000000011111011100 
	Parameter CPLL_FBDIV bound to: 4 - type: integer 
	Parameter CPLL_FBDIV_45 bound to: 5 - type: integer 
	Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110 
	Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000 
	Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer 
	Parameter DEC_MCOMMA_DETECT bound to: FALSE - type: string 
	Parameter DEC_PCOMMA_DETECT bound to: FALSE - type: string 
	Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string 
	Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000 
	Parameter ES_CLK_PHASE_SEL bound to: 1'b0 
	Parameter ES_CONTROL bound to: 6'b000000 
	Parameter ES_ERRDET_EN bound to: FALSE - type: string 
	Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string 
	Parameter ES_HORZ_OFFSET bound to: 12'b000000000000 
	Parameter ES_PMA_CFG bound to: 10'b0000000000 
	Parameter ES_PRESCALE bound to: 5'b00000 
	Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 
	Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 
	Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 
	Parameter ES_VERT_OFFSET bound to: 9'b000000000 
	Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111 
	Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111 
	Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string 
	Parameter GEARBOX_MODE bound to: 3'b001 
	Parameter IS_CLKRSVD0_INVERTED bound to: 1'b0 
	Parameter IS_CLKRSVD1_INVERTED bound to: 1'b0 
	Parameter IS_CPLLLOCKDETCLK_INVERTED bound to: 1'b0 
	Parameter IS_DMONITORCLK_INVERTED bound to: 1'b0 
	Parameter IS_DRPCLK_INVERTED bound to: 1'b0 
	Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 
	Parameter IS_RXUSRCLK2_INVERTED bound to: 1'b0 
	Parameter IS_RXUSRCLK_INVERTED bound to: 1'b0 
	Parameter IS_SIGVALIDCLK_INVERTED bound to: 1'b0 
	Parameter IS_TXPHDLYTSTCLK_INVERTED bound to: 1'b0 
	Parameter IS_TXUSRCLK2_INVERTED bound to: 1'b0 
	Parameter IS_TXUSRCLK_INVERTED bound to: 1'b0 
	Parameter LOOPBACK_CFG bound to: 1'b0 
	Parameter OUTREFCLK_SEL_INV bound to: 2'b11 
	Parameter PCS_PCIE_EN bound to: FALSE - type: string 
	Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000 
	Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100 
	Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00011001 
	Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100 
	Parameter PMA_RSV bound to: 128 - type: integer 
	Parameter PMA_RSV2 bound to: 469762058 - type: integer 
	Parameter PMA_RSV3 bound to: 2'b00 
	Parameter PMA_RSV4 bound to: 15'b000000000001000 
	Parameter PMA_RSV5 bound to: 4'b0000 
	Parameter RESET_POWERSAVE_DISABLE bound to: 1'b0 
	Parameter RXBUFRESET_TIME bound to: 5'b00001 
	Parameter RXBUF_ADDR_MODE bound to: FAST - type: string 
	Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000 
	Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000 
	Parameter RXBUF_EN bound to: TRUE - type: string 
	Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string 
	Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string 
	Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string 
	Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string 
	Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer 
	Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string 
	Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer 
	Parameter RXCDRFREQRESET_TIME bound to: 5'b00001 
	Parameter RXCDRPHRESET_TIME bound to: 5'b00001 
	Parameter RXCDR_CFG bound to: 83'b00000000000001000000000011111111110001000000000000011000010000010000000000000011010 
	Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0 
	Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0 
	Parameter RXCDR_LOCK_CFG bound to: 6'b010101 
	Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0 
	Parameter RXDFELPMRESET_TIME bound to: 7'b0001111 
	Parameter RXDLY_CFG bound to: 16'b0000000000011111 
	Parameter RXDLY_LCFG bound to: 9'b000110000 
	Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000 
	Parameter RXGEARBOX_EN bound to: TRUE - type: string 
	Parameter RXISCANRESET_TIME bound to: 5'b00001 
	Parameter RXLPM_HF_CFG bound to: 14'b00001000000000 
	Parameter RXLPM_LF_CFG bound to: 18'b001001000000000000 
	Parameter RXOOB_CFG bound to: 7'b0000110 
	Parameter RXOOB_CLK_CFG bound to: PMA - type: string 
	Parameter RXOSCALRESET_TIME bound to: 5'b00011 
	Parameter RXOSCALRESET_TIMEOUT bound to: 5'b00000 
	Parameter RXOUT_DIV bound to: 1 - type: integer 
	Parameter RXPCSRESET_TIME bound to: 5'b00001 
	Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000 
	Parameter RXPH_CFG bound to: 24'b110000000000000000000010 
	Parameter RXPH_MONITOR_SEL bound to: 5'b00000 
	Parameter RXPI_CFG0 bound to: 2'b00 
	Parameter RXPI_CFG1 bound to: 2'b11 
	Parameter RXPI_CFG2 bound to: 2'b11 
	Parameter RXPI_CFG3 bound to: 2'b11 
	Parameter RXPI_CFG4 bound to: 1'b0 
	Parameter RXPI_CFG5 bound to: 1'b0 
	Parameter RXPI_CFG6 bound to: 3'b100 
	Parameter RXPMARESET_TIME bound to: 5'b00011 
	Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0 
	Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer 
	Parameter RXSLIDE_MODE bound to: OFF - type: string 
	Parameter RXSYNC_MULTILANE bound to: 1'b0 
	Parameter RXSYNC_OVRD bound to: 1'b0 
	Parameter RXSYNC_SKIP_DA bound to: 1'b0 
	Parameter RX_BIAS_CFG bound to: 24'b000011000000000000010000 
	Parameter RX_BUFFER_CFG bound to: 6'b000000 
	Parameter RX_CLK25_DIV bound to: 7 - type: integer 
	Parameter RX_CLKMUX_PD bound to: 1'b1 
	Parameter RX_CM_SEL bound to: 2'b11 
	Parameter RX_CM_TRIM bound to: 4'b1010 
	Parameter RX_DATA_WIDTH bound to: 32 - type: integer 
	Parameter RX_DDI_SEL bound to: 6'b000000 
	Parameter RX_DEBUG_CFG bound to: 14'b00000000000000 
	Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string 
	Parameter RX_DFELPM_CFG0 bound to: 4'b0110 
	Parameter RX_DFELPM_CFG1 bound to: 1'b0 
	Parameter RX_DFELPM_KLKH_AGC_STUP_EN bound to: 1'b1 
	Parameter RX_DFE_AGC_CFG0 bound to: 2'b00 
	Parameter RX_DFE_AGC_CFG1 bound to: 3'b100 
	Parameter RX_DFE_AGC_CFG2 bound to: 4'b0000 
	Parameter RX_DFE_AGC_OVRDEN bound to: 1'b1 
	Parameter RX_DFE_GAIN_CFG bound to: 23'b00000000010000011000000 
	Parameter RX_DFE_H2_CFG bound to: 12'b000000000000 
	Parameter RX_DFE_H3_CFG bound to: 12'b000001000000 
	Parameter RX_DFE_H4_CFG bound to: 11'b00011100000 
	Parameter RX_DFE_H5_CFG bound to: 11'b00011100000 
	Parameter RX_DFE_H6_CFG bound to: 11'b00000100000 
	Parameter RX_DFE_H7_CFG bound to: 11'b00000100000 
	Parameter RX_DFE_KL_CFG bound to: 33'b001000001000000000000001100010000 
	Parameter RX_DFE_KL_LPM_KH_CFG0 bound to: 2'b01 
	Parameter RX_DFE_KL_LPM_KH_CFG1 bound to: 3'b010 
	Parameter RX_DFE_KL_LPM_KH_CFG2 bound to: 4'b0010 
	Parameter RX_DFE_KL_LPM_KH_OVRDEN bound to: 1'b1 
	Parameter RX_DFE_KL_LPM_KL_CFG0 bound to: 2'b10 
	Parameter RX_DFE_KL_LPM_KL_CFG1 bound to: 3'b010 
	Parameter RX_DFE_KL_LPM_KL_CFG2 bound to: 4'b0010 
	Parameter RX_DFE_KL_LPM_KL_OVRDEN bound to: 1'b1 
	Parameter RX_DFE_LPM_CFG bound to: 16'b0000000010000000 
	Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0 
	Parameter RX_DFE_ST_CFG bound to: 54'b000000111000010000000000000000000011000000000000111111 
	Parameter RX_DFE_UT_CFG bound to: 17'b00011100000000000 
	Parameter RX_DFE_VP_CFG bound to: 17'b00011101010100011 
	Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string 
	Parameter RX_INT_DATAWIDTH bound to: 1 - type: integer 
	Parameter RX_OS_CFG bound to: 13'b0000010000000 
	Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer 
	Parameter RX_XCLK_SEL bound to: RXREC - type: string 
	Parameter SAS_MAX_COM bound to: 64 - type: integer 
	Parameter SAS_MIN_COM bound to: 36 - type: integer 
	Parameter SATA_BURST_SEQ_LEN bound to: 4'b1111 
	Parameter SATA_BURST_VAL bound to: 3'b100 
	Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string 
	Parameter SATA_EIDLE_VAL bound to: 3'b100 
	Parameter SATA_MAX_BURST bound to: 8 - type: integer 
	Parameter SATA_MAX_INIT bound to: 21 - type: integer 
	Parameter SATA_MAX_WAKE bound to: 7 - type: integer 
	Parameter SATA_MIN_BURST bound to: 4 - type: integer 
	Parameter SATA_MIN_INIT bound to: 12 - type: integer 
	Parameter SATA_MIN_WAKE bound to: 4 - type: integer 
	Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string 
	Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 
	Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string 
	Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string 
	Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string 
	Parameter SIM_VERSION bound to: 2.0 - type: string 
	Parameter TERM_RCAL_CFG bound to: 15'b100001000010000 
	Parameter TERM_RCAL_OVRD bound to: 3'b000 
	Parameter TRANS_TIME_RATE bound to: 8'b00001110 
	Parameter TST_RSV bound to: 0 - type: integer 
	Parameter TXBUF_EN bound to: TRUE - type: string 
	Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string 
	Parameter TXDLY_CFG bound to: 16'b0000000000011111 
	Parameter TXDLY_LCFG bound to: 9'b000110000 
	Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000 
	Parameter TXGEARBOX_EN bound to: TRUE - type: string 
	Parameter TXOOB_CFG bound to: 1'b0 
	Parameter TXOUT_DIV bound to: 1 - type: integer 
	Parameter TXPCSRESET_TIME bound to: 5'b00001 
	Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000 
	Parameter TXPH_CFG bound to: 16'b0000011110000000 
	Parameter TXPH_MONITOR_SEL bound to: 5'b00000 
	Parameter TXPI_CFG0 bound to: 2'b00 
	Parameter TXPI_CFG1 bound to: 2'b00 
	Parameter TXPI_CFG2 bound to: 2'b00 
	Parameter TXPI_CFG3 bound to: 1'b0 
	Parameter TXPI_CFG4 bound to: 1'b0 
	Parameter TXPI_CFG5 bound to: 3'b100 
	Parameter TXPI_GREY_SEL bound to: 1'b0 
	Parameter TXPI_INVSTROBE_SEL bound to: 1'b0 
	Parameter TXPI_PPMCLK_SEL bound to: TXUSRCLK2 - type: string 
	Parameter TXPI_PPM_CFG bound to: 8'b00000000 
	Parameter TXPI_SYNFREQ_PPM bound to: 3'b000 
	Parameter TXPMARESET_TIME bound to: 5'b00001 
	Parameter TXSYNC_MULTILANE bound to: 1'b0 
	Parameter TXSYNC_OVRD bound to: 1'b0 
	Parameter TXSYNC_SKIP_DA bound to: 1'b0 
	Parameter TX_CLK25_DIV bound to: 7 - type: integer 
	Parameter TX_CLKMUX_PD bound to: 1'b1 
	Parameter TX_DATA_WIDTH bound to: 32 - type: integer 
	Parameter TX_DEEMPH0 bound to: 6'b000000 
	Parameter TX_DEEMPH1 bound to: 6'b000000 
	Parameter TX_DRIVE_MODE bound to: DIRECT - type: string 
	Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110 
	Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100 
	Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer 
	Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string 
	Parameter TX_MAINCURSOR_SEL bound to: 1'b0 
	Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110 
	Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001 
	Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101 
	Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010 
	Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000 
	Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110 
	Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100 
	Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010 
	Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000 
	Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000 
	Parameter TX_QPI_STATUS_EN bound to: 1'b0 
	Parameter TX_RXDETECT_CFG bound to: 14'b01100000110010 
	Parameter TX_RXDETECT_PRECHARGE_TIME bound to: 17'b10101010111001100 
	Parameter TX_RXDETECT_REF bound to: 3'b100 
	Parameter TX_XCLK_SEL bound to: TXOUT - type: string 
	Parameter UCODEER_CLR bound to: 1'b0 
	Parameter USE_PCS_CLK_PHASE_SEL bound to: 1'b0 
WARNING: [Synth 8-689] width (2) of port connection 'mac_status_vector' does not match port width (3) of module 'axi_10g_ethernet_shared' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:163]
WARNING: [Synth 8-350] instance 'axi_10g_ethernet_i' of module 'axi_10g_ethernet_shared' requires 51 connections, but only 50 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:147]
	Parameter C_OPERATION bound to: not - type: string 
	Parameter C_SIZE bound to: 1 - type: integer 
	Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_DEFAULT_VALUE_ENABLE bound to: 1 - type: integer 
	Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer 
	Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer 
	Parameter C_M_AXIS_DATA_WIDTH_INTERNAL bound to: 64 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH_INTERNAL bound to: 64 - type: integer 
	Parameter NUM_RW_REGS bound to: 1 - type: integer 
	Parameter NUM_RO_REGS bound to: 17 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter C_USE_WSTRB bound to: 0 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:117]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:118]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:119]
INFO: [Common 17-14] Message 'Synth 8-5534' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
	Parameter C_NUM_SYNC_REGS bound to: 6 - type: integer 
	Parameter AXI_DATA_WIDTH bound to: 64 - type: integer 
	Parameter IDLE bound to: 0 - type: integer 
	Parameter WAIT_FOR_EOP bound to: 1 - type: integer 
	Parameter DROP bound to: 2 - type: integer 
	Parameter BUBBLE bound to: 3 - type: integer 
	Parameter ERR_IDLE bound to: 0 - type: integer 
	Parameter ERR_WAIT bound to: 1 - type: integer 
	Parameter ERR_BUBBLE bound to: 2 - type: integer 
	Parameter ALMOST_EMPTY_OFFSET bound to: 9'b000001010 
	Parameter ALMOST_FULL_OFFSET bound to: 9'b100101100 
	Parameter DATA_WIDTH bound to: 72 - type: integer 
	Parameter DO_REG bound to: 1 - type: integer 
	Parameter EN_ECC_READ bound to: FALSE - type: string 
	Parameter EN_ECC_WRITE bound to: FALSE - type: string 
	Parameter EN_SYN bound to: FALSE - type: string 
	Parameter FIFO_MODE bound to: FIFO36_72 - type: string 
	Parameter FIRST_WORD_FALL_THROUGH bound to: TRUE - type: string 
	Parameter INIT bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 
	Parameter IS_RDCLK_INVERTED bound to: 1'b0 
	Parameter IS_RDEN_INVERTED bound to: 1'b0 
	Parameter IS_RSTREG_INVERTED bound to: 1'b0 
	Parameter IS_RST_INVERTED bound to: 1'b0 
	Parameter IS_WRCLK_INVERTED bound to: 1'b0 
	Parameter IS_WREN_INVERTED bound to: 1'b0 
	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
	Parameter SRVAL bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 
INFO: [Synth 8-638] synthesizing module 'fifo_generator_1_9' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/synth/fifo_generator_1_9.vhd:75]
	Parameter C_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter C_SELECT_XPM bound to: 0 - type: integer 
	Parameter C_COUNT_TYPE bound to: 0 - type: integer 
	Parameter C_DATA_COUNT_WIDTH bound to: 4 - type: integer 
	Parameter C_DEFAULT_VALUE bound to: BlankString - type: string 
	Parameter C_DIN_WIDTH bound to: 1 - type: integer 
	Parameter C_DOUT_RST_VAL bound to: 0 - type: string 
	Parameter C_DOUT_WIDTH bound to: 1 - type: integer 
	Parameter C_ENABLE_RLOCS bound to: 0 - type: integer 
	Parameter C_FAMILY bound to: virtex7 - type: string 
	Parameter C_FULL_FLAGS_RST_VAL bound to: 1 - type: integer 
	Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer 
	Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer 
	Parameter C_HAS_BACKUP bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer 
	Parameter C_HAS_INT_CLK bound to: 0 - type: integer 
	Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer 
	Parameter C_HAS_OVERFLOW bound to: 0 - type: integer 
	Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer 
	Parameter C_HAS_RD_RST bound to: 0 - type: integer 
	Parameter C_HAS_RST bound to: 1 - type: integer 
	Parameter C_HAS_SRST bound to: 0 - type: integer 
	Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer 
	Parameter C_HAS_VALID bound to: 0 - type: integer 
	Parameter C_HAS_WR_ACK bound to: 0 - type: integer 
	Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer 
	Parameter C_HAS_WR_RST bound to: 0 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer 
	Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer 
	Parameter C_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter C_MIF_FILE_NAME bound to: BlankString - type: string 
	Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer 
	Parameter C_OVERFLOW_LOW bound to: 0 - type: integer 
	Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer 
	Parameter C_PRELOAD_REGS bound to: 1 - type: integer 
	Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer 
	Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 15 - type: integer 
	Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 14 - type: integer 
	Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer 
	Parameter C_RD_DATA_COUNT_WIDTH bound to: 4 - type: integer 
	Parameter C_RD_DEPTH bound to: 16 - type: integer 
	Parameter C_RD_FREQ bound to: 1 - type: integer 
	Parameter C_RD_PNTR_WIDTH bound to: 4 - type: integer 
	Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer 
	Parameter C_USE_DOUT_RST bound to: 1 - type: integer 
	Parameter C_USE_ECC bound to: 0 - type: integer 
	Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer 
	Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer 
	Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer 
	Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer 
	Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer 
	Parameter C_VALID_LOW bound to: 0 - type: integer 
	Parameter C_WR_ACK_LOW bound to: 0 - type: integer 
	Parameter C_WR_DATA_COUNT_WIDTH bound to: 4 - type: integer 
	Parameter C_WR_DEPTH bound to: 16 - type: integer 
	Parameter C_WR_FREQ bound to: 1 - type: integer 
	Parameter C_WR_PNTR_WIDTH bound to: 4 - type: integer 
	Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer 
	Parameter C_MSGON_VAL bound to: 1 - type: integer 
	Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer 
	Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer 
	Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer 
	Parameter C_INTERFACE_TYPE bound to: 0 - type: integer 
	Parameter C_AXI_TYPE bound to: 1 - type: integer 
	Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer 
	Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer 
	Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer 
	Parameter C_HAS_MASTER_CE bound to: 0 - type: integer 
	Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer 
	Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer 
	Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer 
	Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer 
	Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer 
	Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer 
	Parameter C_HAS_AXI_ID bound to: 0 - type: integer 
	Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer 
	Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer 
	Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer 
	Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer 
	Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer 
	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer 
	Parameter C_HAS_AXIS_TID bound to: 0 - type: integer 
	Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer 
	Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer 
	Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer 
	Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer 
	Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer 
	Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer 
	Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer 
	Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer 
	Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer 
	Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer 
	Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer 
	Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer 
	Parameter C_WACH_TYPE bound to: 0 - type: integer 
	Parameter C_WDCH_TYPE bound to: 0 - type: integer 
	Parameter C_WRCH_TYPE bound to: 0 - type: integer 
	Parameter C_RACH_TYPE bound to: 0 - type: integer 
	Parameter C_RDCH_TYPE bound to: 0 - type: integer 
	Parameter C_AXIS_TYPE bound to: 0 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer 
	Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer 
	Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer 
	Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer 
	Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer 
	Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer 
	Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer 
	Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string 
	Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string 
	Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string 
	Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string 
	Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string 
	Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string 
	Parameter C_USE_ECC_WACH bound to: 0 - type: integer 
	Parameter C_USE_ECC_WDCH bound to: 0 - type: integer 
	Parameter C_USE_ECC_WRCH bound to: 0 - type: integer 
	Parameter C_USE_ECC_RACH bound to: 0 - type: integer 
	Parameter C_USE_ECC_RDCH bound to: 0 - type: integer 
	Parameter C_USE_ECC_AXIS bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer 
	Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer 
	Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer 
	Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer 
	Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer 
	Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer 
	Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer 
	Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer 
	Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer 
	Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer 
	Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer 
	Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer 
	Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer 
	Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer 
	Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer 
	Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer 
	Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer 
	Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer 
	Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer 
	Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer 
	Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer 
	Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer 
	Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer 
	Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer 
	Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer 
	Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'fifo_generator_v13_2_2' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/fifo_generator_v13_2_2/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38483' bound to instance 'U0' of component 'fifo_generator_v13_2_2' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/synth/fifo_generator_1_9.vhd:545]
INFO: [Synth 8-256] done synthesizing module 'fifo_generator_1_9' (649#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/synth/fifo_generator_1_9.vhd:75]
WARNING: [Synth 8-350] instance 'rx_info_fifo' of module 'fifo_generator_1_9' requires 11 connections, but only 9 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/rx_queue.v:148]
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/rx_queue.v:175]
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/rx_queue.v:247]
	Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_LEN_WIDTH bound to: 16 - type: integer 
	Parameter C_SPT_WIDTH bound to: 8 - type: integer 
	Parameter C_DPT_WIDTH bound to: 8 - type: integer 
	Parameter C_DEFAULT_VALUE_ENABLE bound to: 1 - type: integer 
	Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer 
	Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer 
	Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_LEN_WIDTH bound to: 16 - type: integer 
	Parameter C_SPT_WIDTH bound to: 8 - type: integer 
	Parameter C_DPT_WIDTH bound to: 8 - type: integer 
	Parameter C_DEFAULT_VALUE_ENABLE bound to: 1 - type: integer 
	Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer 
	Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer 
	Parameter MAX_PKT_SIZE bound to: 1600 - type: integer 
	Parameter LENGTH_COUNTER_WIDTH bound to: 3 - type: integer 
	Parameter IN_FIFO_DEPTH_BIT bound to: 8 - type: integer 
	Parameter M_S_RATIO_COUNT bound to: 4 - type: integer 
	Parameter S_M_RATIO_COUNT bound to: 0 - type: integer 
	Parameter METADATA_STATE_WAIT_START bound to: 0 - type: integer 
	Parameter METADATA_STATE_WAIT_END bound to: 1 - type: integer 
	Parameter WIDTH bound to: 16 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 5 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer 
	Parameter WIDTH bound to: 16 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 5 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer 
	Parameter MAX_DEPTH bound to: 32 - type: integer 
	Parameter WIDTH bound to: 73 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 255 - type: integer 
	Parameter WIDTH bound to: 73 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 8 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 255 - type: integer 
	Parameter MAX_DEPTH bound to: 256 - type: integer 
	Parameter C_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter WAIT_START bound to: 0 - type: integer 
	Parameter RCV_WORD bound to: 1 - type: integer 
	Parameter L2_IFSM_STATES bound to: 1 - type: integer 
	Parameter RFSM_START bound to: 0 - type: integer 
	Parameter RFSM_FINISH_PKT bound to: 1 - type: integer 
	Parameter L2_RFSM_STATES bound to: 1 - type: integer 
	Parameter MAX_PKT_SIZE bound to: 2048 - type: integer 
	Parameter MIN_PKT_SIZE bound to: 64 - type: integer 
	Parameter MAX_PKTS bound to: 32 - type: integer 
	Parameter MAX_DEPTH bound to: 8 - type: integer 
	Parameter L2_MAX_DEPTH bound to: 3 - type: integer 
	Parameter L2_MAX_PKTS bound to: 5 - type: integer 
	Parameter WIDTH bound to: 289 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 3 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 7 - type: integer 
	Parameter WIDTH bound to: 289 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 3 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 7 - type: integer 
	Parameter MAX_DEPTH bound to: 8 - type: integer 
	Parameter WIDTH bound to: 128 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 5 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer 
	Parameter WIDTH bound to: 128 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 5 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer 
	Parameter MAX_DEPTH bound to: 32 - type: integer 
	Parameter C_M_AXIS_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_LEN_WIDTH bound to: 16 - type: integer 
	Parameter C_SPT_WIDTH bound to: 8 - type: integer 
	Parameter C_DPT_WIDTH bound to: 8 - type: integer 
	Parameter C_DEFAULT_VALUE_ENABLE bound to: 1'b0 
	Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer 
	Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer 
	Parameter C_M_AXIS_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_LEN_WIDTH bound to: 16 - type: integer 
	Parameter C_SPT_WIDTH bound to: 8 - type: integer 
	Parameter C_DPT_WIDTH bound to: 8 - type: integer 
	Parameter C_DEFAULT_VALUE_ENABLE bound to: 1'b0 
	Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer 
	Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer 
	Parameter MAX_PKT_SIZE bound to: 1600 - type: integer 
	Parameter LENGTH_COUNTER_WIDTH bound to: 5 - type: integer 
	Parameter IN_FIFO_DEPTH_BIT bound to: 6 - type: integer 
	Parameter M_S_RATIO_COUNT bound to: 0 - type: integer 
	Parameter S_M_RATIO_COUNT bound to: 4 - type: integer 
	Parameter METADATA_STATE_WAIT_START bound to: 0 - type: integer 
	Parameter METADATA_STATE_WAIT_END bound to: 1 - type: integer 
	Parameter WIDTH bound to: 289 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 6 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer 
	Parameter WIDTH bound to: 289 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 6 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer 
	Parameter MAX_DEPTH bound to: 64 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element SLAVE_WIDER.length_prev_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_axis_converter_main.v:514]
	Parameter C_AXIS_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter WAIT_START bound to: 0 - type: integer 
	Parameter RCV_WORD bound to: 1 - type: integer 
	Parameter L2_IFSM_STATES bound to: 1 - type: integer 
	Parameter RFSM_START bound to: 0 - type: integer 
	Parameter RFSM_FINISH_PKT bound to: 1 - type: integer 
	Parameter L2_RFSM_STATES bound to: 1 - type: integer 
	Parameter MAX_PKT_SIZE bound to: 2048 - type: integer 
	Parameter MIN_PKT_SIZE bound to: 64 - type: integer 
	Parameter MAX_PKTS bound to: 32 - type: integer 
	Parameter MAX_DEPTH bound to: 32 - type: integer 
	Parameter L2_MAX_DEPTH bound to: 5 - type: integer 
	Parameter L2_MAX_PKTS bound to: 5 - type: integer 
	Parameter WIDTH bound to: 73 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 5 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer 
	Parameter WIDTH bound to: 73 - type: integer 
	Parameter MAX_DEPTH_BITS bound to: 5 - type: integer 
	Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer 
	Parameter MAX_DEPTH bound to: 32 - type: integer 
	Parameter AXI_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter IDLE bound to: 2'b00 
	Parameter SEND_PKT bound to: 2'b01 
	Parameter METADATA bound to: 1'b0 
	Parameter EOP bound to: 1'b1 
	Parameter ALMOST_EMPTY_OFFSET bound to: 9'b000001010 
	Parameter ALMOST_FULL_OFFSET bound to: 9'b100000000 
	Parameter DATA_WIDTH bound to: 72 - type: integer 
	Parameter DO_REG bound to: 1 - type: integer 
	Parameter EN_ECC_READ bound to: FALSE - type: string 
	Parameter EN_ECC_WRITE bound to: FALSE - type: string 
	Parameter EN_SYN bound to: FALSE - type: string 
	Parameter FIFO_MODE bound to: FIFO36_72 - type: string 
	Parameter FIRST_WORD_FALL_THROUGH bound to: TRUE - type: string 
	Parameter INIT bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 
	Parameter IS_RDCLK_INVERTED bound to: 1'b0 
	Parameter IS_RDEN_INVERTED bound to: 1'b0 
	Parameter IS_RSTREG_INVERTED bound to: 1'b0 
	Parameter IS_RST_INVERTED bound to: 1'b0 
	Parameter IS_WRCLK_INVERTED bound to: 1'b0 
	Parameter IS_WREN_INVERTED bound to: 1'b0 
	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
	Parameter SRVAL bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 
WARNING: [Synth 8-350] instance 'tx_info_fifo' of module 'fifo_generator_1_9' requires 11 connections, but only 9 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/tx_queue.v:153]
INFO: [Synth 8-226] default block is never used [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/tx_queue.v:208]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'rx_fifo_intf'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:180]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'converter_rx'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:222]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'converter_tx'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:258]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'tx_fifo_intf'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:290]
INFO: [Synth 8-638] synthesizing module 'fifo_generator_status' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/synth/fifo_generator_status.vhd:72]
	Parameter C_COMMON_CLOCK bound to: 0 - type: integer 
	Parameter C_SELECT_XPM bound to: 0 - type: integer 
	Parameter C_COUNT_TYPE bound to: 0 - type: integer 
	Parameter C_DATA_COUNT_WIDTH bound to: 4 - type: integer 
	Parameter C_DEFAULT_VALUE bound to: BlankString - type: string 
	Parameter C_DIN_WIDTH bound to: 458 - type: integer 
	Parameter C_DOUT_RST_VAL bound to: 0 - type: string 
	Parameter C_DOUT_WIDTH bound to: 458 - type: integer 
	Parameter C_ENABLE_RLOCS bound to: 0 - type: integer 
	Parameter C_FAMILY bound to: virtex7 - type: string 
	Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer 
	Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer 
	Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer 
	Parameter C_HAS_BACKUP bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer 
	Parameter C_HAS_INT_CLK bound to: 0 - type: integer 
	Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer 
	Parameter C_HAS_OVERFLOW bound to: 0 - type: integer 
	Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer 
	Parameter C_HAS_RD_RST bound to: 0 - type: integer 
	Parameter C_HAS_RST bound to: 0 - type: integer 
	Parameter C_HAS_SRST bound to: 0 - type: integer 
	Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer 
	Parameter C_HAS_VALID bound to: 0 - type: integer 
	Parameter C_HAS_WR_ACK bound to: 0 - type: integer 
	Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer 
	Parameter C_HAS_WR_RST bound to: 0 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer 
	Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer 
	Parameter C_MEMORY_TYPE bound to: 1 - type: integer 
	Parameter C_MIF_FILE_NAME bound to: BlankString - type: string 
	Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer 
	Parameter C_OVERFLOW_LOW bound to: 0 - type: integer 
	Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer 
	Parameter C_PRELOAD_REGS bound to: 1 - type: integer 
	Parameter C_PRIM_FIFO_TYPE bound to: 512x72 - type: string 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer 
	Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 15 - type: integer 
	Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 14 - type: integer 
	Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer 
	Parameter C_RD_DATA_COUNT_WIDTH bound to: 4 - type: integer 
	Parameter C_RD_DEPTH bound to: 16 - type: integer 
	Parameter C_RD_FREQ bound to: 1 - type: integer 
	Parameter C_RD_PNTR_WIDTH bound to: 4 - type: integer 
	Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer 
	Parameter C_USE_DOUT_RST bound to: 0 - type: integer 
	Parameter C_USE_ECC bound to: 0 - type: integer 
	Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer 
	Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer 
	Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer 
	Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer 
	Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer 
	Parameter C_VALID_LOW bound to: 0 - type: integer 
	Parameter C_WR_ACK_LOW bound to: 0 - type: integer 
	Parameter C_WR_DATA_COUNT_WIDTH bound to: 4 - type: integer 
	Parameter C_WR_DEPTH bound to: 16 - type: integer 
	Parameter C_WR_FREQ bound to: 1 - type: integer 
	Parameter C_WR_PNTR_WIDTH bound to: 4 - type: integer 
	Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer 
	Parameter C_MSGON_VAL bound to: 1 - type: integer 
	Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer 
	Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer 
	Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer 
	Parameter C_INTERFACE_TYPE bound to: 0 - type: integer 
	Parameter C_AXI_TYPE bound to: 1 - type: integer 
	Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer 
	Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer 
	Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer 
	Parameter C_HAS_MASTER_CE bound to: 0 - type: integer 
	Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer 
	Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer 
	Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer 
	Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer 
	Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
	Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer 
	Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer 
	Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer 
	Parameter C_HAS_AXI_ID bound to: 0 - type: integer 
	Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer 
	Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer 
	Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer 
	Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer 
	Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer 
	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
	Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer 
	Parameter C_HAS_AXIS_TID bound to: 0 - type: integer 
	Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer 
	Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer 
	Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer 
	Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer 
	Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer 
	Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer 
	Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer 
	Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer 
	Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer 
	Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer 
	Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer 
	Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer 
	Parameter C_WACH_TYPE bound to: 0 - type: integer 
	Parameter C_WDCH_TYPE bound to: 0 - type: integer 
	Parameter C_WRCH_TYPE bound to: 0 - type: integer 
	Parameter C_RACH_TYPE bound to: 0 - type: integer 
	Parameter C_RDCH_TYPE bound to: 0 - type: integer 
	Parameter C_AXIS_TYPE bound to: 0 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer 
	Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer 
	Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer 
	Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer 
	Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer 
	Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer 
	Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer 
	Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer 
	Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string 
	Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string 
	Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string 
	Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string 
	Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string 
	Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string 
	Parameter C_USE_ECC_WACH bound to: 0 - type: integer 
	Parameter C_USE_ECC_WDCH bound to: 0 - type: integer 
	Parameter C_USE_ECC_WRCH bound to: 0 - type: integer 
	Parameter C_USE_ECC_RACH bound to: 0 - type: integer 
	Parameter C_USE_ECC_RDCH bound to: 0 - type: integer 
	Parameter C_USE_ECC_AXIS bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer 
	Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer 
	Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer 
	Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer 
	Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer 
	Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer 
	Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer 
	Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer 
	Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer 
	Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer 
	Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer 
	Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer 
	Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer 
	Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer 
	Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer 
	Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer 
	Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer 
	Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer 
	Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer 
	Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer 
	Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer 
	Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer 
	Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer 
	Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer 
	Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer 
	Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer 
	Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer 
	Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer 
	Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer 
	Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer 
	Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer 
	Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'fifo_generator_v13_2_2' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/fifo_generator_v13_2_2/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38483' bound to instance 'U0' of component 'fifo_generator_v13_2_2' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/synth/fifo_generator_status.vhd:542]
INFO: [Synth 8-256] done synthesizing module 'fifo_generator_status' (656#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/synth/fifo_generator_status.vhd:72]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'xge_attachment'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:228]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'axi_10g_ethernet_i'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:147]
	Parameter C_BASE_ADDRESS bound to: 0 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer 
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_cpu_regs.v:322]
	Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_BASE_ADDRESS bound to: 0 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer 
	Parameter tuser_bits_per_byte bound to: 16 - type: integer 
	Parameter interface_byte_width bound to: 32 - type: integer 
	Parameter tuser_width_intern bound to: 512 - type: integer 
	Parameter tuser_width_remain bound to: 384 - type: integer 
	Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer 
	Parameter C_AXIS_DATA_INTERNAL_WIDTH bound to: 64 - type: integer 
	Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer 
	Parameter MASTER_WATCHDOG_TIMER_RESET bound to: 29'b00110111111000010010110100000 
	Parameter RXRESETTIME_NOM bound to: 24'b000000000000011000011011 
	Parameter RXRESETTIME_MAX bound to: 24'b000100011010010010100110 
	Parameter SYNTH_VALUE bound to: 24'b000100011010010010100110 
	Parameter SIM_VALUE bound to: 24'b000000000000011000011011 
	Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer 
	Parameter C_RVAL bound to: 1'b1 
	Parameter C_NUM_SYNC_REGS bound to: 7 - type: integer 
	Parameter C_RVAL bound to: 1'b1 
	Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer 
	Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer 
	Parameter C_RVAL bound to: 1'b0 
	Parameter CABLE_PULL_WATCHDOG_RESET bound to: 20'b00100000000000000000 
	Parameter CABLE_UNPULL_WATCHDOG_RESET bound to: 20'b00100000000000000000 
	Parameter GEARBOXSLIP_IGNORE_COUNT bound to: 4'b1111 
	Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 
	Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 
	Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 
	Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 
	Parameter TXSYNC_OVRD_IN bound to: 1'b0 
	Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 
WARNING: [Synth 8-689] width (2) of port connection 'mac_status_vector' does not match port width (3) of module 'axi_10g_ethernet_nonshared' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_block.v:164]
WARNING: [Synth 8-350] instance 'axi_10g_ethernet_i' of module 'axi_10g_ethernet_nonshared' requires 51 connections, but only 50 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_block.v:148]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'axi_10g_ethernet_i'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_block.v:148]
	Parameter C_BASE_ADDRESS bound to: 0 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer 
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:322]
INFO: [Synth 8-638] synthesizing module 'identifier_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/synth/identifier_ip.vhd:85]
	Parameter C_FAMILY bound to: virtex7 - type: string 
	Parameter C_XDEVICEFAMILY bound to: virtex7 - type: string 
	Parameter C_ELABORATION_DIR bound to: ./ - type: string 
	Parameter C_INTERFACE_TYPE bound to: 1 - type: integer 
	Parameter C_AXI_TYPE bound to: 0 - type: integer 
	Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer 
	Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer 
	Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer 
	Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string 
	Parameter C_HAS_AXI_ID bound to: 0 - type: integer 
	Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer 
	Parameter C_MEM_TYPE bound to: 1 - type: integer 
	Parameter C_BYTE_SIZE bound to: 8 - type: integer 
	Parameter C_ALGORITHM bound to: 1 - type: integer 
	Parameter C_PRIM_TYPE bound to: 1 - type: integer 
	Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer 
	Parameter C_INIT_FILE_NAME bound to: identifier_ip.mif - type: string 
	Parameter C_INIT_FILE bound to: identifier_ip.mem - type: string 
	Parameter C_USE_DEFAULT_DATA bound to: 1 - type: integer 
	Parameter C_DEFAULT_DATA bound to: DEADDEAD - type: string 
	Parameter C_HAS_RSTA bound to: 0 - type: integer 
	Parameter C_RST_PRIORITY_A bound to: CE - type: string 
	Parameter C_RSTRAM_A bound to: 0 - type: integer 
	Parameter C_INITA_VAL bound to: 0 - type: string 
	Parameter C_HAS_ENA bound to: 1 - type: integer 
	Parameter C_HAS_REGCEA bound to: 0 - type: integer 
	Parameter C_USE_BYTE_WEA bound to: 1 - type: integer 
	Parameter C_WEA_WIDTH bound to: 4 - type: integer 
	Parameter C_WRITE_MODE_A bound to: READ_FIRST - type: string 
	Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer 
	Parameter C_READ_WIDTH_A bound to: 32 - type: integer 
	Parameter C_WRITE_DEPTH_A bound to: 4096 - type: integer 
	Parameter C_READ_DEPTH_A bound to: 4096 - type: integer 
	Parameter C_ADDRA_WIDTH bound to: 12 - type: integer 
	Parameter C_HAS_RSTB bound to: 1 - type: integer 
	Parameter C_RST_PRIORITY_B bound to: CE - type: string 
	Parameter C_RSTRAM_B bound to: 0 - type: integer 
	Parameter C_INITB_VAL bound to: 0 - type: string 
	Parameter C_HAS_ENB bound to: 1 - type: integer 
	Parameter C_HAS_REGCEB bound to: 0 - type: integer 
	Parameter C_USE_BYTE_WEB bound to: 1 - type: integer 
	Parameter C_WEB_WIDTH bound to: 4 - type: integer 
	Parameter C_WRITE_MODE_B bound to: READ_FIRST - type: string 
	Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer 
	Parameter C_READ_WIDTH_B bound to: 32 - type: integer 
	Parameter C_WRITE_DEPTH_B bound to: 4096 - type: integer 
	Parameter C_READ_DEPTH_B bound to: 4096 - type: integer 
	Parameter C_ADDRB_WIDTH bound to: 12 - type: integer 
	Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 0 - type: integer 
	Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer 
	Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer 
	Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer 
	Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer 
	Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer 
	Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer 
	Parameter C_USE_SOFTECC bound to: 0 - type: integer 
	Parameter C_USE_ECC bound to: 0 - type: integer 
	Parameter C_EN_ECC_PIPE bound to: 0 - type: integer 
	Parameter C_HAS_INJECTERR bound to: 0 - type: integer 
	Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string 
	Parameter C_COMMON_CLK bound to: 1 - type: integer 
	Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer 
	Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer 
	Parameter C_USE_URAM bound to: 0 - type: integer 
	Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer 
	Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer 
	Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer 
	Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer 
	Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer 
	Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer 
	Parameter C_COUNT_36K_BRAM bound to: 4 - type: string 
	Parameter C_COUNT_18K_BRAM bound to: 0 - type: string 
	Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP     :     21.0181 mW - type: string 
INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_1' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/blk_mem_gen_v8_4_1/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195313' bound to instance 'U0' of component 'blk_mem_gen_v8_4_1' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/synth/identifier_ip.vhd:265]
INFO: [Synth 8-256] done synthesizing module 'identifier_ip' (688#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/synth/identifier_ip.vhd:85]
WARNING: [Synth 8-689] width (12) of port connection 's_axi_awaddr' does not match port width (32) of module 'identifier_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1229]
WARNING: [Synth 8-689] width (12) of port connection 's_axi_araddr' does not match port width (32) of module 'identifier_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1239]
WARNING: [Synth 8-350] instance 'identifier' of module 'identifier_ip' requires 21 connections, but only 19 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1226]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_datapath_0'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:564]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_0'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:908]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_1'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:990]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_2'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1068]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_3'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1148]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'control_sub_i'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:696]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_RLAST
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_R_LAST_INT
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[7]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[6]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[5]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[4]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[3]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[2]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[1]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARSIZE[2]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARSIZE[1]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARSIZE[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARBURST[1]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARBURST[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[3]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[2]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[1]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MUX_RST[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MEM_LAT_RST
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MEM_REG_RST
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MUX_REGCE[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MEM_REGCE
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port WE
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[11]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[10]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[9]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[8]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[7]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[6]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[5]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[4]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[3]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[2]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[1]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[7]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[6]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[5]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[3]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[7]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[6]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[5]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[4]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[3]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[2]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[1]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ECCPIPECE
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MUX_RST[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MEM_LAT_RST
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MEM_REG_RST
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MUX_REGCE[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MEM_REGCE
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port WE
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[11]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[10]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[9]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[8]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[7]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[6]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[5]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[4]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[3]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[2]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[1]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[7]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[6]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[5]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[4]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[3]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[2]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[1]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[7]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[6]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[5]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[4]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[3]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[2]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[1]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ECCPIPECE
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port SSRA
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port REGCEA
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port SSRB
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port WEB[0]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[8]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[7]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[6]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[5]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[4]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[3]
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[2]
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:02:41 ; elapsed = 00:03:07 . Memory (MB): peak = 2377.312 ; gain = 1055.098 ; free physical = 5814 ; free virtual = 13816
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
WARNING: [Synth 8-3295] tying undriven pin arbiter_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:348]
WARNING: [Synth 8-3295] tying undriven pin wlrpvy4rsdrfl6s4u7kkyypl3_198:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:409]
WARNING: [Synth 8-3295] tying undriven pin wlrpvy4rsdrfl6s4u7kkyypl3_198:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:409]
WARNING: [Synth 8-3295] tying undriven pin mvz7xkeut076iznclj71pbiykw6_1202:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:450]
WARNING: [Synth 8-3295] tying undriven pin mvz7xkeut076iznclj71pbiykw6_1202:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:450]
WARNING: [Synth 8-3295] tying undriven pin hyrzp6taloqmmwij4f4sj4ghvca_564:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:491]
WARNING: [Synth 8-3295] tying undriven pin hyrzp6taloqmmwij4f4sj4ghvca_564:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:491]
WARNING: [Synth 8-3295] tying undriven pin j4ljiyl61srd3ect0w0_1048:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:534]
WARNING: [Synth 8-3295] tying undriven pin j4ljiyl61srd3ect0w0_1048:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:534]
WARNING: [Synth 8-3295] tying undriven pin k6j2b0g89m17enc7130a7tltr1s_699:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:661]
WARNING: [Synth 8-3295] tying undriven pin k6j2b0g89m17enc7130a7tltr1s_699:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:661]
WARNING: [Synth 8-3295] tying undriven pin jx2gwgarhcldkoh6_10:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:702]
WARNING: [Synth 8-3295] tying undriven pin jx2gwgarhcldkoh6_10:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:702]
WARNING: [Synth 8-3295] tying undriven pin mpjcdkflu7yrzqmbuolk5m3_440:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:743]
WARNING: [Synth 8-3295] tying undriven pin mpjcdkflu7yrzqmbuolk5m3_440:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:743]
WARNING: [Synth 8-3295] tying undriven pin floqxoej5aicutpz7i0zfl3a2yo_1736:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:786]
WARNING: [Synth 8-3295] tying undriven pin floqxoej5aicutpz7i0zfl3a2yo_1736:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:786]
WARNING: [Synth 8-3295] tying undriven pin ioexwad3y5i2qhphqmb2ken4km02_773:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:829]
WARNING: [Synth 8-3295] tying undriven pin ioexwad3y5i2qhphqmb2ken4km02_773:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:829]
WARNING: [Synth 8-3295] tying undriven pin k9vs7qqzhhdv2zey1_659:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:872]
WARNING: [Synth 8-3295] tying undriven pin k9vs7qqzhhdv2zey1_659:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:872]
WARNING: [Synth 8-3295] tying undriven pin uaw8hbzp8uthjy28n20bk_2023:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:915]
WARNING: [Synth 8-3295] tying undriven pin uaw8hbzp8uthjy28n20bk_2023:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:915]
WARNING: [Synth 8-3295] tying undriven pin t539xkdlyz0yc8oovx06y8hcclnmjtr_2504:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:958]
WARNING: [Synth 8-3295] tying undriven pin t539xkdlyz0yc8oovx06y8hcclnmjtr_2504:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:958]
WARNING: [Synth 8-3295] tying undriven pin dvkcxpj9tgydwxf0uaacewfj1lgs44n_577:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:850]
WARNING: [Synth 8-3295] tying undriven pin dvkcxpj9tgydwxf0uaacewfj1lgs44n_577:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:850]
WARNING: [Synth 8-3295] tying undriven pin xlxy2vk2641yoha3e_1822:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:891]
WARNING: [Synth 8-3295] tying undriven pin xlxy2vk2641yoha3e_1822:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:891]
WARNING: [Synth 8-3295] tying undriven pin osh9yoxxjklf0zptis9c_990:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:932]
WARNING: [Synth 8-3295] tying undriven pin osh9yoxxjklf0zptis9c_990:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:932]
WARNING: [Synth 8-3295] tying undriven pin m7o3hoymg8uqcdqizeadzv8k_2122:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:975]
WARNING: [Synth 8-3295] tying undriven pin m7o3hoymg8uqcdqizeadzv8k_2122:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:975]
WARNING: [Synth 8-3295] tying undriven pin gghdqjx444zucre728gloe6_277:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1018]
WARNING: [Synth 8-3295] tying undriven pin gghdqjx444zucre728gloe6_277:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1018]
WARNING: [Synth 8-3295] tying undriven pin rqi3coc7d6nfo9vpmtw1osvanvjfag_1667:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1061]
WARNING: [Synth 8-3295] tying undriven pin rqi3coc7d6nfo9vpmtw1osvanvjfag_1667:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1061]
WARNING: [Synth 8-3295] tying undriven pin jmn7mgem3iz1kdmn9sqw93_2107:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1104]
WARNING: [Synth 8-3295] tying undriven pin jmn7mgem3iz1kdmn9sqw93_2107:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1104]
WARNING: [Synth 8-3295] tying undriven pin aup6zkcizv14pimeye6t4q44_717:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1147]
WARNING: [Synth 8-3295] tying undriven pin aup6zkcizv14pimeye6t4q44_717:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1147]
WARNING: [Synth 8-3295] tying undriven pin dnamqnvcoxbq1q8d4ajs2o9r82uvt_186:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1190]
WARNING: [Synth 8-3295] tying undriven pin dnamqnvcoxbq1q8d4ajs2o9r82uvt_186:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1190]
WARNING: [Synth 8-3295] tying undriven pin ooy32m177bv6ya8qd36kkxz9ae9s_566:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1233]
WARNING: [Synth 8-3295] tying undriven pin ooy32m177bv6ya8qd36kkxz9ae9s_566:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1233]
WARNING: [Synth 8-3295] tying undriven pin lah2fef13rfm7lr6x_454:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1276]
WARNING: [Synth 8-3295] tying undriven pin lah2fef13rfm7lr6x_454:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1276]
WARNING: [Synth 8-3295] tying undriven pin viwe29jpldowrxiyo9oh20jjqtzx6c6_1217:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:913]
WARNING: [Synth 8-3295] tying undriven pin viwe29jpldowrxiyo9oh20jjqtzx6c6_1217:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:913]
WARNING: [Synth 8-3295] tying undriven pin c7982oxn1ft1zx03d0_1883:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:954]
WARNING: [Synth 8-3295] tying undriven pin c7982oxn1ft1zx03d0_1883:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:954]
WARNING: [Synth 8-3295] tying undriven pin z20ebgxmlf2wz2spqe_2680:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:995]
WARNING: [Synth 8-3295] tying undriven pin z20ebgxmlf2wz2spqe_2680:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:995]
WARNING: [Synth 8-3295] tying undriven pin ufi21gd9cod5i8zmbsn_386:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1038]
WARNING: [Synth 8-3295] tying undriven pin ufi21gd9cod5i8zmbsn_386:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1038]
WARNING: [Synth 8-3295] tying undriven pin z9lcgcecur72ty6e3hwewxm68okrwjkz_836:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1081]
WARNING: [Synth 8-3295] tying undriven pin z9lcgcecur72ty6e3hwewxm68okrwjkz_836:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1081]
WARNING: [Synth 8-3295] tying undriven pin kmx85e9k8hls511lexi9vcc3n9opnyf_1703:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1124]
WARNING: [Synth 8-3295] tying undriven pin kmx85e9k8hls511lexi9vcc3n9opnyf_1703:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1124]
WARNING: [Synth 8-3295] tying undriven pin khxyr7u7157o34roo3qky80hlj_1032:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1167]
WARNING: [Synth 8-3295] tying undriven pin khxyr7u7157o34roo3qky80hlj_1032:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1167]
WARNING: [Synth 8-3295] tying undriven pin akxg1tfymljerus1vpcnepyv8wl7y_170:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1210]
WARNING: [Synth 8-3295] tying undriven pin akxg1tfymljerus1vpcnepyv8wl7y_170:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1210]
WARNING: [Synth 8-3295] tying undriven pin i4bhqagkugyabg8pt4qtyisoea79s5_80:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1253]
WARNING: [Synth 8-3295] tying undriven pin i4bhqagkugyabg8pt4qtyisoea79s5_80:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1253]
WARNING: [Synth 8-3295] tying undriven pin oifasqvrhgnf3x3oyfx42u_1092:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1296]
WARNING: [Synth 8-3295] tying undriven pin oifasqvrhgnf3x3oyfx42u_1092:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1296]
WARNING: [Synth 8-3295] tying undriven pin lyq1o92avk5w3720fvrfdo_576:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1339]
WARNING: [Synth 8-3295] tying undriven pin lyq1o92avk5w3720fvrfdo_576:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1339]
WARNING: [Synth 8-3295] tying undriven pin w5y7682mjw2ipu44fcs95o4cqw9j_321:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1382]
WARNING: [Synth 8-3295] tying undriven pin w5y7682mjw2ipu44fcs95o4cqw9j_321:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1382]
WARNING: [Synth 8-3295] tying undriven pin rrx2o92507e60rsejcoaqy_2580:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:661]
WARNING: [Synth 8-3295] tying undriven pin rrx2o92507e60rsejcoaqy_2580:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:661]
WARNING: [Synth 8-3295] tying undriven pin te3fcfez76chzmfek_1821:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:702]
WARNING: [Synth 8-3295] tying undriven pin te3fcfez76chzmfek_1821:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:702]
WARNING: [Synth 8-3295] tying undriven pin lkis63w9hmt3fpru78meaacsu_1457:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:743]
WARNING: [Synth 8-3295] tying undriven pin lkis63w9hmt3fpru78meaacsu_1457:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:743]
WARNING: [Synth 8-3295] tying undriven pin x59vx3wada7a411ba31_2374:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:786]
WARNING: [Synth 8-3295] tying undriven pin x59vx3wada7a411ba31_2374:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:786]
WARNING: [Synth 8-3295] tying undriven pin of49eycjluhg2js6xdhgiiy1js06gv_1190:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:829]
WARNING: [Synth 8-3295] tying undriven pin of49eycjluhg2js6xdhgiiy1js06gv_1190:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:829]
WARNING: [Synth 8-3295] tying undriven pin onctbgj1uc88lix0_190:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:872]
WARNING: [Synth 8-3295] tying undriven pin onctbgj1uc88lix0_190:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:872]
WARNING: [Synth 8-3295] tying undriven pin nczo24ruhk6u3b1ok20l9jc3z6zpaw_782:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:915]
WARNING: [Synth 8-3295] tying undriven pin nczo24ruhk6u3b1ok20l9jc3z6zpaw_782:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:915]
WARNING: [Synth 8-3295] tying undriven pin mjjip2n5ms3clnld2wphvbc0_2464:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:958]
WARNING: [Synth 8-3295] tying undriven pin mjjip2n5ms3clnld2wphvbc0_2464:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:958]
WARNING: [Synth 8-3295] tying undriven pin la3bvivtp1cnzub8_1029:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:479]
WARNING: [Synth 8-3295] tying undriven pin la3bvivtp1cnzub8_1029:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:479]
WARNING: [Synth 8-3295] tying undriven pin kty4eu99g0lcln2zjl4dm8w48s9_2303:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:520]
WARNING: [Synth 8-3295] tying undriven pin kty4eu99g0lcln2zjl4dm8w48s9_2303:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:520]
WARNING: [Synth 8-3295] tying undriven pin s487z0rob4coa34tq19uftml_2207:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:561]
WARNING: [Synth 8-3295] tying undriven pin s487z0rob4coa34tq19uftml_2207:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:561]
WARNING: [Synth 8-3295] tying undriven pin xob1479vc8hxdsk2seqzos5lpnt7wwh_1463:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:604]
WARNING: [Synth 8-3295] tying undriven pin xob1479vc8hxdsk2seqzos5lpnt7wwh_1463:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:604]
WARNING: [Synth 8-3295] tying undriven pin sss_output_queues_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:643]
WARNING: [Synth 8-3295] tying undriven pin nf_10g_interface_shared_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared.v:261]
WARNING: [Synth 8-3295] tying undriven pin nf_10g_interface_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface.v:262]
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:02:46 ; elapsed = 00:03:13 . Memory (MB): peak = 2377.312 ; gain = 1055.098 ; free physical = 5925 ; free virtual = 13927
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:02:46 ; elapsed = 00:03:13 . Memory (MB): peak = 2377.312 ; gain = 1055.098 ; free physical = 5925 ; free virtual = 13927
---------------------------------------------------------------------------------
INFO: [Netlist 29-17] Analyzing 246 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0/control_sub_mdm_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0/control_sub_mdm_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0/control_sub_microblaze_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0/control_sub_microblaze_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0/control_sub_lmb_bram_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0/control_sub_lmb_bram_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1/control_sub_xbar_1_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1/control_sub_xbar_1_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie_reset_inv'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie_reset_inv'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0/control_sub_xbar_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0/control_sub_xbar_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0/control_sub_m01_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0/control_sub_auto_cc_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0/control_sub_auto_cc_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:53]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:55]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:57]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:60]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:62]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:64]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:67]
WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:69]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:70]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:53]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:55]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:57]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:60]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:62]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:64]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:67]
WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:69]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:70]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:53]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:55]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:57]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:60]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:62]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:64]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:67]
WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:69]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:70]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:54]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:56]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:58]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:61]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:63]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:65]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:68]
WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:70]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:71]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
INFO: [Timing 38-2] Deriving generated clocks
Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
WARNING: [Vivado 12-507] No nets matched 'control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/pipe_txoutclk_out'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc:116]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/top_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied.
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
WARNING: [Constraints 18-619] A clock with name 'xphy_refclk_p' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:92]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:114]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:115]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:116]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:117]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:118]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:119]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:120]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:121]
WARNING: [Vivado 12-627] No clocks matched 'clk_250mhz_mux_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134]
WARNING: [Vivado 12-627] No clocks matched 'clk_125mhz_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134]
WARNING: [Vivado 12-627] No clocks matched 'clk_125mhz_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135]
WARNING: [Vivado 12-627] No clocks matched 'clk_250mhz_mux_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135]
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:137]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:137]
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:138]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:138]
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:140]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:140]
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:141]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:141]
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:143]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:143]
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:144]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:144]
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:146]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:146]
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:147]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:147]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/top_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied.
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/dont_touch.xdc]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/dont_touch.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Common 17-14] Message 'Vivado 12-3272' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Common 17-14] Message 'XPM_CDC_GRAY: TCL 1000' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 192 instances were transformed.
  BUFGCE => BUFGCTRL: 1 instances
  FDR => FDRE: 12 instances
  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
  MUXCY_L => MUXCY: 176 instances
  SRL16 => SRL16E: 1 instances

Constraint Validation Runtime : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4616.531 ; gain = 0.000 ; free physical = 3621 ; free virtual = 11628
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_clock_converter_0' at clock pin 's_axi_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_dwidth_dma_rx' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_dwidth_dma_tx' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_fifo_10g_rx' at clock pin 'm_axis_aclk' is different from the actual clock period '4.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_fifo_10g_tx' at clock pin 'm_axis_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/xbar' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc' at clock pin 'm_axi_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram' at clock pin 'clka' is different from the actual clock period '10.000', this can lead to different synthesis results.
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:05:44 ; elapsed = 00:06:14 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 5387 ; free virtual = 13395
---------------------------------------------------------------------------------
INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-4471] merging register 'seq_cnt_en_reg' into 'from_sys_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:377]
WARNING: [Synth 8-6014] Unused sequential element seq_cnt_en_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:377]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'sume_to_sdnet'
INFO: [Synth 8-5546] ROM "kfw5rcmmtazfzl5uicmzk_223" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "qv2nvn0ml7fv931vyldv_203" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "wwb9tx90f0u48ee9whodzx_707" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "size_0" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "CamReg_reg[3]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CamReg_reg[2]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CamReg_reg[1]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CamReg_reg[0]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'UpdateFSM_reg' in module 'realmain_nat64_0_t_Update'
INFO: [Synth 8-5544] ROM "Entry_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Count_G" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "UpdateFSM_D" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "wack_i" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "term10R" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "CamReg_reg[3]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CamReg_reg[2]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CamReg_reg[1]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CamReg_reg[0]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'UpdateFSM_reg' in module 'realmain_lookup_table_0_t_Update'
INFO: [Synth 8-5544] ROM "Entry_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "Count_G" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "UpdateFSM_D" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "wack_i" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "term1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "flag1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "term10R" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_0_Editor_FifoReader'
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "MUX_EditCmd_offsetEop" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_2_Editor_FifoReader'
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "MUX_EditCmd_offsetEop" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "MUX_EditDat_0_MASK" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "MUX_EditDat_0_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "MUX_EditDat_1_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "MUX_EditDat_2_MASK" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "MUX_EditDat_2_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
INFO: [Synth 8-5544] ROM "gen_rst_ic.rst_seq_reentered" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.fifo_wr_rst_i" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.wr_rst_busy_i" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_rrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_rrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__2'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__2'
INFO: [Synth 8-5544] ROM "gen_rst_ic.rst_seq_reentered" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.fifo_wr_rst_i" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.wr_rst_busy_i" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_rrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_rrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'S_PROTOCOL_ADAPTER_INGRESS'
INFO: [Synth 8-5544] ROM "nxt_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nxt_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nxt_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nxt_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized2'
INFO: [Synth 8-5544] ROM "gen_fwft.leaving_empty_fwft" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_fwft.next_fwft_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_fwft.next_fwft_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_fwft.next_fwft_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_fwft.next_fwft_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Common 17-14] Message 'Synth 8-5544' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__3'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__3'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__4'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__4'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized6'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__5'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__5'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__6'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__6'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__7'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__7'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__8'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__8'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__9'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__9'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__10'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__10'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized13'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__11'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__11'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__12'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__12'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__13'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__13'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__14'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__14'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__15'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__15'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__16'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__16'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__17'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__17'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__18'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__18'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__19'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__19'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized24'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__20'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__20'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__21'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__21'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__22'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__22'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__23'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__23'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__24'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__24'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__25'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__25'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__26'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__26'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__27'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__27'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__28'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__28'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__29'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__29'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized30'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__30'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__30'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__31'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__31'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__32'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__32'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__33'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__33'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__34'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__34'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__35'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__35'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__36'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__36'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst'
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_small_fifo.v:103]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'sss_output_queues'
INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[0].metadata_state_reg[0]' in module 'sss_output_queues'
INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[1].metadata_state_reg[1]' in module 'sss_output_queues'
INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[2].metadata_state_reg[2]' in module 'sss_output_queues'
INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[3].metadata_state_reg[3]' in module 'sss_output_queues'
INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[4].metadata_state_reg[4]' in module 'sss_output_queues'
INFO: [Synth 8-802] inferred FSM for state register 'rs_state_reg' in module 'ten_gig_eth_mac_v15_1_6_rs_64bit'
INFO: [Synth 8-5546] ROM "crc_position_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "dic_required" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "dic_returned" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "poss_ifg_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
INFO: [Synth 8-5546] ROM "control_frame" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
INFO: [Synth 8-5546] ROM "control_frame" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'pause_state_reg' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl'
INFO: [Synth 8-802] inferred FSM for state register 'legacy_state_reg' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl'
INFO: [Synth 8-802] inferred FSM for state register 'pause_state_reg' in module 'ten_gig_eth_mac_v15_1_6_tx_pause_cntl'
INFO: [Synth 8-802] inferred FSM for state register 'rx_state_int_reg' in module 'ten_gig_eth_mac_v15_1_6_rx_fsm'
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5546] ROM "frame_max" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5545] ROM "broadcast_detect" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
INFO: [Synth 8-5546] ROM "control_frame_any_add" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "pause_opcode" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "pfc_opcode" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5545] ROM "special_addr_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
INFO: [Synth 8-5546] ROM "early_truncate" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "early_truncate" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'pause_state_reg' in module 'ten_gig_eth_mac_v15_1_6_rx_control'
INFO: [Synth 8-802] inferred FSM for state register 'mcp1_state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_idle_delete'
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "s_code_c0" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "s_code_c4" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_tx_pcs_fsm'
INFO: [Synth 8-802] inferred FSM for state register 'mcp1_state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_block_lock_fsm'
INFO: [Common 17-14] Message 'Synth 8-802' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5546] ROM "mcp1_rx_64_ctrl_out" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "IsValidControl" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "IsValidControl0" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "IsValidControl1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "IsValidControl2" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "IsValidControl3" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "IsValidControl4" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "IsValidControl5" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "IsValidControl6" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5587] ROM size for "DecodeWord" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "DecodeWord0" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "DecodeWord1" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "DecodeWord2" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "DecodeWord3" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "DecodeWord4" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "DecodeWord5" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "DecodeWord6" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "gt_txd_mux" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "gt_txc_mux" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25)
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
INFO: [Synth 8-5546] ROM "tkeep_encoded_i" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25)
INFO: [Synth 8-5546] ROM "tkeep_encoded_i" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "tkeep_encoded_i" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "tkeep_encoded_i" won't be mapped to RAM because it is too sparse
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                   FIRST |                                0 |                               00
                    WAIT |                                1 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'sume_to_sdnet'
INFO: [Synth 8-3971] The signal gen_wr_b.gen_word_narrow.mem_reg was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_INIT |                             1010 |                             0000
                FSM_IDLE |                             0011 |                             0001
          FSM_LOOK_READ2 |                             1000 |                             1011
           FSM_LOOK_READ |                             0111 |                             0010
          FSM_LOOK_WRITE |                             0000 |                             0011
            FSM_CAM_DEL1 |                             0001 |                             1001
            FSM_CAM_DEL2 |                             1001 |                             1010
             FSM_CAM_POP |                             0010 |                             0111
           FSM_CAM_LATCH |                             1011 |                             1000
            FSM_ADD_READ |                             0100 |                             0100
            FSM_CAM_PUSH |                             0101 |                             0110
           FSM_ADD_WRITE |                             0110 |                             0101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'UpdateFSM_reg' using encoding 'sequential' in module 'realmain_nat64_0_t_Update'
INFO: [Synth 8-3971] The signal gen_wr_b.gen_word_narrow.mem_reg was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_INIT |                             1010 |                             0000
                FSM_IDLE |                             0011 |                             0001
          FSM_LOOK_READ2 |                             1000 |                             1011
           FSM_LOOK_READ |                             0111 |                             0010
          FSM_LOOK_WRITE |                             0000 |                             0011
            FSM_CAM_DEL1 |                             0001 |                             1001
            FSM_CAM_DEL2 |                             1001 |                             1010
             FSM_CAM_POP |                             0010 |                             0111
           FSM_CAM_LATCH |                             1011 |                             1000
            FSM_ADD_READ |                             0100 |                             0100
            FSM_CAM_PUSH |                             0101 |                             0110
           FSM_ADD_WRITE |                             0110 |                             0101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'UpdateFSM_reg' using encoding 'sequential' in module 'realmain_lookup_table_0_t_Update'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                          0000001 |                              000
          FSM_INSERT_PAD |                          0000010 |                              100
            FSM_INSERT_2 |                          0000100 |                              101
            FSM_REMOVE_2 |                          0001000 |                              001
     FSM_REMOVE_WAIT_EOP |                          0010000 |                              010
     FSM_INSERT_WAIT_EOP |                          0100000 |                              110
        FSM_INSERT_FLUSH |                          1000000 |                              111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_0_Editor_FifoReader'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                          0000001 |                              000
          FSM_INSERT_PAD |                          0000010 |                              100
            FSM_INSERT_2 |                          0000100 |                              101
            FSM_REMOVE_2 |                          0001000 |                              001
     FSM_REMOVE_WAIT_EOP |                          0010000 |                              010
     FSM_INSERT_WAIT_EOP |                          0100000 |                              110
        FSM_INSERT_FLUSH |                          1000000 |                              111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_2_Editor_FifoReader'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__1'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__2'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__2'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                               00 |                              001
              RX_SOF_EOF |                               01 |                              011
                  RX_SOF |                               10 |                              010
                  RX_PKT |                               11 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'S_PROTOCOL_ADAPTER_INGRESS'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 invalid |                               00 |                               00
            stage1_valid |                               01 |                               10
       both_stages_valid |                               10 |                               11
            stage2_valid |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized2'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__3'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__3'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__4'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__4'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 invalid |                               00 |                               00
            stage1_valid |                               01 |                               10
       both_stages_valid |                               10 |                               11
            stage2_valid |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized6'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__5'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__5'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__6'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__6'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__7'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__7'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__8'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__8'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__9'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__9'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__10'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__10'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 invalid |                               00 |                               00
            stage1_valid |                               01 |                               10
       both_stages_valid |                               10 |                               11
            stage2_valid |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized13'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__11'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__11'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__12'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__12'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__13'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__13'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__14'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__14'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__15'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__15'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__16'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__16'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__17'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__17'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__18'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__18'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__19'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__19'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 invalid |                               00 |                               00
            stage1_valid |                               01 |                               10
       both_stages_valid |                               10 |                               11
            stage2_valid |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized24'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__20'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__20'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__21'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__21'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__22'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__22'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__23'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__23'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__24'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__24'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__25'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__25'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__26'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__26'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__27'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__27'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__28'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__28'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__29'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__29'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 invalid |                               00 |                               00
            stage1_valid |                               01 |                               10
       both_stages_valid |                               10 |                               11
            stage2_valid |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized30'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__30'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__30'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__31'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__31'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__32'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__32'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__33'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__33'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__34'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__34'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__35'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__35'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__36'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__36'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               WRST_IDLE |                            00001 |                              000
                 WRST_IN |                            00010 |                              010
                WRST_OUT |                            00100 |                              111
               WRST_EXIT |                            01000 |                              110
            WRST_GO2IDLE |                            10000 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               RRST_IDLE |                               00 |                               00
                 RRST_IN |                               01 |                               10
                RRST_OUT |                               10 |                               11
               RRST_EXIT |                               11 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              001 |                              000
                  WR_PKT |                              010 |                              001
                    DROP |                              100 |                              010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'sss_output_queues'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
             WAIT_HEADER |                                0 |                               00
                WAIT_EOP |                                1 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[0].metadata_state_reg[0]' using encoding 'sequential' in module 'sss_output_queues'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
             WAIT_HEADER |                                0 |                               00
                WAIT_EOP |                                1 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[1].metadata_state_reg[1]' using encoding 'sequential' in module 'sss_output_queues'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
             WAIT_HEADER |                                0 |                               00
                WAIT_EOP |                                1 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[2].metadata_state_reg[2]' using encoding 'sequential' in module 'sss_output_queues'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
             WAIT_HEADER |                                0 |                               00
                WAIT_EOP |                                1 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[3].metadata_state_reg[3]' using encoding 'sequential' in module 'sss_output_queues'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
             WAIT_HEADER |                                0 |                               00
                WAIT_EOP |                                1 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[4].metadata_state_reg[4]' using encoding 'sequential' in module 'sss_output_queues'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    INIT |                               00 |                               00
                   COUNT |                               01 |                               01
                   FAULT |                               10 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'rs_state_reg' using encoding 'sequential' in module 'ten_gig_eth_mac_v15_1_6_rs_64bit'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                             0001 |                              000
                     REQ |                             0010 |                              001
                    WAIT |                             0100 |                              010
                   COUNT |                             1000 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'legacy_state_reg' using encoding 'one-hot' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  P_IDLE |                               00 |                               00
                   P_REQ |                               01 |                               01
                  P_WAIT |                               10 |                               10
                  P_HOLD |                               11 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'pause_state_reg' using encoding 'sequential' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              001 |                               00
                 REQUEST |                              010 |                               01
                    SEND |                              100 |                               10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'pause_state_reg' using encoding 'one-hot' in module 'ten_gig_eth_mac_v15_1_6_tx_pause_cntl'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              000 |                              000
               CHECK_MIN |                              001 |                              001
                    DATA |                              010 |                              010
               BAD_STRIP |                              011 |                              011
                VALIDATE |                              100 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'rx_state_int_reg' using encoding 'sequential' in module 'ten_gig_eth_mac_v15_1_6_rx_fsm'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                            00001 |                              000
                  LEGACY |                            00010 |                              001
                     PFC |                            00100 |                              100
                PFCQ3_Q6 |                            01000 |                              101
                   PFCQ7 |                            10000 |                              110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'pause_state_reg' using encoding 'one-hot' in module 'ten_gig_eth_mac_v15_1_6_rx_control'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                STRAIGHT |                              000 |                              000
                 DELETE3 |                              001 |                              010
                 DELETE1 |                              010 |                              001
                 TWISTED |                              011 |                              100
        POSSIBLE_DELETE4 |                              100 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'mcp1_state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_idle_delete'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 TX_INIT |                              000 |                              000
                    TX_E |                              001 |                              100
                    TX_C |                              010 |                              001
                    TX_D |                              011 |                              010
                    TX_T |                              100 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_tx_pcs_fsm'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               LOCK_INIT |                               00 |                               00
               RESET_CNT |                               01 |                               01
   TEST_VALID_INVALID_SH |                               10 |                               10
                    SLIP |                               11 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'mcp1_state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_block_lock_fsm'
INFO: [Common 17-14] Message 'Synth 8-3354' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
             BER_MT_INIT |                              000 |                              000
             START_TIMER |                              001 |                              001
             BER_TEST_SH |                              010 |                              010
              BER_BAD_SH |                              011 |                              011
                  HI_BER |                              100 |                              100
                GOOD_BER |                              101 |                              101
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 RX_INIT |                              000 |                              000
                    RX_E |                              001 |                              100
                    RX_T |                              010 |                              011
                    RX_C |                              011 |                              001
                    RX_D |                              100 |                              010
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                               00 |                              000
                  RDREQ1 |                               01 |                              001
              RDPENDING1 |                               10 |                              010
                 RDRESP1 |                               11 |                              011
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                               00 |                               00
                     REQ |                               01 |                               01
                     GNT |                               10 |                               10
                    GNT1 |                               11 |                               11
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
              ERR_BUBBLE |                               00 |                              010
                ERR_IDLE |                               01 |                              000
                ERR_WAIT |                               10 |                              001
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                               00 |                             0000
            WAIT_FOR_EOP |                               01 |                             0001
                  BUBBLE |                               10 |                             0011
                    DROP |                               11 |                             0010
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                                0 |                              000
                SEND_PKT |                                1 |                              001
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
              ERR_BUBBLE |                               00 |                              010
                ERR_IDLE |                               01 |                              000
                ERR_WAIT |                               10 |                              001
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                               00 |                             0000
            WAIT_FOR_EOP |                               01 |                             0001
                  BUBBLE |                               10 |                             0011
                    DROP |                               11 |                             0010
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                                0 |                              000
                SEND_PKT |                                1 |                              001
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
              ERR_BUBBLE |                               00 |                              010
                ERR_IDLE |                               01 |                              000
                ERR_WAIT |                               10 |                              001
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                               00 |                             0000
            WAIT_FOR_EOP |                               01 |                             0001
                  BUBBLE |                               10 |                             0011
                    DROP |                               11 |                             0010
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                                0 |                              000
                SEND_PKT |                                1 |                              001
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
              ERR_BUBBLE |                               00 |                              010
                ERR_IDLE |                               01 |                              000
                ERR_WAIT |                               10 |                              001
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                               00 |                             0000
            WAIT_FOR_EOP |                               01 |                             0001
                  BUBBLE |                               10 |                             0011
                    DROP |                               11 |                             0010
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                                0 |                              000
                SEND_PKT |                                1 |                              001
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
             wait_wraddr |                               00 |                               00
              reg_wraddr |                               01 |                               01
                   os_wr |                               10 |                               10
                  wr_mem |                               11 |                               11
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:06:26 ; elapsed = 00:06:59 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 2948 ; free virtual = 10984
---------------------------------------------------------------------------------
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 

Report RTL Partitions: 
+------+-------------------------------------------+------------+----------+
|      |RTL Partition                              |Replication |Instances |
+------+-------------------------------------------+------------+----------+
|1     |clk_wiz_ip_clk_wiz__GC0                    |           1|        13|
|2     |TopParser_t_EngineStage_0__GB0             |           1|     28779|
|3     |TopParser_t_EngineStage_0__GB1             |           1|     25901|
|4     |TopParser_t_EngineStage_0__GB2             |           1|     28664|
|5     |TopParser_t_EngineStage_0__GB3             |           1|     16353|
|6     |TopParser_t_EngineStage_0__GB4             |           1|     10254|
|7     |TopParser_t_EngineStage_1__GB0             |           1|     24956|
|8     |TopParser_t_EngineStage_1__GB1             |           1|     11997|
|9     |TopParser_t_EngineStage_1__GB2             |           1|     13649|
|10    |TopParser_t_EngineStage_1__GB3             |           1|      9735|
|11    |TopParser_t_EngineStage_1__GB4             |           1|     13026|
|12    |TopParser_t_Engine__GC0                    |           1|      4218|
|13    |TopParser_t__GC0                           |           1|        20|
|14    |TopPipe_lvl_0_t_EngineStage_2__GB0         |           1|     18569|
|15    |TopPipe_lvl_0_t_EngineStage_2__GB1         |           1|     14378|
|16    |TopPipe_lvl_0_t_EngineStage_2__GB2         |           1|     11127|
|17    |TopPipe_lvl_0_t_Engine__GCB0               |           1|     29703|
|18    |TopPipe_lvl_0_t_Engine__GCB1               |           1|     22252|
|19    |TopPipe_lvl_0_t_Engine__GCB2               |           1|     27183|
|20    |TopPipe_lvl_0_t_EngineStage_8              |           1|     27185|
|21    |TopPipe_lvl_0_t_Engine__GCB4               |           1|     29739|
|22    |TopPipe_lvl_0_t_EngineStage_5              |           1|     22245|
|23    |TopPipe_lvl_0_t_Engine__GCB6               |           1|     19851|
|24    |TopPipe_lvl_0_t_Engine__GCB7               |           1|     27186|
|25    |TopPipe_lvl_0_t_Engine__GCB8               |           1|     22253|
|26    |TopPipe_lvl_0_t_Engine__GCB9               |           1|     24716|
|27    |TopPipe_lvl_1_t_EngineStage_1              |           1|     26710|
|28    |TopPipe_lvl_1_t_Engine__GB1                |           1|     19507|
|29    |TopPipe_lvl_1_t_Engine__GB2                |           1|     22045|
|30    |TopPipe_lvl_1_t_Engine__GB3                |           1|     21839|
|31    |TopPipe_lvl_1_t_Engine__GB4                |           1|        13|
|32    |TopDeparser_t_EngineStage_0__GB0           |           1|     33017|
|33    |TopDeparser_t_EngineStage_0__GB1           |           1|      6497|
|34    |TopDeparser_t_EngineStage_0__GB2           |           1|     18709|
|35    |reg__2029                                  |           1|      1403|
|36    |TopDeparser_t_EngineStage_2_Editor__GB0    |           1|     29503|
|37    |TopDeparser_t_EngineStage_2_Editor__GB1    |           1|     12589|
|38    |TopDeparser_t_EngineStage_2__GC0           |           1|     29578|
|39    |TopDeparser_t_Engine__GC0                  |           1|     34766|
|40    |TopDeparser_t__GC0                         |           1|        22|
|41    |SimpleSumeSwitch__GCB0                     |           1|     23270|
|42    |S_SYNCER_for_TopDeparser                   |           1|      6030|
|43    |SimpleSumeSwitch__GCB2                     |           1|     25101|
|44    |SimpleSumeSwitch__GCB3                     |           1|     41657|
|45    |SimpleSumeSwitch__GCB4                     |           1|      9745|
|46    |nf_sume_sdnet__GC0                         |           1|        11|
|47    |nf_datapath__GCB0                          |           1|     23530|
|48    |nf_datapath__GCB1                          |           1|     10473|
|49    |bd_a1aa_xpcs_0_shared_clock_and_reset__GC0 |           1|        53|
|50    |ten_gig_eth_pcs_pma_v6_0_13                |           2|     14863|
|51    |bd_a1aa_xpcs_0_block__GC0                  |           1|       899|
|52    |bd_a1aa_xpcs_0_support__GC0                |           1|         2|
|53    |bd_a1aa__GC0                               |           1|     15327|
|54    |nf_10g_interface_shared_block__GC0         |           1|     11027|
|55    |nf_10g_interface_shared__GC0               |           1|      2767|
|56    |bd_7ad4_xmac_0_block                       |           3|     15327|
|57    |bd_7ad4_xpcs_0_block__GC0                  |           1|       899|
|58    |nf_10g_interface_block__xdcDup__1__GC0     |           1|     11027|
|59    |nf_10g_interface__xdcDup__1__GC0           |           1|      2758|
|60    |nf_10g_interface_block__xdcDup__2__GC0     |           1|     11027|
|61    |nf_10g_interface__xdcDup__2__GC0           |           1|      2758|
|62    |nf_10g_interface_block__GC0                |           1|     11027|
|63    |nf_10g_interface__GC0                      |           1|      2758|
|64    |top__GC0                                   |           1|      8070|
+------+-------------------------------------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 3600 (col length:200)
BRAMs: 2940 (col length: RAMB18 200 RAMB36 100)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
WARNING: [Synth 8-6014] Unused sequential element wrpp2_inst/count_value_i_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1720]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.next_state_d1_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_d1_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.ge_fwft_d1_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
WARNING: [Synth 8-6014] Unused sequential element wrpp2_inst/count_value_i_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1720]
WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
INFO: [Synth 8-5546] ROM "wack_i" won't be mapped to RAM because it is too sparse
WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
WARNING: [Synth 8-6014] Unused sequential element rst_d2_inst/d_out_reg was removed.  [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1766]
INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25)
WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_shared_cpu_regs_inst/resetn_soft_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_cpu_regs.v:155]
INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25)
WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_cpu_regs_inst/resetn_soft_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:155]
WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_cpu_regs_inst/resetn_soft_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:155]
WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_cpu_regs_inst/resetn_soft_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:155]
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
WARNING: [Synth 8-6014] Unused sequential element gen_wr_b.gen_word_narrow.mem_reg was removed. 
WARNING: [Synth 8-6014] Unused sequential element gen_wr_b.gen_word_narrow.mem_reg was removed. 
WARNING: [Synth 8-6014] Unused sequential element gen_wr_b.gen_word_narrow.mem_reg was removed. 
WARNING: [Synth 8-6014] Unused sequential element gen_wr_b.gen_word_narrow.mem_reg was removed. 
WARNING: [Synth 8-6014] Unused sequential element gen_wr_b.gen_word_narrow.mem_reg was removed. 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[13] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[16] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[17] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[18] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[19] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[21] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[22] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[23] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[24] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[25] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[26] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[27] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[28] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[29] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[13] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[16] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[17] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[18] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[19] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[21] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[22] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[23] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[24] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[25] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[26] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[27] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[28] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[29] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[32] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[33] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[34] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[35] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[36] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[37] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[38] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[39] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[40] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[41] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[42] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[43] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[44] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[45] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[46] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[47] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[48] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[49] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[50] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[51] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[52] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[53] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[54] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[55] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[56] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[57] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[58] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[59] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[60] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[61] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[62] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[63] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[64] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[65] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[66] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[67] )
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-3332] Sequential element (gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized29.
WARNING: [Synth 8-3332] Sequential element (gwdc.wr_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized29.
WARNING: [Synth 8-3332] Sequential element (grdc.rd_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized29.
WARNING: [Synth 8-3332] Sequential element (gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized30.
WARNING: [Synth 8-3332] Sequential element (gwdc.wr_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized30.
WARNING: [Synth 8-3332] Sequential element (grdc.rd_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized30.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized7.
WARNING: [Synth 8-3332] Sequential element (gwdc.wr_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized7.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized7.
WARNING: [Synth 8-3332] Sequential element (grdc.rd_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized7.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized8.
WARNING: [Synth 8-3332] Sequential element (gwdc.wr_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized8.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized8.
WARNING: [Synth 8-3332] Sequential element (grdc.rd_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized8.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized9.
WARNING: [Synth 8-3332] Sequential element (gwdc.wr_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized9.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized9.
WARNING: [Synth 8-3332] Sequential element (grdc.rd_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized9.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized10.
WARNING: [Synth 8-3332] Sequential element (gwdc.wr_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized10.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized10.
WARNING: [Synth 8-3332] Sequential element (grdc.rd_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized10.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[1]) is unused and will be removed from module xpm_fifo_base__parameterized31.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized31.
WARNING: [Synth 8-3332] Sequential element (gwdc.wr_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized31.
WARNING: [Synth 8-3332] Sequential element (grdc.rd_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized31.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[1]) is unused and will be removed from module xpm_fifo_base__parameterized32.
WARNING: [Synth 8-3332] Sequential element (gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized32.
WARNING: [Synth 8-3332] Sequential element (gwdc.wr_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized32.
WARNING: [Synth 8-3332] Sequential element (grdc.rd_data_count_i_reg[0]) is unused and will be removed from module xpm_fifo_base__parameterized32.
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Update_inst/RamRwAddr_r_reg[0][4]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/RamRwAddr_r_reg[0]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Update_inst/RamRwAddr_r_reg[0][5]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/RamRwAddr_r_reg[1]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Update_inst/RamRwAddr_r_reg[0][6]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/RamRwAddr_r_reg[2]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Update_inst/RamRwAddr_r_reg[0][7]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/RamRdMsb_r_reg'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[0]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][0]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[1]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][1]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[2]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][2]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[3]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][3]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[4]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][4]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[5]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][5]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[6]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][6]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[7]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[8]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][8]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[9]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][9]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[10]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][10]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[11]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][11]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[12]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][12]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[13]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][13]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[14]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][14]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[15]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][15]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[16]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][16]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[17]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][17]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[18]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][18]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[19]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][19]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[20]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][20]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[21]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][21]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[22]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][22]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[23]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][23]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[24]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][24]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[25]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][25]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[26]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][26]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[27]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][27]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[28]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][28]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[29]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][29]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[30]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][30]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[31]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][31]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[32]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][32]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[33]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][33]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[34]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][34]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[35]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][35]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[36]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][36]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[37]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][37]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[38]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][38]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[39]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][39]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[40]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][40]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[41]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][41]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[42]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][42]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[43]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][43]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[44]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][44]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[45]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][45]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[46]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][46]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqKey_d1_reg[47]' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Key_p_reg[1][47]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupReqValid_d1_reg' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Valid_p_reg[1]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Look_r1_reg' (FD) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Valid_p_reg[1]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[0]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamAging_Capability_reg[0]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[1]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[4]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[2]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamAging_Capability_reg[0]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[3]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamAging_Capability_reg[0]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[4]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[5]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[6]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamAging_Capability_reg[0]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[7]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamAging_Capability_reg[0]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[7]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamAging_Capability_reg[0]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamAging_Capability_reg[0]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[8]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[8]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[9]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[8]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[9]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[9]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[10]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[9]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[10]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[10]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[11]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[10]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[11]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[11]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[12]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[11]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[12]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[12]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[13]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[12]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[13]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[13]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[14]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[13]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[14]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[14]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[15]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[14]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[15]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[15]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[16]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[15]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[16]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[16]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[17]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[16]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[17]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[17]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[18]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[17]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[18]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[18]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[19]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[18]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[19]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[19]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[20]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[19]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[20]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[20]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[21]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[20]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[21]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[21]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[22]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[21]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[22]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[22]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[23]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[22]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[23]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[23]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[24]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[23]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[24]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[24]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[25]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[24]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[25]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[25]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[26]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/DeviceID__reg[25]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[26]'
INFO: [Synth 8-3886] merging instance 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[26]' (FDRE) to 'nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_5/realmain_lookup_table_0/realmain_lookup_table_0_t_csr_inst/CamSize__reg[27]'
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespAddr_reg[1]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespAddr_reg[0]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[47]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[46]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[45]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[44]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[43]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[42]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[41]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[40]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[39]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[38]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[37]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[36]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[35]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[34]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[33]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[32]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[31]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[30]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[29]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[28]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[27]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[26]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[25]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[24]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[23]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[22]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[21]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[20]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[19]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[18]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[17]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[16]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[15]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[14]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[13]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[12]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[11]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[10]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[9]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[8]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[7]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[6]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[5]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[4]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[3]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[2]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[1]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Cam_inst/LookupRespKey_reg[0]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data1_r2_reg[53]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data1_r2_reg[52]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data1_r2_reg[51]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data2_r2_reg[53]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data2_r2_reg[52]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data2_r2_reg[51]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data3_r2_reg[53]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data3_r2_reg[52]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data3_r2_reg[51]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data4_r2_reg[53]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data4_r2_reg[52]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data4_r2_reg[51]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data0_r2_reg[53]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data0_r2_reg[52]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/Data0_r2_reg[51]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/LookupRespKey_reg[47]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/LookupRespKey_reg[46]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/LookupRespKey_reg[45]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/LookupRespKey_reg[44]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
WARNING: [Synth 8-3332] Sequential element (realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/LookupRespKey_reg[43]) is unused and will be removed from module realmain_lookup_table_0_t_Wrap.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-4471] merging register 'section_start_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4031]
INFO: [Synth 8-4471] merging register 'section_start_inst/p_arp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4151]
INFO: [Synth 8-4471] merging register 'section_start_inst/p_icmp6_option_link_layer_addr_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4123]
INFO: [Synth 8-4471] merging register 'section_start_inst/p_icmp6_na_ns_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4374]
INFO: [Synth 8-4471] merging register 'section_start_inst/p_icmp6_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4147]
INFO: [Synth 8-4471] merging register 'section_start_inst/p_cpu_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4019]
INFO: [Synth 8-4471] merging register 'section_start_inst/p_icmp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3907]
INFO: [Synth 8-4471] merging register 'section_start_inst/p_udp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4295]
INFO: [Synth 8-4471] merging register 'section_start_inst/p_tcp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3943]
INFO: [Synth 8-4471] merging register 'section_start_inst/p_ipv6_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3887]
INFO: [Synth 8-4471] merging register 'section_start_inst/p_ipv4_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4171]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ipv4_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4163]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ipv6_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4402]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_tcp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4095]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_udp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3959]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_icmp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4091]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_cpu_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4035]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_icmp6_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4143]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_icmp6_na_ns_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4398]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4255]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_arp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4243]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_dma_q_size_1_reg[15:0]' into 'section_start_inst/sume_metadata_dma_q_size_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4207]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_nf3_q_size_1_reg[15:0]' into 'section_start_inst/sume_metadata_nf3_q_size_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3883]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_nf2_q_size_1_reg[15:0]' into 'section_start_inst/sume_metadata_nf2_q_size_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3919]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_nf1_q_size_1_reg[15:0]' into 'section_start_inst/sume_metadata_nf1_q_size_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3923]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_nf0_q_size_1_reg[15:0]' into 'section_start_inst/sume_metadata_nf0_q_size_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3911]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_send_dig_to_cpu_1_reg[7:0]' into 'section_start_inst/sume_metadata_send_dig_to_cpu_1_reg[7:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4382]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_drop_1_reg[7:0]' into 'section_start_inst/sume_metadata_drop_1_reg[7:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4155]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_dst_port_1_reg[7:0]' into 'section_start_inst/sume_metadata_dst_port_1_reg[7:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4283]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_src_port_1_reg[7:0]' into 'section_start_inst/sume_metadata_src_port_1_reg[7:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4259]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_pkt_len_1_reg[15:0]' into 'section_start_inst/sume_metadata_pkt_len_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4370]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ethernet_isValid_1_reg[0:0]' into 'section_start_inst/p_ethernet_isValid_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4410]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ethernet_dst_addr_1_reg[47:0]' into 'section_start_inst/p_ethernet_dst_addr_1_reg[47:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3875]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ethernet_src_addr_1_reg[47:0]' into 'section_start_inst/p_ethernet_src_addr_1_reg[47:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3951]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ethernet_ethertype_1_reg[15:0]' into 'section_start_inst/p_ethernet_ethertype_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3935]
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_digest_data_1_unused_1_reg[255:0]' into 'section_start_inst/digest_data_unused_1_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4079]
INFO: [Synth 8-4471] merging register 'section_reject_inst/control_1_reg[21:0]' into 'section_start_inst/control_1_reg[21:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14396]
INFO: [Synth 8-4471] merging register 'section_reject_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14385]
INFO: [Synth 8-4471] merging register 'section_reject_inst/TopParser_fl_1_reg[1946:0]' into 'section_start_inst/TopParser_fl_1_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14416]
INFO: [Synth 8-4471] merging register 'TopParser_fl_3_reg[1946:0]' into 'section_start_inst/TopParser_fl_1_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:915]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/control_increment_offsetEop_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4031]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_arp_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4151]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_icmp6_option_link_layer_addr_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4123]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_icmp6_na_ns_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4374]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_icmp6_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4147]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_cpu_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4019]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_icmp_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3907]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_udp_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4295]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_tcp_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3943]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_ipv6_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3887]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_ipv4_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4171]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ipv4_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4163]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ipv6_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4402]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_tcp_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4095]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_udp_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3959]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_icmp_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4091]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_cpu_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4035]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_icmp6_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4143]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_icmp6_na_ns_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4398]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4255]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_arp_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4243]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_dma_q_size_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4207]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_nf3_q_size_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3883]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_nf2_q_size_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3919]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_nf1_q_size_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3923]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_nf0_q_size_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3911]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_send_dig_to_cpu_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4382]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_drop_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4155]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_dst_port_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4283]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_src_port_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4259]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_pkt_len_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4370]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ethernet_isValid_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4410]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ethernet_dst_addr_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3875]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ethernet_src_addr_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3951]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ethernet_ethertype_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3935]
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_digest_data_1_unused_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4079]
WARNING: [Synth 8-6014] Unused sequential element section_reject_inst/control_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14396]
WARNING: [Synth 8-6014] Unused sequential element section_reject_inst/control_increment_offsetEop_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14385]
WARNING: [Synth 8-6014] Unused sequential element section_reject_inst/TopParser_fl_1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14416]
WARNING: [Synth 8-6014] Unused sequential element TopParser_fl_3_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:915]
INFO: [Synth 8-4471] merging register 'ErrorCheck_inst/EOP_i1_reg[0:0]' into 'PKT_EOP_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:1076]
WARNING: [Synth 8-6014] Unused sequential element ErrorCheck_inst/EOP_i1_reg was removed.  [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:1076]
INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-4471] merging register 'ErrorCheck_inst/EOP_i1_reg[0:0]' into 'PKT_EOP_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:15508]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_p_1_reg[1402:0]' into 'p_1_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3523]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_p_2_reg[1402:0]' into 'p_2_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3524]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_table_id_sec_p_1_reg[1402:0]' into 'p_1_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3568]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_table_id_sec_p_2_reg[1402:0]' into 'p_2_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3569]
INFO: [Synth 8-4471] merging register 'user_metadata_1_reg[159:0]' into 'NoAction_0_sec_user_metadata_1_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3685]
INFO: [Synth 8-4471] merging register 'sume_metadata_1_reg[127:0]' into 'NoAction_0_sec_sume_metadata_1_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3680]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/compute_p_ipv4_src_addr_inst/term1R_reg[127:0]' into 'section_realmain_nat64_static_sec_inst/compute_TopPipe_fl_realmain_src_0_inst/term1R_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7499]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/compute_p_ipv4_src_addr_inst/realmain_nat64_0_resp_1_reg[175:0]' into 'section_realmain_nat64_static_sec_inst/compute_TopPipe_fl_realmain_src_0_inst/realmain_nat64_0_resp_1_reg[175:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7484]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/compute_p_ipv4_dst_addr_inst/term1_reg[127:0]' into 'section_realmain_nat64_static_sec_inst/compute_TopPipe_fl_realmain_dst_0_inst/term1_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7605]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_realmain_nat64_static_sec_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6150]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/control_increment_offsetEop_2_reg[0:0]' into 'section_realmain_nat64_static_sec_inst/control_nextDone_2_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6151]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/p_ipv4_dst_addr_2_reg[31:0]' into 'section_realmain_nat64_static_sec_inst/TopPipe_fl_realmain_dst_0_2_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6146]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/p_ipv6_isValid_1_reg[0:0]' into 'section_realmain_nat64_static_sec_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6126]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/p_ipv6_isValid_2_reg[0:0]' into 'section_realmain_nat64_static_sec_inst/control_nextDone_2_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6127]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/sume_metadata_1_reg[127:0]' into 'NoAction_0_sec_sume_metadata_1_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6220]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/sume_metadata_2_reg[127:0]' into 'NoAction_0_sec_sume_metadata_2_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6221]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/user_metadata_1_reg[159:0]' into 'NoAction_0_sec_user_metadata_1_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6225]
INFO: [Synth 8-4471] merging register 'NoAction_0_sec_user_metadata_2_reg[159:0]' into 'section_realmain_nat64_static_sec_inst/user_metadata_2_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3489]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/user_metadata_chk_ipv4_1_reg[0:0]' into 'section_realmain_nat64_static_sec_inst/p_ipv4_isValid_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6117]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/user_metadata_chk_ipv4_2_reg[0:0]' into 'section_realmain_nat64_static_sec_inst/p_ipv4_isValid_2_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6118]
INFO: [Synth 8-4471] merging register 'NoAction_0_sec_p_1_reg[1402:0]' into 'section_realmain_nat64_static_sec_inst/p_1_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3478]
INFO: [Synth 8-4471] merging register 'user_metadata_2_reg[159:0]' into 'section_realmain_nat64_static_sec_inst/user_metadata_2_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3686]
INFO: [Synth 8-4471] merging register 'sume_metadata_2_reg[127:0]' into 'NoAction_0_sec_sume_metadata_2_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3681]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_sume_metadata_1_reg[127:0]' into 'realmain_controller_debug_table_id_sec_sume_metadata_1_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3528]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_sume_metadata_2_reg[127:0]' into 'realmain_controller_debug_table_id_sec_sume_metadata_2_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3529]
INFO: [Synth 8-4471] merging register 'section_realmain_nat64_static_sec_inst/compute_p_ipv4_src_addr_inst/term2_reg[127:0]' into 'section_realmain_nat64_static_sec_inst/compute_TopPipe_fl_realmain_src_0_inst/term2_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:7489]
WARNING: [Synth 8-3936] Found unconnected internal register 'section_realmain_nat64_static_sec_inst/compute_TopPipe_fl_realmain_src_0_inst/term2_reg' and it is trimmed from '128' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6399]
WARNING: [Synth 8-3936] Found unconnected internal register 'section_realmain_nat64_static_sec_inst/compute_TopPipe_fl_realmain_src_0_inst/term1R_reg' and it is trimmed from '128' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6409]
WARNING: [Synth 8-3936] Found unconnected internal register 'section_realmain_nat64_static_sec_inst/compute_TopPipe_fl_realmain_dst_0_inst/term1_reg' and it is trimmed from '128' to '32' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6515]
WARNING: [Synth 8-3936] Found unconnected internal register 'section_realmain_nat64_static_sec_inst/TopPipe_fl_2_reg' and it is trimmed from '113' to '49' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6201]
WARNING: [Synth 8-3936] Found unconnected internal register 'section_realmain_nat64_static_sec_inst/TopPipe_fl_1_reg' and it is trimmed from '113' to '49' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:6200]
INFO: [Synth 8-4471] merging register 'NoAction_0_sec_TopPipe_fl_1_reg[112:0]' into 'TopPipe_fl_1_reg[112:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3463]
INFO: [Synth 8-4471] merging register 'NoAction_0_sec_TopPipe_fl_2_reg[112:0]' into 'TopPipe_fl_2_reg[112:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3464]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_TopPipe_fl_1_reg[112:0]' into 'TopPipe_fl_1_reg[112:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3508]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_TopPipe_fl_2_reg[112:0]' into 'TopPipe_fl_2_reg[112:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3509]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_table_id_sec_TopPipe_fl_1_reg[112:0]' into 'TopPipe_fl_1_reg[112:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3553]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_table_id_sec_TopPipe_fl_2_reg[112:0]' into 'TopPipe_fl_2_reg[112:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3554]
INFO: [Synth 8-4471] merging register 'NoAction_0_sec_digest_data_1_reg[255:0]' into 'digest_data_1_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3468]
INFO: [Synth 8-4471] merging register 'NoAction_0_sec_digest_data_2_reg[255:0]' into 'digest_data_2_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3469]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_digest_data_1_reg[255:0]' into 'digest_data_1_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3513]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_digest_data_2_reg[255:0]' into 'digest_data_2_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3514]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_table_id_sec_digest_data_1_reg[255:0]' into 'digest_data_1_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3558]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_table_id_sec_digest_data_2_reg[255:0]' into 'digest_data_2_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3559]
INFO: [Synth 8-4471] merging register 'NoAction_0_sec_local_state_1_reg[15:0]' into 'local_state_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3473]
INFO: [Synth 8-4471] merging register 'NoAction_0_sec_local_state_2_reg[15:0]' into 'local_state_2_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3474]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_local_state_1_reg[15:0]' into 'local_state_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3518]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_local_state_2_reg[15:0]' into 'local_state_2_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3519]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_table_id_sec_local_state_1_reg[15:0]' into 'local_state_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3563]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_table_id_sec_local_state_2_reg[15:0]' into 'local_state_2_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3564]
INFO: [Synth 8-4471] merging register 'NoAction_0_sec_realmain_lookup_table_0_req_1_reg[47:0]' into 'realmain_lookup_table_0_req_1_reg[47:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3493]
INFO: [Synth 8-4471] merging register 'NoAction_0_sec_realmain_lookup_table_0_req_2_reg[47:0]' into 'realmain_lookup_table_0_req_2_reg[47:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3494]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_realmain_lookup_table_0_req_1_reg[47:0]' into 'realmain_lookup_table_0_req_1_reg[47:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3538]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_sec_realmain_lookup_table_0_req_2_reg[47:0]' into 'realmain_lookup_table_0_req_2_reg[47:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3539]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_table_id_sec_realmain_lookup_table_0_req_1_reg[47:0]' into 'realmain_lookup_table_0_req_1_reg[47:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3583]
INFO: [Synth 8-4471] merging register 'realmain_controller_debug_table_id_sec_realmain_lookup_table_0_req_2_reg[47:0]' into 'realmain_lookup_table_0_req_2_reg[47:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3584]
INFO: [Synth 8-4471] merging register 'NoAction_0_sec_realmain_nat64_0_resp_1_reg[307:0]' into 'realmain_nat64_0_resp_1_reg[307:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:3498]
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5546] ROM "compute_control_nextSection_inst/flag1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "compute_control_nextSection_inst/term1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5784] Optimized 5 bits of RAM "RAM/RAM_reg" due to constant propagation. Old ram width 44 bits, new ram width 39 bits.
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5546] ROM "DscFifo_inst/empty" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DscFifo_inst/full" won't be mapped to RAM because it is too sparse
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE 
INFO: [Common 17-14] Message 'Synth 8-5775' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5784] Optimized 1 bits of RAM "gen_wr_a.gen_word_narrow.mem_reg" due to constant propagation. Old ram width 266 bits, new ram width 265 bits.
INFO: [Synth 8-5546] ROM "wack_i" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "S_RESET_clk_control/wwb9tx90f0u48ee9whodzx_707" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "S_RESET_clk_lookup/qv2nvn0ml7fv931vyldv_203" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "S_RESET_clk_line/kfw5rcmmtazfzl5uicmzk_223" won't be mapped to RAM because it is too sparse
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord0" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord1" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord2" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord3" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord4" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord5" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord6" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-3936] Found unconnected internal register 'drp_ipif_i/synch_1/q_reg' and it is trimmed from '34' to '33' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/hdl/ten_gig_eth_pcs_pma_v6_0_rfs.v:40303]
INFO: [Synth 8-3936] Found unconnected internal register 'drp_ipif_i/synch_1/d_reg_reg' and it is trimmed from '34' to '33' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/hdl/ten_gig_eth_pcs_pma_v6_0_rfs.v:40277]
INFO: [Synth 8-5587] ROM size for "gt_txc_mux" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port is_eval driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port gt_progdiv_reset driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[4] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[3] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[2] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[1] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[0] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[4] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[3] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[2] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[1] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[0] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[6] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[5] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[4] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[3] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[2] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[1] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[0] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port txdiffctrl[4] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port txdiffctrl[3] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port txdiffctrl[2] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port txdiffctrl[1] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port txdiffctrl[0] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[15] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[14] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[13] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[12] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[11] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[10] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[9] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[8] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[7] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[6] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[5] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[4] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[3] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[2] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[1] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[0] driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rdack driven by constant 0
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_wrack driven by constant 0
INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "broadcast_detect" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits.
INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM.
INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5545] ROM "broadcast_detect" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits.
INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM.
INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits.
INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM.
INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits.
INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:08:26 ; elapsed = 00:09:37 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 1928 ; free virtual = 10280
---------------------------------------------------------------------------------
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_7 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_8 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_9 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_10 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_11 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_12 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_13 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_14 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_15 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_16 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_17 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_18 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_19 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_7 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_8 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_9 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_10 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_11 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_12 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_13 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_14 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_15 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_16 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_17 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_18 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_19 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_7 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_8 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_9 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_10 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_11 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_12 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_13 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_14 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_15 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_16 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_17 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_18 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_19 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Common 17-14] Message 'Synth 8-4480' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.

Report RTL Partitions: 
+------+-------------------------------------------+------------+----------+
|      |RTL Partition                              |Replication |Instances |
+------+-------------------------------------------+------------+----------+
|1     |clk_wiz_ip_clk_wiz__GC0                    |           1|        13|
|2     |TopParser_t_EngineStage_0__GB0             |           1|     18385|
|3     |TopParser_t_EngineStage_0__GB1             |           1|     25891|
|4     |TopParser_t_EngineStage_0__GB2             |           1|     28664|
|5     |TopParser_t_EngineStage_0__GB3             |           1|     16353|
|6     |TopParser_t_EngineStage_0__GB4             |           1|      7256|
|7     |TopParser_t_EngineStage_1__GB0             |           1|     15198|
|8     |TopParser_t_EngineStage_1__GB1             |           1|     11997|
|9     |TopParser_t_EngineStage_1__GB2             |           1|     13633|
|10    |TopParser_t_EngineStage_1__GB3             |           1|      7788|
|11    |TopParser_t_EngineStage_1__GB4             |           1|     12936|
|12    |TopParser_t_Engine__GC0                    |           1|       398|
|13    |TopParser_t__GC0                           |           1|        20|
|14    |TopPipe_lvl_0_t_EngineStage_2__GB0         |           1|     12941|
|15    |TopPipe_lvl_0_t_EngineStage_2__GB1         |           1|      5252|
|16    |TopPipe_lvl_0_t_EngineStage_2__GB2         |           1|      4423|
|17    |TopPipe_lvl_0_t_Engine__GCB0               |           1|     20103|
|18    |TopPipe_lvl_0_t_Engine__GCB1               |           1|     12472|
|19    |TopPipe_lvl_0_t_Engine__GCB2               |           1|     16646|
|20    |TopPipe_lvl_0_t_EngineStage_8              |           1|     16779|
|21    |TopPipe_lvl_0_t_Engine__GCB4               |           1|     37371|
|22    |TopPipe_lvl_0_t_EngineStage_5              |           1|     10994|
|23    |TopPipe_lvl_0_t_Engine__GCB6               |           1|      4937|
|24    |TopPipe_lvl_0_t_Engine__GCB7               |           1|     18648|
|25    |TopPipe_lvl_0_t_Engine__GCB8               |           1|     14506|
|26    |TopPipe_lvl_0_t_Engine__GCB9               |           1|     13783|
|27    |TopPipe_lvl_1_t_EngineStage_1              |           1|     16533|
|28    |TopPipe_lvl_1_t_Engine__GB1                |           1|     24128|
|29    |TopPipe_lvl_1_t_Engine__GB2                |           1|      4735|
|30    |TopPipe_lvl_1_t_Engine__GB3                |           1|      7910|
|31    |TopPipe_lvl_1_t_Engine__GB4                |           1|         1|
|32    |TopDeparser_t_EngineStage_0__GB0           |           1|     19223|
|33    |TopDeparser_t_EngineStage_0__GB1           |           1|      3041|
|34    |TopDeparser_t_EngineStage_0__GB2           |           1|     14013|
|35    |reg__2029                                  |           1|      1403|
|36    |TopDeparser_t_EngineStage_2_Editor__GB0    |           1|     21243|
|37    |TopDeparser_t_EngineStage_2_Editor__GB1    |           1|      6970|
|38    |TopDeparser_t_EngineStage_2__GC0           |           1|     16354|
|39    |TopDeparser_t_Engine__GC0                  |           1|     20467|
|40    |TopDeparser_t__GC0                         |           1|        22|
|41    |SimpleSumeSwitch__GCB0                     |           1|     18487|
|42    |S_SYNCER_for_TopDeparser                   |           1|      4735|
|43    |SimpleSumeSwitch__GCB2                     |           1|     11007|
|44    |SimpleSumeSwitch__GCB3                     |           1|     31308|
|45    |SimpleSumeSwitch__GCB4                     |           1|      6402|
|46    |nf_sume_sdnet__GC0                         |           1|        11|
|47    |nf_datapath__GCB0                          |           1|     14815|
|48    |nf_datapath__GCB1                          |           1|      9225|
|49    |bd_a1aa_xpcs_0_shared_clock_and_reset__GC0 |           1|        53|
|50    |ten_gig_eth_pcs_pma_v6_0_13                |           4|      9273|
|51    |bd_a1aa_xpcs_0_block__GC0                  |           1|       674|
|52    |bd_a1aa_xpcs_0_support__GC0                |           1|         2|
|53    |bd_a1aa__GC0                               |           1|      9790|
|54    |nf_10g_interface_shared_block__GC0         |           1|      7932|
|55    |nf_10g_interface_shared__GC0               |           1|      1851|
|56    |bd_7ad4_xmac_0_block                       |           3|      9790|
|57    |bd_7ad4_xpcs_0_block__GC0                  |           3|       674|
|58    |nf_10g_interface_block__xdcDup__1__GC0     |           1|      7932|
|59    |nf_10g_interface__xdcDup__1__GC0           |           1|      1789|
|60    |nf_10g_interface_block__xdcDup__2__GC0     |           1|      7932|
|61    |nf_10g_interface__xdcDup__2__GC0           |           1|      1789|
|62    |nf_10g_interface_block__GC0                |           1|      7932|
|63    |nf_10g_interface__GC0                      |           1|      1789|
|64    |top__GC0                                   |           1|      7748|
+------+-------------------------------------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/clk_wiz_1/clk_out1' to pin 'control_sub_i/nf_mbsys/clk_wiz_1/bbstub_clk_out1/O'
INFO: [Synth 8-5783] Moving clock source from hierarchical pin 'control_sub_i/nf_mbsys/clk_wiz_1/clk_in1' to 'axi_lite_bufg0/I'
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/Dbg_Clk_0' to pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/bbstub_Dbg_Clk_0/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/Dbg_Update_0' to pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/bbstub_Dbg_Update_0/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr/BRAM_Clk_A' to pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr/bbstub_BRAM_Clk_A/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr/BRAM_Clk_A' to pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr/bbstub_BRAM_Clk_A/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/dma_sub/pcie3_7x_1/user_clk' to pin 'control_sub_i/dma_sub/pcie3_7x_1/bbstub_user_clk/O'
WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 75 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:75]
WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 75 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:75]
WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 75 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:75]
WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 76 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:76]
INFO: [Synth 8-5578] Moved timing constraint from pin 'axi_clocking_i/clk_wiz_i/inst/clk_in1' to pin 'axi_clocking_i/clkin1_buf/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'axi_clocking_i/clk_wiz_i/clk_out1' to pin 'clkout1_buf/O'
WARNING: [Synth 8-565] redefining clock 'xphy_refclk_p'
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK'
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK'
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK'
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK'
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK'
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK'
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK'
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK'
INFO: [Synth 8-5819] Moved 9 constraints on hierarchical pins to their respective driving/loading pins
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:09:10 ; elapsed = 00:10:23 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 1275 ; free virtual = 9869
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:10:34 ; elapsed = 00:11:49 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 1236 ; free virtual = 9822
---------------------------------------------------------------------------------

Report RTL Partitions: 
+------+-------------------------------------------+------------+----------+
|      |RTL Partition                              |Replication |Instances |
+------+-------------------------------------------+------------+----------+
|1     |clk_wiz_ip_clk_wiz__GC0                    |           1|        13|
|2     |TopParser_t_EngineStage_0__GB0             |           1|       623|
|3     |TopParser_t_EngineStage_0__GB1             |           1|       276|
|4     |TopParser_t_EngineStage_0__GB2             |           1|       113|
|5     |TopParser_t_EngineStage_0__GB3             |           1|      1685|
|6     |TopParser_t_EngineStage_0__GB4             |           1|      5325|
|7     |TopParser_t_EngineStage_1__GB0             |           1|      1183|
|8     |TopParser_t_EngineStage_1__GB1             |           1|       339|
|9     |TopParser_t_EngineStage_1__GB2             |           1|         1|
|10    |TopParser_t_EngineStage_1__GB4             |           1|      4032|
|11    |TopParser_t_Engine__GC0                    |           1|       398|
|12    |TopParser_t__GC0                           |           1|        17|
|13    |TopPipe_lvl_0_t_EngineStage_2__GB0         |           1|     12795|
|14    |TopPipe_lvl_0_t_EngineStage_2__GB1         |           1|      5187|
|15    |TopPipe_lvl_0_t_EngineStage_2__GB2         |           1|      3656|
|16    |TopPipe_lvl_0_t_Engine__GCB0               |           1|     14476|
|17    |TopPipe_lvl_0_t_Engine__GCB1               |           1|     12244|
|18    |TopPipe_lvl_0_t_Engine__GCB2               |           1|     16423|
|19    |TopPipe_lvl_0_t_EngineStage_8              |           1|     16497|
|20    |TopPipe_lvl_0_t_Engine__GCB4               |           1|     24069|
|21    |TopPipe_lvl_0_t_EngineStage_5              |           1|     10839|
|22    |TopPipe_lvl_0_t_Engine__GCB6               |           1|      4857|
|23    |TopPipe_lvl_0_t_Engine__GCB7               |           1|     18330|
|24    |TopPipe_lvl_0_t_Engine__GCB8               |           1|     14282|
|25    |TopPipe_lvl_0_t_Engine__GCB9               |           1|      7205|
|26    |TopPipe_lvl_1_t_EngineStage_1              |           1|     13433|
|27    |TopPipe_lvl_1_t_Engine__GB1                |           1|      5896|
|28    |TopPipe_lvl_1_t_Engine__GB2                |           1|      3815|
|29    |TopPipe_lvl_1_t_Engine__GB3                |           1|      7799|
|30    |TopDeparser_t_EngineStage_0__GB0           |           1|     17398|
|31    |TopDeparser_t_EngineStage_0__GB1           |           1|      2465|
|32    |TopDeparser_t_EngineStage_0__GB2           |           1|      2329|
|33    |reg__2029                                  |           1|       179|
|34    |TopDeparser_t_EngineStage_2_Editor__GB0    |           1|     18952|
|35    |TopDeparser_t_EngineStage_2_Editor__GB1    |           1|      6932|
|36    |TopDeparser_t_EngineStage_2__GC0           |           1|      5960|
|37    |TopDeparser_t_Engine__GC0                  |           1|      7506|
|38    |TopDeparser_t__GC0                         |           1|         3|
|39    |SimpleSumeSwitch__GCB0                     |           1|     18487|
|40    |S_SYNCER_for_TopDeparser                   |           1|      4735|
|41    |SimpleSumeSwitch__GCB2                     |           1|     11005|
|42    |SimpleSumeSwitch__GCB3                     |           1|     31177|
|43    |SimpleSumeSwitch__GCB4                     |           1|      6402|
|44    |nf_sume_sdnet__GC0                         |           1|        11|
|45    |nf_datapath__GCB0                          |           1|     14808|
|46    |nf_datapath__GCB1                          |           1|      9225|
|47    |bd_a1aa_xpcs_0_shared_clock_and_reset__GC0 |           1|        53|
|48    |ten_gig_eth_pcs_pma_v6_0_13                |           4|      9273|
|49    |bd_a1aa_xpcs_0_block__GC0                  |           1|       674|
|50    |bd_a1aa_xpcs_0_support__GC0                |           1|         2|
|51    |bd_a1aa__GC0                               |           1|      9790|
|52    |nf_10g_interface_shared_block__GC0         |           1|      7932|
|53    |nf_10g_interface_shared__GC0               |           1|      1851|
|54    |bd_7ad4_xmac_0_block                       |           3|      9790|
|55    |bd_7ad4_xpcs_0_block__GC0                  |           3|       674|
|56    |nf_10g_interface_block__xdcDup__1__GC0     |           1|      7932|
|57    |nf_10g_interface__xdcDup__1__GC0           |           1|      1789|
|58    |nf_10g_interface_block__xdcDup__2__GC0     |           1|      7932|
|59    |nf_10g_interface__xdcDup__2__GC0           |           1|      1789|
|60    |nf_10g_interface_block__GC0                |           1|      7932|
|61    |nf_10g_interface__GC0                      |           1|      1789|
|62    |top__GC0                                   |           1|      7748|
+------+-------------------------------------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met 
INFO: [Synth 8-4765] Removing register instance (\S_BRIDGER_for_realmain_nat64_0_tuple_in_request/rd_en_d1_reg__0 ) from module (SimpleSumeSwitch__GCB4) as it is equivalent to (\S_BRIDGER_for_realmain_nat64_0_tuple_in_request/rd_en_d1_reg ) and driving same net [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_nat64_0_tuple_in_request.v:80]
INFO: [Synth 8-4765] Removing register instance (\S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/rd_en_d1_reg ) from module (SimpleSumeSwitch__GCB4) as it is equivalent to (\S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/rd_en_d1_reg__0 ) and driving same net [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request.v:89]
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:12:23 ; elapsed = 00:13:43 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 1353 ; free virtual = 9926
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
INFO: [Synth 8-5365] Flop stage_0/ErrorCheck_inst/validBits_i1_reg[10] is being inverted and renamed to stage_0/ErrorCheck_inst/validBits_i1_reg[10]_inv.
INFO: [Synth 8-5365] Flop stage_10/section_condition_sec_inst/compute_control_nextSection_inst/term10L_reg[0] is being inverted and renamed to stage_10/section_condition_sec_inst/compute_control_nextSection_inst/term10L_reg[0]_inv.
INFO: [Synth 8-5365] Flop stage_0/ErrorCheck_inst/validBits_i1_reg[10] is being inverted and renamed to stage_0/ErrorCheck_inst/validBits_i1_reg[10]_inv.
INFO: [Synth 8-5365] Flop inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT______TopDeparser_BACKPRESSURE_3_reg is being inverted and renamed to inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT______TopDeparser_BACKPRESSURE_3_reg_inv.
INFO: [Synth 8-6064] Net \inst/wr_en [4] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver. 
INFO: [Synth 8-6064] Net \inst/wr_en [3] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver. 
INFO: [Synth 8-6064] Net \inst/wr_en [2] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver. 
INFO: [Synth 8-6064] Net \inst/wr_en [1] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver. 
INFO: [Synth 8-6064] Net \inst/wr_en [0] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver. 
INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156  is sub-optimal because some of its loads are not in same hierarchy as its driver   
INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas.
INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156  is sub-optimal because some of its loads are not in same hierarchy as its driver   
INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas.
INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156  is sub-optimal because some of its loads are not in same hierarchy as its driver   
INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas.
INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156  is sub-optimal because some of its loads are not in same hierarchy as its driver   
INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas.
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
WARNING: [Synth 8-3295] tying undriven pin m_axis_rx_tready_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin m_axis_rx_tready_inferred:in0 to constant 0
INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:12:33 ; elapsed = 00:13:53 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 1353 ; free virtual = 9925
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:12:34 ; elapsed = 00:13:54 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 1353 ; free virtual = 9926
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:12:56 ; elapsed = 00:14:16 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 1333 ; free virtual = 9906
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:12:57 ; elapsed = 00:14:17 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 1333 ; free virtual = 9906
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:13:07 ; elapsed = 00:14:28 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 1332 ; free virtual = 9904
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:13:08 ; elapsed = 00:14:29 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 1331 ; free virtual = 9904
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+------+------------------------------------+----------+
|      |BlackBox name                       |Instances |
+------+------------------------------------+----------+
|1     |control_sub_xbar_0                  |         1|
|2     |control_sub_m00_data_fifo_0         |         1|
|3     |control_sub_m01_data_fifo_0         |         1|
|4     |control_sub_m02_data_fifo_0         |         1|
|5     |control_sub_m03_data_fifo_0         |         1|
|6     |control_sub_m04_data_fifo_0         |         1|
|7     |control_sub_m05_data_fifo_0         |         1|
|8     |control_sub_m06_data_fifo_0         |         1|
|9     |control_sub_m07_data_fifo_0         |         1|
|10    |control_sub_m08_data_fifo_0         |         1|
|11    |control_sub_auto_cc_0               |         1|
|12    |control_sub_s00_data_fifo_0         |         1|
|13    |control_sub_axi_clock_converter_0_0 |         1|
|14    |control_sub_axis_dwidth_dma_rx_0    |         1|
|15    |control_sub_axis_dwidth_dma_tx_0    |         1|
|16    |control_sub_axis_fifo_10g_rx_0      |         1|
|17    |control_sub_axis_fifo_10g_tx_0      |         1|
|18    |control_sub_nf_riffa_dma_1_0        |         1|
|19    |control_sub_pcie3_7x_1_0            |         1|
|20    |control_sub_pcie_reset_inv_0        |         1|
|21    |control_sub_axi_iic_0_0             |         1|
|22    |control_sub_axi_uartlite_0_0        |         1|
|23    |control_sub_clk_wiz_1_0             |         1|
|24    |control_sub_xbar_1                  |         1|
|25    |control_sub_mdm_1_0                 |         1|
|26    |control_sub_microblaze_0_0          |         1|
|27    |control_sub_microblaze_0_axi_intc_0 |         1|
|28    |control_sub_microblaze_0_xlconcat_0 |         1|
|29    |control_sub_rst_clk_wiz_1_100M_0    |         1|
|30    |control_sub_dlmb_bram_if_cntlr_0    |         1|
|31    |control_sub_dlmb_v10_0              |         1|
|32    |control_sub_ilmb_bram_if_cntlr_0    |         1|
|33    |control_sub_ilmb_v10_0              |         1|
|34    |control_sub_lmb_bram_0              |         1|
+------+------------------------------------+----------+

Report Cell Usage: 
+------+------------------------------------+-------+
|      |Cell                                |Count  |
+------+------------------------------------+-------+
|1     |control_sub_auto_cc_0               |      1|
|2     |control_sub_axi_clock_converter_0_0 |      1|
|3     |control_sub_axi_iic_0_0             |      1|
|4     |control_sub_axi_uartlite_0_0        |      1|
|5     |control_sub_axis_dwidth_dma_rx_0    |      1|
|6     |control_sub_axis_dwidth_dma_tx_0    |      1|
|7     |control_sub_axis_fifo_10g_rx_0      |      1|
|8     |control_sub_axis_fifo_10g_tx_0      |      1|
|9     |control_sub_clk_wiz_1_0             |      1|
|10    |control_sub_dlmb_bram_if_cntlr_0    |      1|
|11    |control_sub_dlmb_v10_0              |      1|
|12    |control_sub_ilmb_bram_if_cntlr_0    |      1|
|13    |control_sub_ilmb_v10_0              |      1|
|14    |control_sub_lmb_bram_0              |      1|
|15    |control_sub_m00_data_fifo_0         |      1|
|16    |control_sub_m01_data_fifo_0         |      1|
|17    |control_sub_m02_data_fifo_0         |      1|
|18    |control_sub_m03_data_fifo_0         |      1|
|19    |control_sub_m04_data_fifo_0         |      1|
|20    |control_sub_m05_data_fifo_0         |      1|
|21    |control_sub_m06_data_fifo_0         |      1|
|22    |control_sub_m07_data_fifo_0         |      1|
|23    |control_sub_m08_data_fifo_0         |      1|
|24    |control_sub_mdm_1_0                 |      1|
|25    |control_sub_microblaze_0_0          |      1|
|26    |control_sub_microblaze_0_axi_intc_0 |      1|
|27    |control_sub_microblaze_0_xlconcat_0 |      1|
|28    |control_sub_nf_riffa_dma_1_0        |      1|
|29    |control_sub_pcie3_7x_1_0            |      1|
|30    |control_sub_pcie_reset_inv_0        |      1|
|31    |control_sub_rst_clk_wiz_1_100M_0    |      1|
|32    |control_sub_s00_data_fifo_0         |      1|
|33    |control_sub_xbar_0                  |      1|
|34    |control_sub_xbar_1                  |      1|
|35    |BUFG                                |      4|
|36    |BUFGCE                              |      1|
|37    |BUFH                                |      5|
|38    |CARRY4                              |   1896|
|39    |FIFO36E1                            |      4|
|40    |FIFO36E1_1                          |      4|
|41    |GTHE2_CHANNEL                       |      4|
|42    |GTHE2_COMMON                        |      1|
|43    |IBUFDS_GTE2                         |      2|
|44    |LUT1                                |   1597|
|45    |LUT2                                |   9029|
|46    |LUT3                                |  25802|
|47    |LUT4                                |  10416|
|48    |LUT5                                |   9828|
|49    |LUT6                                |  25912|
|50    |MMCME2_ADV                          |      1|
|51    |MUXCY_L                             |    176|
|52    |MUXF7                               |    382|
|53    |MUXF8                               |      1|
|54    |RAM128X1D                           |     24|
|55    |RAM32M                              |    192|
|56    |RAM64M                              |    342|
|57    |RAM64X1D                            |     42|
|58    |RAMB18E1                            |     11|
|59    |RAMB18E1_1                          |      5|
|60    |RAMB18E1_2                          |      5|
|61    |RAMB18E1_3                          |      5|
|62    |RAMB18E1_4                          |     12|
|63    |RAMB18E1_5                          |     20|
|64    |RAMB36E1_1                          |    155|
|65    |RAMB36E1_10                         |      1|
|66    |RAMB36E1_11                         |     28|
|67    |RAMB36E1_2                          |     70|
|68    |RAMB36E1_3                          |    160|
|69    |RAMB36E1_4                          |     35|
|70    |RAMB36E1_5                          |     86|
|71    |RAMB36E1_6                          |     24|
|72    |RAMB36E1_7                          |      1|
|73    |RAMB36E1_8                          |      1|
|74    |RAMB36E1_9                          |      1|
|75    |SRL16                               |      1|
|76    |SRL16E                              |   3614|
|77    |FDCE                                |     74|
|78    |FDPE                                |    318|
|79    |FDR                                 |      8|
|80    |FDRE                                | 171635|
|81    |FDSE                                |   2091|
|82    |LDCE                                |      4|
|83    |IBUF                                |     27|
|84    |IBUFDS                              |      1|
|85    |IOBUF                               |      2|
|86    |OBUF                                |     33|
+------+------------------------------------+-------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:13:08 ; elapsed = 00:14:29 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 1331 ; free virtual = 9904
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 32343 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:10:16 ; elapsed = 00:11:35 . Memory (MB): peak = 4616.531 ; gain = 1055.098 ; free physical = 4314 ; free virtual = 12887
Synthesis Optimization Complete : Time (s): cpu = 00:13:09 ; elapsed = 00:14:31 . Memory (MB): peak = 4616.531 ; gain = 3294.316 ; free physical = 4327 ; free virtual = 12884
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 3724 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-35] Removing redundant IBUF, axi_clocking_i/clk_wiz_i/inst/clkin1_ibufg, from the path connected to top-level port: fpga_sysclk_p 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
INFO: [Opt 31-140] Inserted 8 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 8 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 676 instances were transformed.
  (MUXCY,XORCY) => CARRY4: 64 instances
  BUFGCE => BUFGCTRL: 1 instances
  FDR => FDRE: 8 instances
  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
  RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 192 instances
  RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 342 instances
  RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 42 instances
  SRL16 => SRL16E: 1 instances

INFO: [Common 17-83] Releasing license: Synthesis
1772 Infos, 784 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:13:50 ; elapsed = 00:15:09 . Memory (MB): peak = 4632.539 ; gain = 3310.324 ; free physical = 4328 ; free virtual = 12885
WARNING: [Constraints 18-5210] No constraint will be written out.
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/top.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:53 ; elapsed = 00:00:48 . Memory (MB): peak = 4656.551 ; gain = 24.012 ; free physical = 4296 ; free virtual = 12894
INFO: [runtcl-4] Executing : report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4656.551 ; gain = 0.000 ; free physical = 4294 ; free virtual = 12893
INFO: [Common 17-206] Exiting Vivado at Wed Jul 24 23:51:22 2019...
[Wed Jul 24 23:51:22 2019] synth finished
wait_on_run: Time (s): cpu = 00:41:09 ; elapsed = 01:01:55 . Memory (MB): peak = 2872.781 ; gain = 0.000 ; free physical = 6806 ; free virtual = 14836
# launch_runs impl_1 -to_step write_bitstream
[Wed Jul 24 23:51:24 2019] Launched synth_1...
Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth_1/runme.log
[Wed Jul 24 23:51:24 2019] Launched impl_1...
Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/runme.log
# wait_on_run impl_1
[Wed Jul 24 23:51:24 2019] Waiting for impl_1 to finish...

*** Running vivado
    with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace


****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source top.tcl -notrace
Command: link_design -top top -part xc7vx690tffg1761-3
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0.dcp' for cell 'control_sub_i/dma_sub/axi_clock_converter_0'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0.dcp' for cell 'control_sub_i/dma_sub/nf_riffa_dma_1'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0.dcp' for cell 'control_sub_i/dma_sub/pcie3_7x_1'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0.dcp' for cell 'control_sub_i/dma_sub/pcie_reset_inv'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_iic_0'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_uartlite_0'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.dcp' for cell 'control_sub_i/nf_mbsys/clk_wiz_1'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram'
INFO: [Netlist 29-17] Analyzing 5150 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc:50]
get_clocks: Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 3550.098 ; gain = 1022.805 ; free physical = 4453 ; free virtual = 12518
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst'
INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc:124]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc:57]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
WARNING: [Constraints 18-619] A clock with name 'xphy_refclk_p' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:92]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:114]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:115]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:116]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:117]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:118]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:119]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:120]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:121]
INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:149]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Common 17-14] Message 'Vivado 12-3272' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Common 17-14] Message 'XPM_CDC_GRAY: TCL 1000' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. 
     Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. 
     Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Generating merged BMM file for the design top 'top'...
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/data/mb_bootloop_le.elf 
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 900 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
  LUT6_2 => LUT6_2 (LUT5, LUT6): 80 instances
  RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 367 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances
  RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 351 instances
  RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 42 instances

148 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:02:23 ; elapsed = 00:02:57 . Memory (MB): peak = 4771.598 ; gain = 3447.195 ; free physical = 4649 ; free virtual = 12720
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4646 ; free virtual = 12718

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1402240af

Time (s): cpu = 00:00:20 ; elapsed = 00:00:07 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4381 ; free virtual = 12448

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 25 inverter(s) to 100 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 17dfaa891

Time (s): cpu = 00:00:40 ; elapsed = 00:00:29 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4647 ; free virtual = 12715
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 18 inverter(s) to 50 load pin(s).
Phase 2 Constant propagation | Checksum: 1b337fea4

Time (s): cpu = 00:00:47 ; elapsed = 00:00:36 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4649 ; free virtual = 12717
INFO: [Opt 31-389] Phase Constant propagation created 1240 cells and removed 2983 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 16d2e5c1b

Time (s): cpu = 00:02:58 ; elapsed = 00:02:47 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4650 ; free virtual = 12718
INFO: [Opt 31-389] Phase Sweep created 9 cells and removed 89946 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: f867f715

Time (s): cpu = 00:03:01 ; elapsed = 00:02:51 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4649 ; free virtual = 12717
INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 2 cells.

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 1672e8bf6

Time (s): cpu = 00:03:08 ; elapsed = 00:02:58 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4655 ; free virtual = 12723
INFO: [Opt 31-389] Phase Shift Register Optimization created 1 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 10b83d1fa

Time (s): cpu = 00:03:13 ; elapsed = 00:03:02 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4654 ; free virtual = 12722
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 20 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.36 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4654 ; free virtual = 12722
Ending Logic Optimization Task | Checksum: 1b7d7e764

Time (s): cpu = 00:03:14 ; elapsed = 00:03:03 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4655 ; free virtual = 12723

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.047 | TNS=0.000 |
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 1 BRAM(s) out of a total of 564 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 43 WE to EN ports
Number of BRAM Ports augmented: 130 newly gated: 125 Total Ports: 1128
Ending PowerOpt Patch Enables Task | Checksum: 1861721fa

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4316 ; free virtual = 12384
Ending Power Optimization Task | Checksum: 1861721fa

Time (s): cpu = 00:02:57 ; elapsed = 00:01:13 . Memory (MB): peak = 5563.586 ; gain = 791.988 ; free physical = 4550 ; free virtual = 12618

Starting Final Cleanup Task

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Logic Optimization Task | Checksum: 211f4088b

Time (s): cpu = 00:00:30 ; elapsed = 00:00:15 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4571 ; free virtual = 12639
Ending Final Cleanup Task | Checksum: 211f4088b

Time (s): cpu = 00:00:30 ; elapsed = 00:00:16 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4571 ; free virtual = 12639
INFO: [Common 17-83] Releasing license: Implementation
171 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:07:08 ; elapsed = 00:04:44 . Memory (MB): peak = 5563.586 ; gain = 791.988 ; free physical = 4571 ; free virtual = 12639
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.10 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4548 ; free virtual = 12624
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_opt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:55 ; elapsed = 00:00:48 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4517 ; free virtual = 12628
INFO: [runtcl-4] Executing : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:23 ; elapsed = 00:00:12 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4480 ; free virtual = 12592
Command: place_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/ENBWREN (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[0] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[1] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[2] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4479 ; free virtual = 12591
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1547ea0fd

Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.32 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4479 ; free virtual = 12591
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4476 ; free virtual = 12589

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
	control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
	control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
	control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
	control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [Place 30-139] Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.

	control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23
	control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 120bdf31f

Time (s): cpu = 00:01:06 ; elapsed = 00:00:34 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4246 ; free virtual = 12359

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 226d5a904

Time (s): cpu = 00:02:19 ; elapsed = 00:01:04 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3911 ; free virtual = 12023

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 226d5a904

Time (s): cpu = 00:02:20 ; elapsed = 00:01:05 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3910 ; free virtual = 12023
Phase 1 Placer Initialization | Checksum: 226d5a904

Time (s): cpu = 00:02:20 ; elapsed = 00:01:05 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3910 ; free virtual = 12023

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 20d9d4ba2

Time (s): cpu = 00:02:58 ; elapsed = 00:01:18 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3786 ; free virtual = 11899

Phase 2.2 Physical Synthesis In Placer
WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins.
INFO: [Physopt 32-76] Pass 1. Identified 3 candidate nets for fanout optimization.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_RESET_clk_lookup/Rst. Replicated 8 times.
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_reset_i/cpllreset. Replicated 13 times.
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/SS[0]. Replicated 13 times.
WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins.
INFO: [Physopt 32-232] Optimized 3 nets. Created 34 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 3 nets or cells. Created 34 new cells, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.40 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3692 ; free virtual = 11805
INFO: [Physopt 32-64] No nets found for fanout-optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_445 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_446 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__0 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].metadata_fifo/fifo/metadata_wr_en[4] could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].metadata_fifo/fifo/queue_reg_0_i_1__8 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__0 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_23_i_1_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_23_i_1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__0 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_3_i_1__0_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_3_i_1__0 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_1[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Hash_Lookup_inst/i_/xpm_memory_tdpram_inst_i_4 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[1].output_fifo/fifo/queue_reg_0_i_1__6_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[1].output_fifo/fifo/queue_reg_0_i_1__6 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_1[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Hash_Lookup_inst/i_/xpm_memory_tdpram_inst_i_5 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[1].output_fifo/fifo/queue_reg_13_i_1__2_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[1].output_fifo/fifo/queue_reg_13_i_1__2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Update_inst/realmain_lookup_table_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_0[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Update_inst/realmain_lookup_table_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/RamWrData[51] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/xpm_memory_tdpram_inst_i_393 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_13_i_1_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_13_i_1 could not be replicated
INFO: [Physopt 32-117] Net nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/converter_tx/nf_converter/input_fifo/SLAVE_WIDER.counter_reg[0][0] could not be optimized because driver nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/converter_tx/nf_converter/input_fifo/queue_reg_0_i_74 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/RamWrData[49] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/xpm_memory_tdpram_inst_i_395 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/RamWrData[45] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/xpm_memory_tdpram_inst_i_399 could not be replicated
INFO: [Physopt 32-68] No nets found for critical-cell optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3700 ; free virtual = 11813

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------
|  Optimization       |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------
|  Very High Fanout   |           34  |              0  |                     3  |           0  |           1  |  00:00:04  |
|  Fanout             |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Critical Cell      |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total              |           34  |              0  |                     3  |           0  |           3  |  00:00:04  |
-----------------------------------------------------------------------------------------------------------------------------


Phase 2.2 Physical Synthesis In Placer | Checksum: 1bc22b310

Time (s): cpu = 00:08:42 ; elapsed = 00:03:35 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3691 ; free virtual = 11804
Phase 2 Global Placement | Checksum: 2306353e4

Time (s): cpu = 00:08:52 ; elapsed = 00:03:40 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3781 ; free virtual = 11893

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 2306353e4

Time (s): cpu = 00:08:54 ; elapsed = 00:03:41 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3778 ; free virtual = 11891

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 27048886c

Time (s): cpu = 00:10:02 ; elapsed = 00:04:04 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3752 ; free virtual = 11864

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2a44a95c7

Time (s): cpu = 00:10:06 ; elapsed = 00:04:07 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3751 ; free virtual = 11863

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 2655393f0

Time (s): cpu = 00:10:06 ; elapsed = 00:04:07 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3751 ; free virtual = 11863

Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 2655393f0

Time (s): cpu = 00:10:07 ; elapsed = 00:04:08 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3751 ; free virtual = 11863

Phase 3.6 Fast Optimization
Phase 3.6 Fast Optimization | Checksum: 22b3667c8

Time (s): cpu = 00:10:11 ; elapsed = 00:04:12 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3749 ; free virtual = 11861

Phase 3.7 Small Shape Detail Placement
Phase 3.7 Small Shape Detail Placement | Checksum: 1c5f90cce

Time (s): cpu = 00:10:57 ; elapsed = 00:04:55 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3556 ; free virtual = 11669

Phase 3.8 Re-assign LUT pins
Phase 3.8 Re-assign LUT pins | Checksum: 1a0fd3ba3

Time (s): cpu = 00:11:02 ; elapsed = 00:05:00 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3567 ; free virtual = 11680

Phase 3.9 Pipeline Register Optimization
Phase 3.9 Pipeline Register Optimization | Checksum: 28ca59471

Time (s): cpu = 00:11:04 ; elapsed = 00:05:01 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3566 ; free virtual = 11679
Phase 3 Detail Placement | Checksum: 28ca59471

Time (s): cpu = 00:11:05 ; elapsed = 00:05:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3567 ; free virtual = 11680

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 28ea1668c

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-33] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[2].output_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-33] Processed net nf_datapath_0/input_arbiter_v1_0/inst/in_arb_queues[3].in_arb_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-33] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-33] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-33] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-33] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-31] BUFG insertion identified 6 candidate nets, 0 success, 6 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 28ea1668c

Time (s): cpu = 00:12:20 ; elapsed = 00:05:24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3698 ; free virtual = 11810
INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.410. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1b967b8a7

Time (s): cpu = 00:15:40 ; elapsed = 00:08:50 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3698 ; free virtual = 11814
Phase 4.1 Post Commit Optimization | Checksum: 1b967b8a7

Time (s): cpu = 00:15:41 ; elapsed = 00:08:51 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3698 ; free virtual = 11814

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1b967b8a7

Time (s): cpu = 00:15:43 ; elapsed = 00:08:52 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3714 ; free virtual = 11831

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1b967b8a7

Time (s): cpu = 00:15:44 ; elapsed = 00:08:53 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3719 ; free virtual = 11836

Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 15dd1be9b

Time (s): cpu = 00:15:45 ; elapsed = 00:08:54 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3720 ; free virtual = 11836
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15dd1be9b

Time (s): cpu = 00:15:46 ; elapsed = 00:08:55 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3720 ; free virtual = 11836
Ending Placer Task | Checksum: 6ed46efd

Time (s): cpu = 00:15:46 ; elapsed = 00:08:56 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3988 ; free virtual = 12105
INFO: [Common 17-83] Releasing license: Implementation
245 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:16:01 ; elapsed = 00:09:09 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3989 ; free virtual = 12105
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:20 ; elapsed = 00:00:08 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3632 ; free virtual = 12033
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:06 ; elapsed = 00:00:51 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3884 ; free virtual = 12071
INFO: [runtcl-4] Executing : report_io -file top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.34 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3843 ; free virtual = 12031
INFO: [runtcl-4] Executing : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3881 ; free virtual = 12069
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:01 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3881 ; free virtual = 12071
Command: phys_opt_design -directive ExploreWithHoldFix
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: ExploreWithHoldFix
Netlist sorting complete. Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.27 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3809 ; free virtual = 11999

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.149 | TNS=-460.660 |
Phase 1 Physical Synthesis Initialization | Checksum: 10dd5ee7d

Time (s): cpu = 00:01:23 ; elapsed = 00:00:23 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3720 ; free virtual = 11910
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.149 | TNS=-460.660 |

Phase 2 Fanout Optimization
INFO: [Physopt 32-64] No nets found for fanout-optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 2 Fanout Optimization | Checksum: 10dd5ee7d

Time (s): cpu = 00:01:28 ; elapsed = 00:00:26 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3708 ; free virtual = 11898

Phase 3 Placement Based Optimization
INFO: [Physopt 32-660] Identified 103 candidate nets for placement-based optimization.
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0].  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0].  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_446
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_497_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_497
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[3].  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_445
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__2_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_50_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_50
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_42_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_42
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_516_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_516
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_484_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_484
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15
INFO: [Physopt 32-661] Optimized 61 nets.  Re-placed 61 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 61 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 61 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.914 | TNS=-412.661 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3680 ; free virtual = 11870
Phase 3 Placement Based Optimization | Checksum: c7405456

Time (s): cpu = 00:01:43 ; elapsed = 00:00:32 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3680 ; free virtual = 11870

Phase 4 MultiInst Placement Optimization
INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__2_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__2/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_501_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_501/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_529_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_529/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0/O
INFO: [Physopt 32-661] Optimized 36 nets.  Re-placed 75 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 36 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 75 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.886 | TNS=-401.071 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3679 ; free virtual = 11870
Phase 4 MultiInst Placement Optimization | Checksum: c7b24d98

Time (s): cpu = 00:02:24 ; elapsed = 00:00:47 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3679 ; free virtual = 11870

Phase 5 Rewire
INFO: [Physopt 32-246] Starting Signal Push optimization...
INFO: [Physopt 32-77] Pass 1. Identified 5 candidate nets for rewire optimization.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3677 ; free virtual = 11868
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3677 ; free virtual = 11868
Phase 5 Rewire | Checksum: 14cc29ac3

Time (s): cpu = 00:02:27 ; elapsed = 00:00:50 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3678 ; free virtual = 11868

Phase 6 Critical Cell Optimization
INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]. Replicated 6 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]. Replicated 5 times.
INFO: [Physopt 32-601] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0. Net driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511 was replaced.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]. Replicated 10 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_51_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0]. Replicated 4 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0. Replicated 1 times.
INFO: [Physopt 32-232] Optimized 23 nets. Created 52 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 23 nets or cells. Created 52 new cells, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.883 | TNS=-394.421 |
Netlist sorting complete. Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.30 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3675 ; free virtual = 11865
Phase 6 Critical Cell Optimization | Checksum: 164a8e8c9

Time (s): cpu = 00:03:38 ; elapsed = 00:01:30 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3675 ; free virtual = 11865

Phase 7 Fanout Optimization
INFO: [Physopt 32-76] Pass 1. Identified 4 candidate nets for fanout optimization.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/D[0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/p_11_in. Replicated 4 times.
INFO: [Physopt 32-572] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_0_i_18__0_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/D[2]. Replicated 8 times.
INFO: [Physopt 32-232] Optimized 2 nets. Created 12 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 12 new cells, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.883 | TNS=-394.492 |
Netlist sorting complete. Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.31 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3676 ; free virtual = 11866
Phase 7 Fanout Optimization | Checksum: 1e00242e0

Time (s): cpu = 00:03:46 ; elapsed = 00:01:34 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3676 ; free virtual = 11867

Phase 8 Placement Based Optimization
INFO: [Physopt 32-660] Identified 162 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica
INFO: [Common 17-14] Message 'Physopt 32-663' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_445
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_5.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_446
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_25__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_25__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN_6.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica_6
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48
INFO: [Physopt 32-661] Optimized 50 nets.  Re-placed 50 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 50 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 50 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.883 | TNS=-389.342 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3674 ; free virtual = 11865
Phase 8 Placement Based Optimization | Checksum: 227bc255d

Time (s): cpu = 00:04:08 ; elapsed = 00:01:42 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3674 ; free virtual = 11865

Phase 9 MultiInst Placement Optimization
INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19/O
INFO: [Physopt 32-661] Optimized 16 nets.  Re-placed 36 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 16 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 36 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.883 | TNS=-388.214 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11864
Phase 9 MultiInst Placement Optimization | Checksum: 1695dda7b

Time (s): cpu = 00:05:39 ; elapsed = 00:02:11 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11864

Phase 10 Rewire
INFO: [Physopt 32-246] Starting Signal Push optimization...
INFO: [Physopt 32-77] Pass 1. Identified 3 candidate nets for rewire optimization.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11864
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11864
Phase 10 Rewire | Checksum: 191f4059e

Time (s): cpu = 00:05:40 ; elapsed = 00:02:13 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11865

Phase 11 Critical Cell Optimization
INFO: [Physopt 32-46] Identified 19 candidate nets for critical-cell optimization.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0. Replicated 3 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1]. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-232] Optimized 9 nets. Created 14 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 9 nets or cells. Created 14 new cells, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.852 | TNS=-384.781 |
Netlist sorting complete. Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.28 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11864
Phase 11 Critical Cell Optimization | Checksum: b01ffebe

Time (s): cpu = 00:06:23 ; elapsed = 00:02:37 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3672 ; free virtual = 11864

Phase 12 Slr Crossing Optimization
Phase 12 Slr Crossing Optimization | Checksum: b01ffebe

Time (s): cpu = 00:06:23 ; elapsed = 00:02:37 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3672 ; free virtual = 11864

Phase 13 Fanout Optimization
INFO: [Physopt 32-76] Pass 1. Identified 6 candidate nets for fanout optimization.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/D[0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/p_11_in_repN_2 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/CamReg_reg[3][0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/CamReg was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/CamReg_reg[1][0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/CamReg_reg[1][0]_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3672 ; free virtual = 11863
Phase 13 Fanout Optimization | Checksum: edb9840f

Time (s): cpu = 00:06:36 ; elapsed = 00:02:44 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3672 ; free virtual = 11863

Phase 14 Placement Based Optimization
INFO: [Physopt 32-660] Identified 166 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_4.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_4.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_5.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_3.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_3
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_446
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_445
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN_6.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica_6
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_499_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_499
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_525_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_525
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1
INFO: [Physopt 32-661] Optimized 25 nets.  Re-placed 25 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 25 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 25 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.852 | TNS=-383.554 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11865
Phase 14 Placement Based Optimization | Checksum: 162888118

Time (s): cpu = 00:06:59 ; elapsed = 00:02:52 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11865

Phase 15 MultiInst Placement Optimization
INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica_1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498/O
INFO: [Physopt 32-661] Optimized 15 nets.  Re-placed 37 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 15 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 37 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.852 | TNS=-380.858 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3674 ; free virtual = 11866
Phase 15 MultiInst Placement Optimization | Checksum: e821a476

Time (s): cpu = 00:08:58 ; elapsed = 00:03:30 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3674 ; free virtual = 11866

Phase 16 Rewire
INFO: [Physopt 32-246] Starting Signal Push optimization...
INFO: [Physopt 32-77] Pass 1. Identified 4 candidate nets for rewire optimization.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862
Phase 16 Rewire | Checksum: eab9b61a

Time (s): cpu = 00:09:00 ; elapsed = 00:03:32 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862

Phase 17 Critical Cell Optimization
INFO: [Physopt 32-46] Identified 24 candidate nets for critical-cell optimization.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2]. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0. Replicated 4 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0_repN was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-232] Optimized 12 nets. Created 18 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 18 new cells, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.842 | TNS=-380.825 |
Netlist sorting complete. Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.28 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3668 ; free virtual = 11860
Phase 17 Critical Cell Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:55 ; elapsed = 00:04:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3668 ; free virtual = 11861

Phase 18 DSP Register Optimization
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 18 DSP Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:55 ; elapsed = 00:04:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3669 ; free virtual = 11861

Phase 19 BRAM Register Optimization
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 19 BRAM Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:56 ; elapsed = 00:04:03 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3669 ; free virtual = 11861

Phase 20 URAM Register Optimization
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 20 URAM Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:56 ; elapsed = 00:04:03 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3669 ; free virtual = 11861

Phase 21 Shift Register Optimization
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 21 Shift Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:57 ; elapsed = 00:04:04 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3671 ; free virtual = 11863

Phase 22 DSP Register Optimization
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 22 DSP Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:57 ; elapsed = 00:04:04 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3671 ; free virtual = 11863

Phase 23 BRAM Register Optimization
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 23 BRAM Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:58 ; elapsed = 00:04:05 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3671 ; free virtual = 11863

Phase 24 URAM Register Optimization
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 24 URAM Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:58 ; elapsed = 00:04:05 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3671 ; free virtual = 11863

Phase 25 Shift Register Optimization
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 25 Shift Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:58 ; elapsed = 00:04:06 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862

Phase 26 Critical Pin Optimization
INFO: [Physopt 32-606] Identified 14 candidate nets for critical-pin optimization.
INFO: [Physopt 32-608] Optimized 8 nets.  Swapped 137 pins.
INFO: [Physopt 32-775] End 1 Pass. Optimized 8 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 137 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.709 | TNS=-375.928 |
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862
Phase 26 Critical Pin Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:10:00 ; elapsed = 00:04:07 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862

Phase 27 Very High Fanout Optimization
INFO: [Physopt 32-76] Pass 1. Identified 100 candidate nets for fanout optimization.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/out[3] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/RX_TUPLE_VALID. Replicated 3 times.
INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/rRst was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/rRst was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_2/valid_2. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_3/TX_TUPLE_VALID. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_3/valid_1. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_1/MUX_TUPLE_control_reg[9]_0[0]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_5/valid_1. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_6/TX_TUPLE_VALID. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_6/valid_1. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_8/MUX_TUPLE_realmain_lookup_table_0_req_reg[0]_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_8/valid_2. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/wr_en. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_12/valid_1. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_0/E[0]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/TUPLE_digest_data_0_reg[0]. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_RESET_clk_line/clk_line_rst_high. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_1/valid_6. Replicated 1 times.
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/user_reset. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/valid_6. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_0_reset. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_0/tupleForward_inst/Enable_d_1. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[2].output_fifo/fifo/SR[0]. Replicated 8 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_3/MUX_TUPLE_TopPipe_fl[112]_i_2__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/input_arbiter_v1_0/inst/in_arb_queues[3].in_arb_fifo/fifo/SR[0]. Replicated 8 times.
INFO: [Physopt 32-81] Processed net nf_10g_interface_3/inst/nf_10g_interface_cpu_regs_inst/pcspmastatusvector13_reg_reg[0][0]. Replicated 1 times.
INFO: [Physopt 32-232] Optimized 23 nets. Created 43 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 23 nets or cells. Created 43 new cells, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.709 | TNS=-375.933 |
Netlist sorting complete. Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.62 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11849
Phase 27 Very High Fanout Optimization | Checksum: 134a2d502

Time (s): cpu = 00:11:48 ; elapsed = 00:04:56 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11849

Phase 28 Placement Based Optimization
INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_4.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_5.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_25_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_25
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_4.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_512_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_512
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_446
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_445
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_499_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_499
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_474_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_474
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_497_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_497
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_3.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_3
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_525_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_525
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_33_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_33
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_508_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_508
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_468_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_468
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_26_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_26
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN_7.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica_7
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_40_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_40
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/D[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_459_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_459
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Hash_Update_inst/Hash3_i[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Hash_Update_inst/xpm_memory_tdpram_inst_i_562
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/Addr[0]_i_2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/Addr[0]_i_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/Addr[0]_i_4_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/Addr[0]_i_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/UpdateValueOut_i[65].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/RamRdData_r_reg[193]
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/p_11_in_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/Hit_r1_i_3_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1_reg[434][38].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1[166]_i_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_194_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_194
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/RamRdData_ram[23].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_215
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1[166].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1_reg[166]
INFO: [Physopt 32-662] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_0_i_18__0_n_0.  Did not re-place instance nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_0_i_18__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_2_0.  Did not re-place instance nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_2_i_19
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_211_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_211
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/RamRdData_ram[6].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_229
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_195_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_195
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/RamRdData_r_reg[30].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/RamRdData_r[30]_i_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_174_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_174
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_153_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_153
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/Entry[157]_i_1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/Entry[157]_i_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/CamReg_reg[3][434][157].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/Entry_reg[157]
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_129_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_129
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1_reg[434][62].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1[190]_i_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1[190].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1_reg[190]
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1_reg[434][5].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1[133]_i_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1[133].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1_reg[133]
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1_reg[434][11].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1[139]_i_1
INFO: [Physopt 32-661] Optimized 54 nets.  Re-placed 54 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 54 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 54 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.709 | TNS=-329.151 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3656 ; free virtual = 11849
Phase 28 Placement Based Optimization | Checksum: b1b8185e

Time (s): cpu = 00:12:25 ; elapsed = 00:05:08 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3656 ; free virtual = 11849

Phase 29 MultiInst Placement Optimization
INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica_1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica_1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica_1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13/O
INFO: [Physopt 32-661] Optimized 12 nets.  Re-placed 30 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 30 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.709 | TNS=-334.110 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11850
Phase 29 MultiInst Placement Optimization | Checksum: 110fdc99e

Time (s): cpu = 00:14:11 ; elapsed = 00:05:43 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11850

Phase 30 Critical Path Optimization
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.709 | TNS=-334.110 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[284]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.671 | TNS=-334.266 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[284]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.661 | TNS=-334.245 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[212]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.656 | TNS=-334.212 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/doutb[176]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.653 | TNS=-333.980 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.650 | TNS=-333.409 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5_replica
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]_repN. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.643 | TNS=-332.975 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_3
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.619 | TNS=-332.984 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.615 | TNS=-331.751 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_5.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_5
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_5. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.610 | TNS=-331.613 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[212]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__2_replica
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0]_repN. Replicated 2 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.593 | TNS=-331.275 |
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.592 | TNS=-331.268 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2_replica
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.588 | TNS=-331.142 |
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.586 | TNS=-331.140 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.586 | TNS=-330.972 |
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.585 | TNS=-330.384 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0/O
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.584 | TNS=-329.936 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22/O
INFO: [Physopt 32-601] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0. Net driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22 was replaced.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.567 | TNS=-329.916 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/doutb[176]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_1
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_1. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.564 | TNS=-329.780 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1_replica
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.564 | TNS=-329.710 |
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.562 | TNS=-329.696 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_4.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_4
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_4. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.555 | TNS=-329.563 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.550 | TNS=-329.341 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.550 | TNS=-328.463 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0/O
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.547 | TNS=-328.738 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2_replica_1
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.546 | TNS=-328.651 |
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.546 | TNS=-328.631 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46/O
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-328.571 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46/O
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[60]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-328.143 |
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/xgetxpkt_reg[25]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[2]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-326.696 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[6]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-326.500 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[8]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-326.316 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[15]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-326.132 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[16]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.948 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[18]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.764 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[23]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.580 |
INFO: [Physopt 32-702] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.533 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/rRdPtr_reg_n_0_[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.438 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/rRdPtr_reg_n_0_[1]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.343 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.191 |
INFO: [Physopt 32-662] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48].  Did not re-place instance nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg_reg[48]
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.151 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[50]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.141 |
INFO: [Physopt 32-662] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[50].  Did not re-place instance nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg_reg[50]
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[50]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.174 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.121 |
INFO: [Physopt 32-702] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[34]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.084 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[62]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.070 |
INFO: [Physopt 32-662] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48].  Did not re-place instance nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg_reg[48]
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.983 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[27]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.949 |
INFO: [Physopt 32-702] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/bd_a1aa_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/bd_a1aa_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[57]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.879 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[42]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.821 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[29]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.784 |
INFO: [Physopt 32-702] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[10]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.774 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[284]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5_replica
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.536 | TNS=-324.723 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[248]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_5.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_5
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_5. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.532 | TNS=-324.604 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2_replica_1
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2]_repN_1. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.531 | TNS=-324.515 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/doutb[428]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-324.101 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica/O
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[57]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[50]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.949 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/reg_inst/txc_output_register/pipeline_inst/gen_stages[1].rData_reg[1][37][60]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.751 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.681 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][49]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.611 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][50]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.541 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][51]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.471 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][52]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.401 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][53]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.331 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/rState[2]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.210 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/rState[4]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.089 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][64]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.023 |
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.023 |
Phase 30 Critical Path Optimization | Checksum: 2008e74ed

Time (s): cpu = 00:15:16 ; elapsed = 00:06:10 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3659 ; free virtual = 11852

Phase 31 Critical Path Optimization
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.023 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica/O
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.528 | TNS=-323.015 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.528 | TNS=-322.998 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2_replica_1
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.527 | TNS=-323.029 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[320]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.527 | TNS=-322.979 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1/O
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0. Replicated 2 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.526 | TNS=-322.970 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[212]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_3
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.524 | TNS=-322.893 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_replica/O
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0_repN. Rewiring did not optimize the net.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.886 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[38]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][65]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.820 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][60]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.766 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][61]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.712 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][62]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.658 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][63]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.604 |
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/xgetxpkt_reg[25]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[3]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.182 |
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/buffer/fifo/mem/rDout[68]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/WEBWE[0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/WEBWE[0].  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/rRAM_reg_0_i_1__2
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/WEBWE[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/wBufWen. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-319.668 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][18]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-319.618 |
INFO: [Common 17-14] Message 'Physopt 32-619' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][19]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][20]. Optimization improves timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[38]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][21]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][22]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][23]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][66]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][67]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][68]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][69]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][70]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][71]. Optimization improves timing on the net.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][30].  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48]
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][30]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/E[0].  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/rRdPtrPlus1[2]_i_1__7
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/E[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_alignment_inst/gen_data_input_regs[3].data_register_/pipeline_inst/E[0]. Optimization improves timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/xgetxpkt_reg[25]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[6]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[5]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[0]. Optimization improves timing on the net.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[2].  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[2]
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[2].  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[2]/Q
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/xgetxpkt_reg[3]_i_2_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast.  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast_INST_0
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast. Optimization improves timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/D[30]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]. Optimization improves timing on the net.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast.  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast_INST_0
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast.  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast_INST_0/O
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/CO[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words_sent_max_carry__1_i_1_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words_sent_max0[27]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words_sent_max0_carry_i_3_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/xgetxpkt_reg_reg[30][25]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1. Optimizations did not improve timing on the net.
Phase 31 Critical Path Optimization | Checksum: 1a4d27137

Time (s): cpu = 00:16:04 ; elapsed = 00:06:30 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11851

Phase 32 BRAM Enable Optimization
Phase 32 BRAM Enable Optimization | Checksum: 1a4d27137

Time (s): cpu = 00:16:05 ; elapsed = 00:06:31 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11851

Phase 33 Hold Fix Optimization
INFO: [Physopt 32-668] Estimated Timing Summary | WNS=-0.523 | TNS=-299.398 | WHS=-0.382 | THS=-502.239 |
INFO: [Physopt 32-45] Identified 83 candidate nets for hold slack optimization.
INFO: [Physopt 32-234] Optimized 83 nets. Inserted 0 new ZHOLD_DELAYs. Calibrated 0 existing ZHOLD_DELAYs. Inserted 83 buffers.

INFO: [Physopt 32-668] Estimated Timing Summary | WNS=-0.523 | TNS=-299.398 | WHS=-0.249 | THS=-477.438 |
Phase 33 Hold Fix Optimization | Checksum: 180337eab

Time (s): cpu = 00:16:46 ; elapsed = 00:06:41 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3601 ; free virtual = 11795
Netlist sorting complete. Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.43 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3610 ; free virtual = 11804
INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=-0.523 | TNS=-299.398 | WHS=-0.249 | THS=-477.438 |

Summary of Physical Synthesis Optimizations
============================================


--------------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization          |  WNS Gain (ns)  |  TNS Gain (ns)  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Fanout                |          0.000  |         -0.070  |           12  |              0  |                     2  |           0  |           3  |  00:00:11  |
|  Placement Based       |          0.235  |        101.158  |            0  |              0  |                   190  |           0  |           4  |  00:00:32  |
|  MultiInst Placement   |          0.028  |         10.455  |            0  |              0  |                    79  |           0  |           4  |  00:01:54  |
|  Rewire                |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           3  |  00:00:04  |
|  Critical Cell         |          0.044  |         10.116  |           84  |              0  |                    44  |           0  |           3  |  00:01:32  |
|  Slr Crossing          |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register          |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  BRAM Register         |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  URAM Register         |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  Shift Register        |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  Critical Pin          |          0.133  |          4.897  |            0  |              0  |                     8  |           0  |           1  |  00:00:00  |
|  Very High Fanout      |          0.000  |         -0.005  |           43  |              0  |                    23  |           4  |           1  |  00:00:48  |
|  BRAM Enable           |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           1  |  00:00:01  |
|  Critical Path         |          0.186  |         34.712  |           17  |              0  |                    98  |           0  |           2  |  00:00:47  |
|  Total                 |          0.626  |        161.262  |          156  |              0  |                   444  |           4  |          31  |  00:05:49  |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------


Summary of Hold Fix Optimizations
=================================


--------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization               |  WHS Gain (ns)  |  THS Gain (ns)  |  Added LUTs  |  Added FFs  |  Optimized Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT1 and ZHOLD Insertion   |          0.133  |         24.801  |          83  |          0  |              83  |           0  |           1  |  00:00:04  |
|  Total                      |          0.133  |         24.801  |          83  |          0  |              83  |           0  |           1  |  00:00:04  |
--------------------------------------------------------------------------------------------------------------------------------------------------------------


Ending Physical Synthesis Task | Checksum: 18cb2de83

Time (s): cpu = 00:16:47 ; elapsed = 00:06:41 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3610 ; free virtual = 11804
INFO: [Common 17-83] Releasing license: Implementation
1631 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
phys_opt_design: Time (s): cpu = 00:17:58 ; elapsed = 00:06:57 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3777 ; free virtual = 11971
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:20 ; elapsed = 00:00:08 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3469 ; free virtual = 11943
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_physopt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:07 ; elapsed = 00:00:52 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3732 ; free virtual = 12000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC PLCK-18] Clock Placer Checks: Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. 
 This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.

	control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23
	control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Checksum: PlaceDB: 53bf3cfd ConstDB: 0 ShapeSum: 66ec5e1c RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 138daf8ae

Time (s): cpu = 00:01:29 ; elapsed = 00:00:48 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3329 ; free virtual = 11598
Post Restoration Checksum: NetGraph: b3084330 NumContArr: 85d2b57e Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 138daf8ae

Time (s): cpu = 00:01:34 ; elapsed = 00:00:53 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3332 ; free virtual = 11600

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 138daf8ae

Time (s): cpu = 00:01:36 ; elapsed = 00:00:55 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3261 ; free virtual = 11530

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 138daf8ae

Time (s): cpu = 00:01:36 ; elapsed = 00:00:55 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3261 ; free virtual = 11530
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1742210f0

Time (s): cpu = 00:03:11 ; elapsed = 00:01:26 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3181 ; free virtual = 11450
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.461 | TNS=-67.976| WHS=-0.431 | THS=-13540.465|


Phase 2.5 Update Timing for Bus Skew

Phase 2.5.1 Update Timing
Phase 2.5.1 Update Timing | Checksum: 17171acae

Time (s): cpu = 00:04:17 ; elapsed = 00:01:42 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3148 ; free virtual = 11416
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.461 | TNS=-53.594| WHS=N/A    | THS=N/A    |

Phase 2.5 Update Timing for Bus Skew | Checksum: 20f6bc080

Time (s): cpu = 00:04:18 ; elapsed = 00:01:42 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3142 ; free virtual = 11410
Phase 2 Router Initialization | Checksum: 19d293d02

Time (s): cpu = 00:04:18 ; elapsed = 00:01:43 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3142 ; free virtual = 11410

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 103668a54

Time (s): cpu = 00:06:46 ; elapsed = 00:02:21 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3093 ; free virtual = 11361

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 15369
 Number of Nodes with overlaps = 2285
 Number of Nodes with overlaps = 615
 Number of Nodes with overlaps = 199
 Number of Nodes with overlaps = 69
 Number of Nodes with overlaps = 18
 Number of Nodes with overlaps = 8
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.729 | TNS=-373.846| WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: d9e64346

Time (s): cpu = 00:15:17 ; elapsed = 00:05:11 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3108 ; free virtual = 11377

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 1441
 Number of Nodes with overlaps = 382
 Number of Nodes with overlaps = 101
 Number of Nodes with overlaps = 40
 Number of Nodes with overlaps = 25
 Number of Nodes with overlaps = 16
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.701 | TNS=-374.385| WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 192c96670

Time (s): cpu = 00:18:49 ; elapsed = 00:07:13 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3106 ; free virtual = 11375

Phase 4.3 Global Iteration 2
 Number of Nodes with overlaps = 1485
Phase 4.3 Global Iteration 2 | Checksum: 17ec49698

Time (s): cpu = 00:19:56 ; elapsed = 00:07:40 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3105 ; free virtual = 11374
Phase 4 Rip-up And Reroute | Checksum: 17ec49698

Time (s): cpu = 00:19:56 ; elapsed = 00:07:40 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3105 ; free virtual = 11374

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 1a2194665

Time (s): cpu = 00:20:13 ; elapsed = 00:07:44 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3105 ; free virtual = 11374
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.701 | TNS=-245.139| WHS=N/A    | THS=N/A    |

 Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 10afc45fd

Time (s): cpu = 00:20:18 ; elapsed = 00:07:46 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3095 ; free virtual = 11364

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 10afc45fd

Time (s): cpu = 00:20:18 ; elapsed = 00:07:46 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3095 ; free virtual = 11364
Phase 5 Delay and Skew Optimization | Checksum: 10afc45fd

Time (s): cpu = 00:20:18 ; elapsed = 00:07:46 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3095 ; free virtual = 11363

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: c1785a78

Time (s): cpu = 00:20:36 ; elapsed = 00:07:51 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3101 ; free virtual = 11370
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.701 | TNS=-245.045| WHS=-0.032 | THS=-0.184 |

Phase 6.1 Hold Fix Iter | Checksum: 15b0d8537

Time (s): cpu = 00:20:38 ; elapsed = 00:07:52 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3092 ; free virtual = 11360
Phase 6 Post Hold Fix | Checksum: 1a4067059

Time (s): cpu = 00:20:39 ; elapsed = 00:07:53 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3091 ; free virtual = 11360

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 7.66597 %
  Global Horizontal Routing Utilization  = 8.57671 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 8x8 Area, Max Cong = 96.0304%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X24Y260 -> INT_R_X31Y267
   INT_L_X24Y252 -> INT_R_X31Y259
   INT_L_X32Y252 -> INT_R_X39Y259
South Dir 8x8 Area, Max Cong = 88.2883%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X24Y244 -> INT_R_X31Y251
   INT_L_X32Y244 -> INT_R_X39Y251
East Dir 4x4 Area, Max Cong = 87.6838%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X24Y252 -> INT_R_X27Y255
   INT_L_X28Y244 -> INT_R_X31Y247
   INT_L_X32Y244 -> INT_R_X35Y247
West Dir 4x4 Area, Max Cong = 88.511%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X32Y248 -> INT_R_X35Y251
   INT_L_X32Y244 -> INT_R_X35Y247

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 2
Effective congestion level: 4 Aspect Ratio: 1 Sparse Ratio: 1.375
Direction: South
----------------
Congested clusters found at Level 3
Effective congestion level: 4 Aspect Ratio: 0.5 Sparse Ratio: 0.5
Direction: East
----------------
Congested clusters found at Level 2
Effective congestion level: 3 Aspect Ratio: 0.666667 Sparse Ratio: 1
Direction: West
----------------
Congested clusters found at Level 2
Effective congestion level: 3 Aspect Ratio: 0.333333 Sparse Ratio: 0.75

Phase 7 Route finalize | Checksum: 20ac97f31

Time (s): cpu = 00:20:41 ; elapsed = 00:07:53 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3088 ; free virtual = 11357

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 20ac97f31

Time (s): cpu = 00:20:41 ; elapsed = 00:07:54 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3086 ; free virtual = 11355

Phase 9 Depositing Routes
INFO: [Route 35-467] Router swapped GT pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_gt_common_block/gthe2_common_0_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y9/GTNORTHREFCLK0
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y23/GTREFCLK1
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y5/GTREFCLK1
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y22/GTREFCLK1
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y21/GTREFCLK1
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y20/GTREFCLK1
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK0
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y4/GTSOUTHREFCLK0
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK0
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK0
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK0
Phase 9 Depositing Routes | Checksum: 1c3cfef64

Time (s): cpu = 00:20:50 ; elapsed = 00:08:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3102 ; free virtual = 11371

Phase 10 Post Router Timing

Phase 10.1 Update Timing
Phase 10.1 Update Timing | Checksum: 1174b4bcd

Time (s): cpu = 00:21:07 ; elapsed = 00:08:07 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3107 ; free virtual = 11376
INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.701 | TNS=-245.045| WHS=0.010  | THS=0.000  |

WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 1174b4bcd

Time (s): cpu = 00:21:08 ; elapsed = 00:08:07 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3107 ; free virtual = 11376
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:21:08 ; elapsed = 00:08:08 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3283 ; free virtual = 11551

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
1661 Infos, 162 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:21:29 ; elapsed = 00:08:23 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3283 ; free virtual = 11551
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 2857 ; free virtual = 11479
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_routed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:07 ; elapsed = 00:00:52 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3169 ; free virtual = 11528
INFO: [runtcl-4] Executing : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:46 ; elapsed = 00:00:15 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3062 ; free virtual = 11421
INFO: [runtcl-4] Executing : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 8 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:03:17 ; elapsed = 00:00:42 . Memory (MB): peak = 5634.605 ; gain = 71.020 ; free physical = 2123 ; free virtual = 10483
INFO: [runtcl-4] Executing : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
1673 Infos, 163 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:01:28 ; elapsed = 00:00:35 . Memory (MB): peak = 5920.883 ; gain = 286.277 ; free physical = 1946 ; free virtual = 10322
INFO: [runtcl-4] Executing : report_route_status -file top_route_status.rpt -pb top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:34 ; elapsed = 00:00:09 . Memory (MB): peak = 5975.855 ; gain = 54.973 ; free physical = 1872 ; free virtual = 10254
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_clock_utilization_routed.rpt
report_clock_utilization: Time (s): cpu = 00:00:54 ; elapsed = 00:00:54 . Memory (MB): peak = 5975.855 ; gain = 0.000 ; free physical = 1869 ; free virtual = 10252
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Command: phys_opt_design -directive AggressiveExplore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 99.4% nets are fully routed)
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AggressiveExplore
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Netlist sorting complete. Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.28 . Memory (MB): peak = 6007.871 ; gain = 0.000 ; free physical = 1865 ; free virtual = 10249

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.697 | TNS=-236.007 | WHS=0.010 | THS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 2c45ed33a

Time (s): cpu = 00:01:31 ; elapsed = 00:00:25 . Memory (MB): peak = 6007.871 ; gain = 0.000 ; free physical = 1721 ; free virtual = 10105
WARNING: [Physopt 32-745] Physical Optimization has determined that the magnitude of the negative slack is too large and it is highly unlikely that slack will be improved. Post-Route Physical Optimization is most effective when WNS is above -0.5ns

Phase 2 Critical Path Optimization
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.697 | TNS=-236.007 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-716] Net axi_clocking_i/clk_wiz_i/inst/clk_out1 has constraints that cannot be copied, and hence, it cannot be cloned. The constraint blocking the replication is set_data_check @ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc:76
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.573 | TNS=-235.774 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_5.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_5
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_5. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.542 | TNS=-235.722 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_1. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-710] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0. Critial path length was reduced through logic transformation on cell nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_comp.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.535 | TNS=-235.355 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN_1. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[49]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-235.326 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[49]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/xgetxpkt_reg[25]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[4]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[4].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[4]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-234.851 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[9]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[9].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[9]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-234.560 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[3]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[3].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[3]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-234.299 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[7]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[7].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[7]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-233.813 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[13]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[13].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[13]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-233.237 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[5]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[5].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[5]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-233.207 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[17]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[17].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[17]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-232.500 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[21]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[21].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[21]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-232.305 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[4]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[4].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[4]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-232.141 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[9]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[9].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[9]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-232.059 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[3]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[3].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[3]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.983 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[7]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[7].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[7]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.894 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[13]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[13].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[13]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.866 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[25]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[25].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[25]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.847 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN_1. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[49]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.847 | WHS=0.010 | THS=0.000 |
Phase 2 Critical Path Optimization | Checksum: 2c45ed33a

Time (s): cpu = 00:30:31 ; elapsed = 00:27:20 . Memory (MB): peak = 6833.941 ; gain = 826.070 ; free physical = 1706 ; free virtual = 10091

Phase 3 Hold Fix Optimization
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.847 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-45] Identified 3 candidate nets for hold slack optimization.
INFO: [Physopt 32-234] Optimized 3 nets. Inserted 0 new ZHOLD_DELAYs. Calibrated 0 existing ZHOLD_DELAYs. Inserted 3 buffers.

INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.847 | WHS=0.010 | THS=0.000 |
Phase 3 Hold Fix Optimization | Checksum: 2c45ed33a

Time (s): cpu = 00:30:54 ; elapsed = 00:27:40 . Memory (MB): peak = 6833.941 ; gain = 826.070 ; free physical = 1702 ; free virtual = 10088
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 6833.941 ; gain = 0.000 ; free physical = 1702 ; free virtual = 10088
INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=-0.534 | TNS=-231.847 | WHS=0.010 | THS=0.000 |

Summary of Physical Synthesis Optimizations
============================================


-------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization   |  WNS Gain (ns)  |  TNS Gain (ns)  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Critical Path  |          0.164  |          4.160  |            0  |              0  |                    18  |           0  |           1  |  00:26:54  |
-------------------------------------------------------------------------------------------------------------------------------------------------------------


Summary of Hold Fix Optimizations
=================================


--------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization               |  WHS Gain (ns)  |  THS Gain (ns)  |  Added LUTs  |  Added FFs  |  Optimized Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT1 and ZHOLD Insertion   |          0.000  |          0.000  |           3  |          0  |               3  |           0  |           1  |  00:00:19  |
|  Total                      |          0.000  |          0.000  |           3  |          0  |               3  |           0  |           1  |  00:00:19  |
--------------------------------------------------------------------------------------------------------------------------------------------------------------


Ending Physical Synthesis Task | Checksum: 2c45ed33a

Time (s): cpu = 00:30:55 ; elapsed = 00:27:40 . Memory (MB): peak = 6833.941 ; gain = 826.070 ; free physical = 1707 ; free virtual = 10092
INFO: [Common 17-83] Releasing license: Implementation
1767 Infos, 165 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
phys_opt_design: Time (s): cpu = 00:31:00 ; elapsed = 00:27:45 . Memory (MB): peak = 6833.941 ; gain = 858.086 ; free physical = 2127 ; free virtual = 10512
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:22 ; elapsed = 00:00:09 . Memory (MB): peak = 6865.957 ; gain = 0.000 ; free physical = 1713 ; free virtual = 10452
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_postroute_physopt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:08 ; elapsed = 00:00:52 . Memory (MB): peak = 6865.957 ; gain = 32.016 ; free physical = 2021 ; free virtual = 10496
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -warn_on_violation -file top_timing_summary_postroute_physopted.rpt -pb top_timing_summary_postroute_physopted.pb -rpx top_timing_summary_postroute_physopted.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:01:44 ; elapsed = 00:00:20 . Memory (MB): peak = 6865.957 ; gain = 0.000 ; free physical = 2065 ; free virtual = 10546
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_postroute_physopted.rpt -pb top_bus_skew_postroute_physopted.pb -rpx top_bus_skew_postroute_physopted.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
Command: write_bitstream -force top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.

Evaluation cores found in this design:
    IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features:
        IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
        IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
    IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
    IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features:
        IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
        IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
    IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.

Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1 is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica. Remove non-muxed BUFG if it is not desired
WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica_1. Remove non-muxed BUFG if it is not desired
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed).
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_25) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_26) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_27) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [Common 17-14] Message 'DRC REQP-181' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 53 Warnings, 126 Advisories
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 125573888 bits.
Writing bitstream ./top.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
1949 Infos, 219 Warnings, 2 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:04:04 ; elapsed = 00:03:23 . Memory (MB): peak = 6921.984 ; gain = 56.027 ; free physical = 2037 ; free virtual = 10534
INFO: [Common 17-206] Exiting Vivado at Thu Jul 25 01:18:44 2019...
[Thu Jul 25 01:18:50 2019] impl_1 finished
wait_on_run: Time (s): cpu = 00:15:14 ; elapsed = 01:27:26 . Memory (MB): peak = 2876.789 ; gain = 0.000 ; free physical = 6338 ; free virtual = 14838
# exit
INFO: [Common 17-206] Exiting Vivado at Thu Jul 25 01:18:50 2019...
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
make -C hw export_to_sdk
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
rm -f ../hw/create_ip/id_rom16x32.coe
cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
echo 16028002 >> rom_data.txt
echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt
grep: ../../../RELEASE_NOTES: No such file or directory
echo 00000204 >> rom_data.txt
echo 0000FFFF >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py 
16

mv -f id_rom16x32.coe ../hw/create_ip/
mv -f rom_data.txt ../hw/create_ip/
if test -d project; then\
	echo "export simple_sume_switch project to SDK"; \
	vivado -mode tcl -source tcl/export_hardware.tcl -tclargs simple_sume_switch;\
else \
	echo "Project simple_sume_switch does not exist.";\
	echo "Please run \"make project\" to create and build the project first";\
fi;\

export simple_sume_switch project to SDK

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source tcl/export_hardware.tcl
# set design [lindex $argv 0] 
# puts "\nOpening $design XPR project\n"

Opening simple_sume_switch XPR project

# open_project project/$design.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'bd_7ad4_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-28028-nsg-System/coregen/bd_7ad4_xpcs_0_1/elaborate/configure_gt.tcl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_a1aa_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-28028-nsg-System/coregen/bd_a1aa_xpcs_0_2/elaborate/configure_gt.tcl'. Please regenerate to continue.
open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1365.527 ; gain = 188.789 ; free physical = 7065 ; free virtual = 15565
# puts "\nOpening $design Implementation design\n"

Opening simple_sume_switch Implementation design

# open_run impl_1
INFO: [Netlist 29-17] Analyzing 4406 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3613.734 ; gain = 179.945 ; free physical = 4950 ; free virtual = 13451
Restored from archive | CPU: 8.870000 secs | Memory: 207.107361 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3613.734 ; gain = 179.945 ; free physical = 4950 ; free virtual = 13451
Generating merged BMM file for the design top 'top'...
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/data/mb_bootloop_le.elf 
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 754 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
  LUT6_2 => LUT6_2 (LUT5, LUT6): 79 instances
  RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 365 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances
  RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 211 instances
  RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 38 instances
  SRLC16E => SRL16E: 1 instances

open_run: Time (s): cpu = 00:01:23 ; elapsed = 00:02:24 . Memory (MB): peak = 4342.090 ; gain = 2976.562 ; free physical = 5012 ; free virtual = 13513
# puts "\nCopying top.sysdef\n"

Copying top.sysdef

# file copy -force ./project/$design.runs/impl_1/top.sysdef ../sw/embedded/$design.hdf
# exit
INFO: [Common 17-206] Exiting Vivado at Thu Jul 25 01:21:26 2019...
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
make -C sw/embedded/ project
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
mkdir ./SDK_Workspace
xsdk -batch -source ./tcl/simple_sume_switch_xsdk.tcl
Starting xsdk. This could take few seconds... Eclipse: Cannot open display: 
done
INFO: [Hsi 55-1698] elapsed time for repository loading 0 seconds
/opt/Xilinx/SDK/2018.2/gnu/microblaze/lin
BSP project 'bsp' created successfully.
WARNING: [Hsi 61-9] Current Software design may not be compatible with "hello_world" app. Tool is ignoring the MSS file specified in the app directory
Application project 'app' created successfully.
Building '/bsp'
Invoking Make Builder...bsp
01:21:33 **** Build of project bsp ****
make -k all 
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
Compiling standalone
microblaze_sleep.c:74:9: note: #pragma message: For the sleep routines, assembly instructions are used
 #pragma message ("For the sleep routines, assembly instructions are used")
         ^~~~~~~
mb-ar: creating ../../../lib/libxil.a
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
Compiling iic
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
Compiling uartlite
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
Compiling bram
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
Compiling cpu
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
Compiling intc
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
Finished building libraries
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'

01:21:35 Build Finished (took 1s.863ms)

Building '/app'
01:21:35 **** Build of configuration Debug for project app ****
make all 
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
Building file: ../src/helloworld.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c"
Finished building: ../src/helloworld.c
 
Building file: ../src/platform.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c"
Finished building: ../src/platform.c
 
Building target: app.elf
Invoking: MicroBlaze gcc linker
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf"  ./src/helloworld.o ./src/platform.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
Finished building target: app.elf
 
Invoking: MicroBlaze Print Size
mb-size app.elf  |tee "app.elf.size"
   text	   data	    bss	    dec	    hex	filename
   3112	    316	   3108	   6536	   1988	app.elf
Finished building: app.elf.size
 
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'

01:21:35 Build Finished (took 517ms)

Invoking scanner config builder on project 
Building '/hw_platform'
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
make -C sw/embedded/ compile
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
Eclipse:
GTK+ Version Check
Eclipse: Cannot open display: 
Building All Projects...
Building workspace
Building '/bsp'
Invoking Make Builder...bsp
01:21:38 **** Build of project bsp ****
make -k all 
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
Compiling standalone
microblaze_sleep.c:74:9: note: #pragma message: For the sleep routines, assembly instructions are used
 #pragma message ("For the sleep routines, assembly instructions are used")
         ^~~~~~~
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
Compiling iic
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
Compiling uartlite
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
Compiling bram
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
Compiling cpu
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
Compiling intc
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
Finished building libraries
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'

01:21:40 Build Finished (took 1s.866ms)

Building '/app'
01:21:40 **** Build of configuration Debug for project app ****
make all 
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
Building file: ../src/helloworld.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c"
../src/helloworld.c: In function 'runManualTest':
../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration]
     pmReadInfo();
     ^~~~~~~~~~
../src/helloworld.c: In function 'main':
../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration]
  Status = IicInit(&IicInstance);
           ^~~~~~~
../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration]
  Status = SetupInterruptSystem(&IicInstance);
           ^~~~~~~~~~~~~~~~~~~~
           XIntc_InterruptHandler
../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration]
  Status = IicInitPost(&IicInstance);
           ^~~~~~~~~~~
../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration]
  config_SI5324();
  ^~~~~~~~~~~~~
Finished building: ../src/helloworld.c
 
Building file: ../src/platform.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c"
Finished building: ../src/platform.c
 
Building target: app.elf
Invoking: MicroBlaze gcc linker
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf"  ./src/helloworld.o ./src/platform.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
./src/helloworld.o: In function `runManualTest':
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:103: undefined reference to `pmReadInfo'
./src/helloworld.o: In function `main':
makefile:36: recipe for target 'app.elf' failed
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:125: undefined reference to `IicInit'
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:143: undefined reference to `IicInitPost'
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:149: undefined reference to `config_SI5324'
collect2: error: ld returned 1 exit status
make[2]: *** [app.elf] Error 1

01:21:41 Build Finished (took 509ms)

01:21:41 **** Build of configuration Release for project app ****
make all 
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'
Building file: ../src/helloworld.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c"
../src/helloworld.c: In function 'runManualTest':
../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration]
     pmReadInfo();
     ^~~~~~~~~~
../src/helloworld.c: In function 'main':
../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration]
  Status = IicInit(&IicInstance);
           ^~~~~~~
../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration]
  Status = SetupInterruptSystem(&IicInstance);
           ^~~~~~~~~~~~~~~~~~~~
           XIntc_InterruptHandler
../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration]
  Status = IicInitPost(&IicInstance);
           ^~~~~~~~~~~
../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration]
  config_SI5324();
  ^~~~~~~~~~~~~
Finished building: ../src/helloworld.c
 
Building file: ../src/iic_config.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_config.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_config.d" -MT"src/iic_config.o" -o "src/iic_config.o" "../src/iic_config.c"
../src/iic_config.c: In function 'IicReadData3':
../src/iic_config.c:439:10: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types]
  addrPtr = &addr;
          ^
../src/iic_config.c:397:5: warning: unused variable 'IicOptions' [-Wunused-variable]
  u8 IicOptions;
     ^~~~~~~~~~
Finished building: ../src/iic_config.c
 
Building file: ../src/iic_pm.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_pm.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_pm.d" -MT"src/iic_pm.o" -o "src/iic_pm.o" "../src/iic_pm.c"
Finished building: ../src/iic_pm.c
 
Building file: ../src/iic_si5324.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_si5324.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_si5324.d" -MT"src/iic_si5324.o" -o "src/iic_si5324.o" "../src/iic_si5324.c"
Finished building: ../src/iic_si5324.c
 
Building file: ../src/platform.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c"
Finished building: ../src/platform.c
 
Building target: app.elf
Invoking: MicroBlaze gcc linker
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf"  ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
Finished building target: app.elf
 
Invoking: MicroBlaze Print Size
mb-size app.elf  |tee "app.elf.size"
   text	   data	    bss	    dec	    hex	filename
  18364	    468	   3376	  22208	   56c0	app.elf
Finished building: app.elf.size
 
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'

01:21:41 Build Finished (took 608ms)

Invoking scanner config builder on project 
Building '/hw_platform'
Eclipse:
GTK+ Version Check
Eclipse: Cannot open display: 
Building All Projects...
Building workspace
Building '/bsp'
Invoking Make Builder...bsp
01:21:45 **** Build of project bsp ****
make -k all 
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s include  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
Compiling standalone
microblaze_sleep.c:74:9: note: #pragma message: For the sleep routines, assembly instructions are used
 #pragma message ("For the sleep routines, assembly instructions are used")
         ^~~~~~~
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
Compiling iic
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
Compiling uartlite
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
Compiling bram
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
Compiling cpu
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s libs  "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
Compiling intc
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
Finished building libraries
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'

01:21:47 Build Finished (took 1s.920ms)

Building '/app'
01:21:48 **** Clean-only build of configuration Debug for project app ****
make clean 
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
rm -rf  ./src/helloworld.o ./src/platform.o  ./src/helloworld.d ./src/platform.d  app.elf.size  app.elf
 
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'

01:21:48 Build Finished (took 408ms)

01:21:48 **** Build of configuration Debug for project app ****
make all 
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
Building file: ../src/helloworld.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c"
../src/helloworld.c: In function 'runManualTest':
../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration]
     pmReadInfo();
     ^~~~~~~~~~
../src/helloworld.c: In function 'main':
../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration]
  Status = IicInit(&IicInstance);
           ^~~~~~~
../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration]
  Status = SetupInterruptSystem(&IicInstance);
           ^~~~~~~~~~~~~~~~~~~~
           XIntc_InterruptHandler
../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration]
  Status = IicInitPost(&IicInstance);
           ^~~~~~~~~~~
../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration]
  config_SI5324();
  ^~~~~~~~~~~~~
Finished building: ../src/helloworld.c
 
Building file: ../src/iic_config.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/iic_config.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_config.d" -MT"src/iic_config.o" -o "src/iic_config.o" "../src/iic_config.c"
../src/iic_config.c: In function 'IicReadData3':
../src/iic_config.c:439:10: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types]
  addrPtr = &addr;
          ^
../src/iic_config.c:397:5: warning: unused variable 'IicOptions' [-Wunused-variable]
  u8 IicOptions;
     ^~~~~~~~~~
Finished building: ../src/iic_config.c
 
Building file: ../src/iic_pm.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/iic_pm.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_pm.d" -MT"src/iic_pm.o" -o "src/iic_pm.o" "../src/iic_pm.c"
Finished building: ../src/iic_pm.c
 
Building file: ../src/iic_si5324.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/iic_si5324.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_si5324.d" -MT"src/iic_si5324.o" -o "src/iic_si5324.o" "../src/iic_si5324.c"
Finished building: ../src/iic_si5324.c
 
Building file: ../src/platform.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c"
Finished building: ../src/platform.c
 
Building target: app.elf
Invoking: MicroBlaze gcc linker
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf"  ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
Finished building target: app.elf
 
Invoking: MicroBlaze Print Size
mb-size app.elf  |tee "app.elf.size"
   text	   data	    bss	    dec	    hex	filename
  20340	    468	   3376	  24184	   5e78	app.elf
Finished building: app.elf.size
 
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'

01:21:49 Build Finished (took 609ms)

01:21:49 **** Clean-only build of configuration Release for project app ****
make clean 
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'
rm -rf  ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o  ./src/helloworld.d ./src/iic_config.d ./src/iic_pm.d ./src/iic_si5324.d ./src/platform.d  app.elf.size  app.elf
 
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'

01:21:49 Build Finished (took 407ms)

01:21:49 **** Build of configuration Release for project app ****
make all 
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'
Building file: ../src/helloworld.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c"
../src/helloworld.c: In function 'runManualTest':
../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration]
     pmReadInfo();
     ^~~~~~~~~~
../src/helloworld.c: In function 'main':
../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration]
  Status = IicInit(&IicInstance);
           ^~~~~~~
../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration]
  Status = SetupInterruptSystem(&IicInstance);
           ^~~~~~~~~~~~~~~~~~~~
           XIntc_InterruptHandler
../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration]
  Status = IicInitPost(&IicInstance);
           ^~~~~~~~~~~
../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration]
  config_SI5324();
  ^~~~~~~~~~~~~
Finished building: ../src/helloworld.c
 
Building file: ../src/iic_config.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_config.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_config.d" -MT"src/iic_config.o" -o "src/iic_config.o" "../src/iic_config.c"
../src/iic_config.c: In function 'IicReadData3':
../src/iic_config.c:439:10: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types]
  addrPtr = &addr;
          ^
../src/iic_config.c:397:5: warning: unused variable 'IicOptions' [-Wunused-variable]
  u8 IicOptions;
     ^~~~~~~~~~
Finished building: ../src/iic_config.c
 
Building file: ../src/iic_pm.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_pm.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_pm.d" -MT"src/iic_pm.o" -o "src/iic_pm.o" "../src/iic_pm.c"
Finished building: ../src/iic_pm.c
 
Building file: ../src/iic_si5324.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_si5324.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_si5324.d" -MT"src/iic_si5324.o" -o "src/iic_si5324.o" "../src/iic_si5324.c"
Finished building: ../src/iic_si5324.c
 
Building file: ../src/platform.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c"
Finished building: ../src/platform.c
 
Building target: app.elf
Invoking: MicroBlaze gcc linker
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf"  ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
Finished building target: app.elf
 
Invoking: MicroBlaze Print Size
mb-size app.elf  |tee "app.elf.size"
   text	   data	    bss	    dec	    hex	filename
  18364	    468	   3376	  22208	   56c0	app.elf
Finished building: app.elf.size
 
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'

01:21:50 Build Finished (took 607ms)

Invoking scanner config builder on project 
Building '/hw_platform'
Eclipse:
GTK+ Version Check
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
make -C hw load_elf
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
if test -d project; then\
	echo "export simple_sume_switch project to SDK"; \
	vivado -mode tcl -source tcl/load_elf.tcl -tclargs simple_sume_switch;\
else \
	echo "Project simple_sume_switch does not exist.";\
	echo "Please run \"make project\" to create and build the project first";\
fi;\

export simple_sume_switch project to SDK

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source tcl/load_elf.tcl
# set design [lindex $argv 0] 
# set ws "SDK_Workspace"
# puts "\nOpening $design XPR project\n"

Opening simple_sume_switch XPR project

# open_project project/$design.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'bd_7ad4_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-28028-nsg-System/coregen/bd_7ad4_xpcs_0_1/elaborate/configure_gt.tcl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_a1aa_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-28028-nsg-System/coregen/bd_a1aa_xpcs_0_2/elaborate/configure_gt.tcl'. Please regenerate to continue.
open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1365.832 ; gain = 189.094 ; free physical = 7035 ; free virtual = 15561
# set bd_file [get_files -regexp -nocase {.*sub*.bd}]
# set elf_file ../sw/embedded/$ws/$design/app/Debug/app.elf
# puts "\nOpening $design BD project\n"

Opening simple_sume_switch BD project

# open_bd_design $bd_file
Adding cell -- xilinx.com:ip:axi_iic:2.0 - axi_iic_0
Adding cell -- xilinx.com:ip:axi_uartlite:2.0 - axi_uartlite_0
Adding cell -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_1
Adding cell -- xilinx.com:ip:mdm:3.2 - mdm_1
Adding cell -- xilinx.com:ip:microblaze:10.0 - microblaze_0
Adding cell -- xilinx.com:ip:axi_intc:4.1 - microblaze_0_axi_intc
Adding cell -- xilinx.com:ip:xlconcat:2.1 - microblaze_0_xlconcat
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_clk_wiz_1_100M
Adding cell -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - dlmb_bram_if_cntlr
Adding cell -- xilinx.com:ip:lmb_v10:3.0 - dlmb_v10
Adding cell -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - ilmb_bram_if_cntlr
Adding cell -- xilinx.com:ip:lmb_v10:3.0 - ilmb_v10
Adding cell -- xilinx.com:ip:blk_mem_gen:8.4 - lmb_bram
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding cell -- xilinx.com:ip:util_vector_logic:2.0 - pcie_reset_inv
Adding cell -- xilinx.com:ip:axis_dwidth_converter:1.1 - axis_dwidth_dma_tx
Adding cell -- xilinx.com:ip:axis_dwidth_converter:1.1 - axis_dwidth_dma_rx
Adding cell -- xilinx.com:ip:axis_data_fifo:1.1 - axis_fifo_10g_rx
Adding cell -- xilinx.com:ip:axis_data_fifo:1.1 - axis_fifo_10g_tx
Adding cell -- NetFPGA:NetFPGA:nf_riffa_dma:1.0 - nf_riffa_dma_1
Adding cell -- xilinx.com:ip:axi_clock_converter:2.1 - axi_clock_converter_0
Adding cell -- xilinx.com:ip:pcie3_7x:4.3 - pcie3_7x_1
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m08_data_fifo
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m07_data_fifo
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m06_data_fifo
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m05_data_fifo
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m04_data_fifo
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m03_data_fifo
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m02_data_fifo
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m01_data_fifo
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m00_data_fifo
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - s00_data_fifo
Adding cell -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Successfully read diagram <control_sub> from BD file </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
# if {[llength [get_files app.elf]]} {
# 	puts "ELF File [get_files app.elf] is already associated"
# 	exit
# } else {
# 	add_files -norecurse -force ${elf_file} 
# 	set_property SCOPED_TO_REF [current_bd_design] [get_files -all -of_objects [get_fileset sources_1] ${elf_file}]
# 	set_property SCOPED_TO_CELLS nf_mbsys/mbsys/microblaze_0 [get_files -all -of_objects [get_fileset sources_1] ${elf_file}]
# }
WARNING: [Vivado 12-818] No files matched 'app.elf'
# reset_run impl_1 -prev_step
# launch_runs impl_1 -to_step write_bitstream
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'...
[Thu Jul 25 01:22:07 2019] Launched impl_1...
Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/runme.log
# wait_on_run impl_1
[Thu Jul 25 01:22:07 2019] Waiting for impl_1 to finish...

*** Running vivado
    with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace


****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source top.tcl -notrace
Command: link_design -top top -part xc7vx690tffg1761-3
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0.dcp' for cell 'control_sub_i/dma_sub/axi_clock_converter_0'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0.dcp' for cell 'control_sub_i/dma_sub/nf_riffa_dma_1'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0.dcp' for cell 'control_sub_i/dma_sub/pcie3_7x_1'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0.dcp' for cell 'control_sub_i/dma_sub/pcie_reset_inv'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_iic_0'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_uartlite_0'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.dcp' for cell 'control_sub_i/nf_mbsys/clk_wiz_1'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10'
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram'
INFO: [Netlist 29-17] Analyzing 5150 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc:50]
get_clocks: Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 3550.098 ; gain = 1022.805 ; free physical = 4453 ; free virtual = 12518
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst'
INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc:124]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc:57]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
WARNING: [Constraints 18-619] A clock with name 'xphy_refclk_p' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:92]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:114]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:115]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:116]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:117]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:118]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:119]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:120]
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:121]
INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:149]
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Common 17-14] Message 'Vivado 12-3272' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Common 17-14] Message 'XPM_CDC_GRAY: TCL 1000' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. 
     Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. 
     Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z20ebgxmlf2wz2spqe_2680/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gghdqjx444zucre728gloe6_277/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/khxyr7u7157o34roo3qky80hlj_1032/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Generating merged BMM file for the design top 'top'...
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/data/mb_bootloop_le.elf 
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 900 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
  LUT6_2 => LUT6_2 (LUT5, LUT6): 80 instances
  RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 367 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances
  RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 351 instances
  RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 42 instances

148 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:02:23 ; elapsed = 00:02:57 . Memory (MB): peak = 4771.598 ; gain = 3447.195 ; free physical = 4649 ; free virtual = 12720
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4646 ; free virtual = 12718

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1402240af

Time (s): cpu = 00:00:20 ; elapsed = 00:00:07 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4381 ; free virtual = 12448

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 25 inverter(s) to 100 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 17dfaa891

Time (s): cpu = 00:00:40 ; elapsed = 00:00:29 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4647 ; free virtual = 12715
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 18 inverter(s) to 50 load pin(s).
Phase 2 Constant propagation | Checksum: 1b337fea4

Time (s): cpu = 00:00:47 ; elapsed = 00:00:36 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4649 ; free virtual = 12717
INFO: [Opt 31-389] Phase Constant propagation created 1240 cells and removed 2983 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 16d2e5c1b

Time (s): cpu = 00:02:58 ; elapsed = 00:02:47 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4650 ; free virtual = 12718
INFO: [Opt 31-389] Phase Sweep created 9 cells and removed 89946 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: f867f715

Time (s): cpu = 00:03:01 ; elapsed = 00:02:51 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4649 ; free virtual = 12717
INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 2 cells.

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 1672e8bf6

Time (s): cpu = 00:03:08 ; elapsed = 00:02:58 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4655 ; free virtual = 12723
INFO: [Opt 31-389] Phase Shift Register Optimization created 1 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 10b83d1fa

Time (s): cpu = 00:03:13 ; elapsed = 00:03:02 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4654 ; free virtual = 12722
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 20 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.36 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4654 ; free virtual = 12722
Ending Logic Optimization Task | Checksum: 1b7d7e764

Time (s): cpu = 00:03:14 ; elapsed = 00:03:03 . Memory (MB): peak = 4771.598 ; gain = 0.000 ; free physical = 4655 ; free virtual = 12723

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.047 | TNS=0.000 |
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 1 BRAM(s) out of a total of 564 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 43 WE to EN ports
Number of BRAM Ports augmented: 130 newly gated: 125 Total Ports: 1128
Ending PowerOpt Patch Enables Task | Checksum: 1861721fa

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4316 ; free virtual = 12384
Ending Power Optimization Task | Checksum: 1861721fa

Time (s): cpu = 00:02:57 ; elapsed = 00:01:13 . Memory (MB): peak = 5563.586 ; gain = 791.988 ; free physical = 4550 ; free virtual = 12618

Starting Final Cleanup Task

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Logic Optimization Task | Checksum: 211f4088b

Time (s): cpu = 00:00:30 ; elapsed = 00:00:15 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4571 ; free virtual = 12639
Ending Final Cleanup Task | Checksum: 211f4088b

Time (s): cpu = 00:00:30 ; elapsed = 00:00:16 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4571 ; free virtual = 12639
INFO: [Common 17-83] Releasing license: Implementation
171 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:07:08 ; elapsed = 00:04:44 . Memory (MB): peak = 5563.586 ; gain = 791.988 ; free physical = 4571 ; free virtual = 12639
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.10 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4548 ; free virtual = 12624
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_opt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:55 ; elapsed = 00:00:48 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4517 ; free virtual = 12628
INFO: [runtcl-4] Executing : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:23 ; elapsed = 00:00:12 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4480 ; free virtual = 12592
Command: place_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/ENBWREN (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[0] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[1] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[2] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4479 ; free virtual = 12591
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1547ea0fd

Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.32 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4479 ; free virtual = 12591
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4476 ; free virtual = 12589

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
	control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
	control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
	control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
	control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [Place 30-139] Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.

	control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23
	control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 120bdf31f

Time (s): cpu = 00:01:06 ; elapsed = 00:00:34 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 4246 ; free virtual = 12359

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 226d5a904

Time (s): cpu = 00:02:19 ; elapsed = 00:01:04 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3911 ; free virtual = 12023

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 226d5a904

Time (s): cpu = 00:02:20 ; elapsed = 00:01:05 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3910 ; free virtual = 12023
Phase 1 Placer Initialization | Checksum: 226d5a904

Time (s): cpu = 00:02:20 ; elapsed = 00:01:05 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3910 ; free virtual = 12023

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 20d9d4ba2

Time (s): cpu = 00:02:58 ; elapsed = 00:01:18 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3786 ; free virtual = 11899

Phase 2.2 Physical Synthesis In Placer
WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins.
INFO: [Physopt 32-76] Pass 1. Identified 3 candidate nets for fanout optimization.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_RESET_clk_lookup/Rst. Replicated 8 times.
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_reset_i/cpllreset. Replicated 13 times.
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/SS[0]. Replicated 13 times.
WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins.
INFO: [Physopt 32-232] Optimized 3 nets. Created 34 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 3 nets or cells. Created 34 new cells, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.40 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3692 ; free virtual = 11805
INFO: [Physopt 32-64] No nets found for fanout-optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_445 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_446 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__0 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].metadata_fifo/fifo/metadata_wr_en[4] could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].metadata_fifo/fifo/queue_reg_0_i_1__8 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__0 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_23_i_1_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_23_i_1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__0 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_3_i_1__0_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_3_i_1__0 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_1[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Hash_Lookup_inst/i_/xpm_memory_tdpram_inst_i_4 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[1].output_fifo/fifo/queue_reg_0_i_1__6_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[1].output_fifo/fifo/queue_reg_0_i_1__6 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_1[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_Hash_Lookup_inst/i_/xpm_memory_tdpram_inst_i_5 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[1].output_fifo/fifo/queue_reg_13_i_1__2_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[1].output_fifo/fifo/queue_reg_13_i_1__2 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Update_inst/realmain_lookup_table_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_0[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Update_inst/realmain_lookup_table_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/RamWrData[51] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/xpm_memory_tdpram_inst_i_393 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_13_i_1_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_13_i_1 could not be replicated
INFO: [Physopt 32-117] Net nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/converter_tx/nf_converter/input_fifo/SLAVE_WIDER.counter_reg[0][0] could not be optimized because driver nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/converter_tx/nf_converter/input_fifo/queue_reg_0_i_74 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/RamWrData[49] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/xpm_memory_tdpram_inst_i_395 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1 could not be replicated
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/RamWrData[45] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/xpm_memory_tdpram_inst_i_399 could not be replicated
INFO: [Physopt 32-68] No nets found for critical-cell optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3700 ; free virtual = 11813

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------
|  Optimization       |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------
|  Very High Fanout   |           34  |              0  |                     3  |           0  |           1  |  00:00:04  |
|  Fanout             |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Critical Cell      |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total              |           34  |              0  |                     3  |           0  |           3  |  00:00:04  |
-----------------------------------------------------------------------------------------------------------------------------


Phase 2.2 Physical Synthesis In Placer | Checksum: 1bc22b310

Time (s): cpu = 00:08:42 ; elapsed = 00:03:35 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3691 ; free virtual = 11804
Phase 2 Global Placement | Checksum: 2306353e4

Time (s): cpu = 00:08:52 ; elapsed = 00:03:40 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3781 ; free virtual = 11893

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 2306353e4

Time (s): cpu = 00:08:54 ; elapsed = 00:03:41 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3778 ; free virtual = 11891

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 27048886c

Time (s): cpu = 00:10:02 ; elapsed = 00:04:04 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3752 ; free virtual = 11864

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2a44a95c7

Time (s): cpu = 00:10:06 ; elapsed = 00:04:07 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3751 ; free virtual = 11863

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 2655393f0

Time (s): cpu = 00:10:06 ; elapsed = 00:04:07 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3751 ; free virtual = 11863

Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 2655393f0

Time (s): cpu = 00:10:07 ; elapsed = 00:04:08 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3751 ; free virtual = 11863

Phase 3.6 Fast Optimization
Phase 3.6 Fast Optimization | Checksum: 22b3667c8

Time (s): cpu = 00:10:11 ; elapsed = 00:04:12 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3749 ; free virtual = 11861

Phase 3.7 Small Shape Detail Placement
Phase 3.7 Small Shape Detail Placement | Checksum: 1c5f90cce

Time (s): cpu = 00:10:57 ; elapsed = 00:04:55 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3556 ; free virtual = 11669

Phase 3.8 Re-assign LUT pins
Phase 3.8 Re-assign LUT pins | Checksum: 1a0fd3ba3

Time (s): cpu = 00:11:02 ; elapsed = 00:05:00 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3567 ; free virtual = 11680

Phase 3.9 Pipeline Register Optimization
Phase 3.9 Pipeline Register Optimization | Checksum: 28ca59471

Time (s): cpu = 00:11:04 ; elapsed = 00:05:01 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3566 ; free virtual = 11679
Phase 3 Detail Placement | Checksum: 28ca59471

Time (s): cpu = 00:11:05 ; elapsed = 00:05:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3567 ; free virtual = 11680

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 28ea1668c

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-33] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[2].output_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-33] Processed net nf_datapath_0/input_arbiter_v1_0/inst/in_arb_queues[3].in_arb_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-33] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-33] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-33] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-33] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-31] BUFG insertion identified 6 candidate nets, 0 success, 6 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 28ea1668c

Time (s): cpu = 00:12:20 ; elapsed = 00:05:24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3698 ; free virtual = 11810
INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.410. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1b967b8a7

Time (s): cpu = 00:15:40 ; elapsed = 00:08:50 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3698 ; free virtual = 11814
Phase 4.1 Post Commit Optimization | Checksum: 1b967b8a7

Time (s): cpu = 00:15:41 ; elapsed = 00:08:51 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3698 ; free virtual = 11814

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1b967b8a7

Time (s): cpu = 00:15:43 ; elapsed = 00:08:52 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3714 ; free virtual = 11831

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1b967b8a7

Time (s): cpu = 00:15:44 ; elapsed = 00:08:53 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3719 ; free virtual = 11836

Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 15dd1be9b

Time (s): cpu = 00:15:45 ; elapsed = 00:08:54 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3720 ; free virtual = 11836
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15dd1be9b

Time (s): cpu = 00:15:46 ; elapsed = 00:08:55 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3720 ; free virtual = 11836
Ending Placer Task | Checksum: 6ed46efd

Time (s): cpu = 00:15:46 ; elapsed = 00:08:56 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3988 ; free virtual = 12105
INFO: [Common 17-83] Releasing license: Implementation
245 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:16:01 ; elapsed = 00:09:09 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3989 ; free virtual = 12105
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:20 ; elapsed = 00:00:08 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3632 ; free virtual = 12033
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:06 ; elapsed = 00:00:51 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3884 ; free virtual = 12071
INFO: [runtcl-4] Executing : report_io -file top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.34 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3843 ; free virtual = 12031
INFO: [runtcl-4] Executing : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3881 ; free virtual = 12069
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:01 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3881 ; free virtual = 12071
Command: phys_opt_design -directive ExploreWithHoldFix
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: ExploreWithHoldFix
Netlist sorting complete. Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.27 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3809 ; free virtual = 11999

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.149 | TNS=-460.660 |
Phase 1 Physical Synthesis Initialization | Checksum: 10dd5ee7d

Time (s): cpu = 00:01:23 ; elapsed = 00:00:23 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3720 ; free virtual = 11910
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.149 | TNS=-460.660 |

Phase 2 Fanout Optimization
INFO: [Physopt 32-64] No nets found for fanout-optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 2 Fanout Optimization | Checksum: 10dd5ee7d

Time (s): cpu = 00:01:28 ; elapsed = 00:00:26 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3708 ; free virtual = 11898

Phase 3 Placement Based Optimization
INFO: [Physopt 32-660] Identified 103 candidate nets for placement-based optimization.
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0].  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0].  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_446
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_497_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_497
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[3].  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_445
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__2_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_50_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_50
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_42_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_42
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_516_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_516
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_484_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_484
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15
INFO: [Physopt 32-661] Optimized 61 nets.  Re-placed 61 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 61 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 61 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.914 | TNS=-412.661 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3680 ; free virtual = 11870
Phase 3 Placement Based Optimization | Checksum: c7405456

Time (s): cpu = 00:01:43 ; elapsed = 00:00:32 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3680 ; free virtual = 11870

Phase 4 MultiInst Placement Optimization
INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__2_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__2/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_501_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_501/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_529_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_529/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__1_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1/O
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0/O
INFO: [Physopt 32-661] Optimized 36 nets.  Re-placed 75 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 36 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 75 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.886 | TNS=-401.071 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3679 ; free virtual = 11870
Phase 4 MultiInst Placement Optimization | Checksum: c7b24d98

Time (s): cpu = 00:02:24 ; elapsed = 00:00:47 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3679 ; free virtual = 11870

Phase 5 Rewire
INFO: [Physopt 32-246] Starting Signal Push optimization...
INFO: [Physopt 32-77] Pass 1. Identified 5 candidate nets for rewire optimization.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3677 ; free virtual = 11868
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3677 ; free virtual = 11868
Phase 5 Rewire | Checksum: 14cc29ac3

Time (s): cpu = 00:02:27 ; elapsed = 00:00:50 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3678 ; free virtual = 11868

Phase 6 Critical Cell Optimization
INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]. Replicated 6 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]. Replicated 5 times.
INFO: [Physopt 32-601] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0. Net driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511 was replaced.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]. Replicated 10 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_51_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0]. Replicated 4 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0. Replicated 1 times.
INFO: [Physopt 32-232] Optimized 23 nets. Created 52 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 23 nets or cells. Created 52 new cells, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.883 | TNS=-394.421 |
Netlist sorting complete. Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.30 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3675 ; free virtual = 11865
Phase 6 Critical Cell Optimization | Checksum: 164a8e8c9

Time (s): cpu = 00:03:38 ; elapsed = 00:01:30 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3675 ; free virtual = 11865

Phase 7 Fanout Optimization
INFO: [Physopt 32-76] Pass 1. Identified 4 candidate nets for fanout optimization.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/D[0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/p_11_in. Replicated 4 times.
INFO: [Physopt 32-572] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_0_i_18__0_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/D[2]. Replicated 8 times.
INFO: [Physopt 32-232] Optimized 2 nets. Created 12 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 12 new cells, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.883 | TNS=-394.492 |
Netlist sorting complete. Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.31 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3676 ; free virtual = 11866
Phase 7 Fanout Optimization | Checksum: 1e00242e0

Time (s): cpu = 00:03:46 ; elapsed = 00:01:34 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3676 ; free virtual = 11867

Phase 8 Placement Based Optimization
INFO: [Physopt 32-660] Identified 162 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica
INFO: [Common 17-14] Message 'Physopt 32-663' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_445
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_5.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_446
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_25__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_25__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN_6.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica_6
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48
INFO: [Physopt 32-661] Optimized 50 nets.  Re-placed 50 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 50 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 50 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.883 | TNS=-389.342 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3674 ; free virtual = 11865
Phase 8 Placement Based Optimization | Checksum: 227bc255d

Time (s): cpu = 00:04:08 ; elapsed = 00:01:42 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3674 ; free virtual = 11865

Phase 9 MultiInst Placement Optimization
INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19/O
INFO: [Physopt 32-661] Optimized 16 nets.  Re-placed 36 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 16 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 36 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.883 | TNS=-388.214 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11864
Phase 9 MultiInst Placement Optimization | Checksum: 1695dda7b

Time (s): cpu = 00:05:39 ; elapsed = 00:02:11 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11864

Phase 10 Rewire
INFO: [Physopt 32-246] Starting Signal Push optimization...
INFO: [Physopt 32-77] Pass 1. Identified 3 candidate nets for rewire optimization.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11864
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11864
Phase 10 Rewire | Checksum: 191f4059e

Time (s): cpu = 00:05:40 ; elapsed = 00:02:13 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11865

Phase 11 Critical Cell Optimization
INFO: [Physopt 32-46] Identified 19 candidate nets for critical-cell optimization.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0. Replicated 3 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1]. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-232] Optimized 9 nets. Created 14 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 9 nets or cells. Created 14 new cells, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.852 | TNS=-384.781 |
Netlist sorting complete. Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.28 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11864
Phase 11 Critical Cell Optimization | Checksum: b01ffebe

Time (s): cpu = 00:06:23 ; elapsed = 00:02:37 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3672 ; free virtual = 11864

Phase 12 Slr Crossing Optimization
Phase 12 Slr Crossing Optimization | Checksum: b01ffebe

Time (s): cpu = 00:06:23 ; elapsed = 00:02:37 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3672 ; free virtual = 11864

Phase 13 Fanout Optimization
INFO: [Physopt 32-76] Pass 1. Identified 6 candidate nets for fanout optimization.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/D[0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/p_11_in_repN_2 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/CamReg_reg[3][0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/CamReg was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/CamReg_reg[1][0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/CamReg_reg[1][0]_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3672 ; free virtual = 11863
Phase 13 Fanout Optimization | Checksum: edb9840f

Time (s): cpu = 00:06:36 ; elapsed = 00:02:44 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3672 ; free virtual = 11863

Phase 14 Placement Based Optimization
INFO: [Physopt 32-660] Identified 166 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_4.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_4.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_5.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_3.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_3
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_446
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_445
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN_6.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica_6
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_499_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_499
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_525_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_525
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_481
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_39__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1
INFO: [Physopt 32-661] Optimized 25 nets.  Re-placed 25 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 25 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 25 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.852 | TNS=-383.554 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11865
Phase 14 Placement Based Optimization | Checksum: 162888118

Time (s): cpu = 00:06:59 ; elapsed = 00:02:52 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3673 ; free virtual = 11865

Phase 15 MultiInst Placement Optimization
INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica_1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498/O
INFO: [Physopt 32-661] Optimized 15 nets.  Re-placed 37 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 15 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 37 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.852 | TNS=-380.858 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3674 ; free virtual = 11866
Phase 15 MultiInst Placement Optimization | Checksum: e821a476

Time (s): cpu = 00:08:58 ; elapsed = 00:03:30 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3674 ; free virtual = 11866

Phase 16 Rewire
INFO: [Physopt 32-246] Starting Signal Push optimization...
INFO: [Physopt 32-77] Pass 1. Identified 4 candidate nets for rewire optimization.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862
Phase 16 Rewire | Checksum: eab9b61a

Time (s): cpu = 00:09:00 ; elapsed = 00:03:32 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862

Phase 17 Critical Cell Optimization
INFO: [Physopt 32-46] Identified 24 candidate nets for critical-cell optimization.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2]. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0. Replicated 4 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0. Replicated 2 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0. Replicated 1 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0_repN was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-232] Optimized 12 nets. Created 18 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 18 new cells, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.842 | TNS=-380.825 |
Netlist sorting complete. Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.28 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3668 ; free virtual = 11860
Phase 17 Critical Cell Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:55 ; elapsed = 00:04:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3668 ; free virtual = 11861

Phase 18 DSP Register Optimization
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 18 DSP Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:55 ; elapsed = 00:04:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3669 ; free virtual = 11861

Phase 19 BRAM Register Optimization
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 19 BRAM Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:56 ; elapsed = 00:04:03 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3669 ; free virtual = 11861

Phase 20 URAM Register Optimization
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 20 URAM Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:56 ; elapsed = 00:04:03 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3669 ; free virtual = 11861

Phase 21 Shift Register Optimization
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 21 Shift Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:57 ; elapsed = 00:04:04 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3671 ; free virtual = 11863

Phase 22 DSP Register Optimization
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 22 DSP Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:57 ; elapsed = 00:04:04 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3671 ; free virtual = 11863

Phase 23 BRAM Register Optimization
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 23 BRAM Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:58 ; elapsed = 00:04:05 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3671 ; free virtual = 11863

Phase 24 URAM Register Optimization
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 24 URAM Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:58 ; elapsed = 00:04:05 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3671 ; free virtual = 11863

Phase 25 Shift Register Optimization
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 25 Shift Register Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:09:58 ; elapsed = 00:04:06 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862

Phase 26 Critical Pin Optimization
INFO: [Physopt 32-606] Identified 14 candidate nets for critical-pin optimization.
INFO: [Physopt 32-608] Optimized 8 nets.  Swapped 137 pins.
INFO: [Physopt 32-775] End 1 Pass. Optimized 8 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 137 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.709 | TNS=-375.928 |
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862
Phase 26 Critical Pin Optimization | Checksum: 1b96724ec

Time (s): cpu = 00:10:00 ; elapsed = 00:04:07 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3670 ; free virtual = 11862

Phase 27 Very High Fanout Optimization
INFO: [Physopt 32-76] Pass 1. Identified 100 candidate nets for fanout optimization.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/out[3] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/RX_TUPLE_VALID. Replicated 3 times.
INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/rRst was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/rRst was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_2/valid_2. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_3/TX_TUPLE_VALID. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_3/valid_1. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_1/MUX_TUPLE_control_reg[9]_0[0]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_5/valid_1. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_6/TX_TUPLE_VALID. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_6/valid_1. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_8/MUX_TUPLE_realmain_lookup_table_0_req_reg[0]_0. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_8/valid_2. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/wr_en. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_12/valid_1. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_0/E[0]. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/TUPLE_digest_data_0_reg[0]. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_RESET_clk_line/clk_line_rst_high. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_1/valid_6. Replicated 1 times.
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/user_reset. Replicated 2 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/valid_6. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_0_reset. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst/stage_0/tupleForward_inst/Enable_d_1. Replicated 1 times.
INFO: [Physopt 32-81] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[2].output_fifo/fifo/SR[0]. Replicated 8 times.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopPipe_lvl_0/TopPipe_lvl_0_t_inst/stage_3/MUX_TUPLE_TopPipe_fl[112]_i_2__1_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net nf_datapath_0/input_arbiter_v1_0/inst/in_arb_queues[3].in_arb_fifo/fifo/SR[0]. Replicated 8 times.
INFO: [Physopt 32-81] Processed net nf_10g_interface_3/inst/nf_10g_interface_cpu_regs_inst/pcspmastatusvector13_reg_reg[0][0]. Replicated 1 times.
INFO: [Physopt 32-232] Optimized 23 nets. Created 43 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 23 nets or cells. Created 43 new cells, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.709 | TNS=-375.933 |
Netlist sorting complete. Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.62 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11849
Phase 27 Very High Fanout Optimization | Checksum: 134a2d502

Time (s): cpu = 00:11:48 ; elapsed = 00:04:56 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11849

Phase 28 Placement Based Optimization
INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_49
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_4.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_496
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_5.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_25_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_25
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_29__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_498
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_4.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6__0_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_512_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_512
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[2].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_446
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_470
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_511
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_500
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_476
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_445
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_464
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_505_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_461
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_462
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_499_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_499
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_463
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_448
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_480
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_474_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_474
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_517
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_497_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_497
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_3.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2_replica_3
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_35__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_525_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_525
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_44
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_23
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_482
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_33_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_33
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_8__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_508_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_508
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_468_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_468
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_510_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_26_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_26
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/addrb[1]_repN_7.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__2_replica_7
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_40_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_40
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/D[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_5
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_459_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_459
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Hash_Update_inst/Hash3_i[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Hash_Update_inst/xpm_memory_tdpram_inst_i_562
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/Addr[0]_i_2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/Addr[0]_i_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/Addr[0]_i_4_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/realmain_nat64_0_t_Randmod4_inst/Addr[0]_i_4
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/UpdateValueOut_i[65].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/RamRdData_r_reg[193]
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_473
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_1[1]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_447_replica_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_48
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/p_11_in_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/Hit_r1_i_3_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1_reg[434][38].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1[166]_i_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_194_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_194
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/RamRdData_ram[23].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_215
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1[166].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1_reg[166]
INFO: [Physopt 32-662] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_0_i_18__0_n_0.  Did not re-place instance nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_0_i_18__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_2_0.  Did not re-place instance nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_2_i_19
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_2.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_211_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_211
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/RamRdData_ram[6].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_229
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_195_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_195
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_15__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/RamRdData_r_reg[30].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/RamRdData_r[30]_i_2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_174_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_174
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_153_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_153
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/Entry[157]_i_1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/Entry[157]_i_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/CamReg_reg[3][434][157].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Update_inst/Entry_reg[157]
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_129_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Hit_r1_i_129
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1_reg[434][62].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1[190]_i_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1[190].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1_reg[190]
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1_reg[434][5].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1[133]_i_1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1[133].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/Data_r1_reg[133]
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1_reg[434][11].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/Data_r1[139]_i_1
INFO: [Physopt 32-661] Optimized 54 nets.  Re-placed 54 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 54 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 54 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.709 | TNS=-329.151 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3656 ; free virtual = 11849
Phase 28 Placement Based Optimization | Checksum: b1b8185e

Time (s): cpu = 00:12:25 ; elapsed = 00:05:08 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3656 ; free virtual = 11849

Phase 29 MultiInst Placement Optimization
INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica_1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_37__0_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_527/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_9/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_31__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_18/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_55_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_24_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_11/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_515_replica_1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_503_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_45_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_20__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_528_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_43/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_531_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_32/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_520/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_36__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_6/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_465/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_502/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_17/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_7__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_27__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_14__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_n_0_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_495_replica_1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_30/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13__1/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_41/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__0/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_523_replica/O
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_13/O
INFO: [Physopt 32-661] Optimized 12 nets.  Re-placed 30 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 30 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.709 | TNS=-334.110 |
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11850
Phase 29 MultiInst Placement Optimization | Checksum: 110fdc99e

Time (s): cpu = 00:14:11 ; elapsed = 00:05:43 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11850

Phase 30 Critical Path Optimization
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.709 | TNS=-334.110 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[284]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.671 | TNS=-334.266 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[284]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.661 | TNS=-334.245 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[212]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.656 | TNS=-334.212 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/doutb[176]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.653 | TNS=-333.980 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.650 | TNS=-333.409 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5_replica
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]_repN. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.643 | TNS=-332.975 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_3
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.619 | TNS=-332.984 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.615 | TNS=-331.751 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_5.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_5
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_5. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.610 | TNS=-331.613 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[212]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__2_replica
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0]_repN. Replicated 2 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_0[0]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.593 | TNS=-331.275 |
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.592 | TNS=-331.268 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2_replica
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.588 | TNS=-331.142 |
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.586 | TNS=-331.140 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.586 | TNS=-330.972 |
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.585 | TNS=-330.384 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0/O
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_34__0_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.584 | TNS=-329.936 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22/O
INFO: [Physopt 32-601] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0. Net driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22 was replaced.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.567 | TNS=-329.916 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/doutb[176]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_1
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_1. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.564 | TNS=-329.780 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__1_replica
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.564 | TNS=-329.710 |
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_22_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.562 | TNS=-329.696 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_4.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_4
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_4. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.555 | TNS=-329.563 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.550 | TNS=-329.341 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.550 | TNS=-328.463 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0/O
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_21__0_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_504_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.547 | TNS=-328.738 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2_replica_1
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.546 | TNS=-328.651 |
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.546 | TNS=-328.631 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46/O
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-328.571 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46/O
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_46_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[60]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-328.143 |
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/xgetxpkt_reg[25]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[2]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-326.696 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[6]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-326.500 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[8]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-326.316 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[15]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-326.132 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[16]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.948 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[18]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.764 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[23]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.580 |
INFO: [Physopt 32-702] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.533 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/rRdPtr_reg_n_0_[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.438 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/rRdPtr_reg_n_0_[1]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.343 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.191 |
INFO: [Physopt 32-662] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48].  Did not re-place instance nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg_reg[48]
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.151 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[50]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.141 |
INFO: [Physopt 32-662] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[50].  Did not re-place instance nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg_reg[50]
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[50]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.174 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.121 |
INFO: [Physopt 32-702] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[34]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.084 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[62]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-325.070 |
INFO: [Physopt 32-662] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48].  Did not re-place instance nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg_reg[48]
INFO: [Physopt 32-735] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.983 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[27]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.949 |
INFO: [Physopt 32-702] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/bd_a1aa_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/bd_a1aa_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[57]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.879 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[42]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.821 |
INFO: [Physopt 32-735] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[29]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.784 |
INFO: [Physopt 32-702] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/bd_7ad4_xpcs_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc_reg[10]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.541 | TNS=-324.774 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[284]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5_replica
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[0]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.536 | TNS=-324.723 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[248]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_5.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4_replica_5
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]_repN_5. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.532 | TNS=-324.604 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_3__2_replica_1
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[2]_repN_1. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.531 | TNS=-324.515 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/doutb[428]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-324.101 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica/O
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[57]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/output_pipeline_inst/pipeline_inst/Q[50]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.949 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/reg_inst/txc_output_register/pipeline_inst/gen_stages[1].rData_reg[1][37][60]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.751 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][48]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.681 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][49]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.611 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][50]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.541 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][51]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.471 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][52]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.401 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][53]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.331 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/rState[2]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.210 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/rState[4]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.089 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][64]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.023 |
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.023 |
Phase 30 Critical Path Optimization | Checksum: 2008e74ed

Time (s): cpu = 00:15:16 ; elapsed = 00:06:10 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3659 ; free virtual = 11852

Phase 31 Critical Path Optimization
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.529 | TNS=-323.023 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_replica/O
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_54_n_0_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.528 | TNS=-323.015 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.528 | TNS=-322.998 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_2_replica_1
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[3]_repN_1. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.527 | TNS=-323.029 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[320]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[1]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.527 | TNS=-322.979 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1/O
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0. Replicated 2 times.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.526 | TNS=-322.970 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[212]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_3
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_3. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.524 | TNS=-322.893 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_replica
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0_repN.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_replica/O
INFO: [Physopt 32-134] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0_repN. Rewiring did not optimize the net.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_19__1_n_0_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.886 |
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[38]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][65]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.820 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][60]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.766 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][61]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.712 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][62]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.658 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][63]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.604 |
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/xgetxpkt_reg[25]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[3]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-322.182 |
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/buffer/fifo/mem/rDout[68]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/WEBWE[0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/WEBWE[0].  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/rRAM_reg_0_i_1__2
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/WEBWE[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/monitor/wBufWen. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-319.668 |
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][18]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-319.618 |
INFO: [Common 17-14] Message 'Physopt 32-619' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][19]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][20]. Optimization improves timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1].  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_4__1
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2/O
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_16__2_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52
INFO: [Physopt 32-662] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0.  Did not re-place instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52/O
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_52_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[38]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][21]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][22]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][23]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][66]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][67]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][68]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][69]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][70]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][71]. Optimization improves timing on the net.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][30].  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/rDataOut_reg[48]
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/gen_stages[1].rData_reg[1][125][30]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/E[0].  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/rRdPtrPlus1[2]_i_1__7
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/txhf_inst/fifo_inst/mem/E[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_alignment_inst/gen_data_input_regs[3].data_register_/pipeline_inst/E[0]. Optimization improves timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/xgetxpkt_reg[25]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[6]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[5]. Optimization improves timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[0]. Optimization improves timing on the net.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[2].  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[2]
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[2].  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[2]/Q
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/xgetxpkt_reg[3]_i_2_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast.  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast_INST_0
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast. Optimization improves timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/D[30]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]. Optimization improves timing on the net.
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast.  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast_INST_0
INFO: [Physopt 32-662] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast.  Did not re-place instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast_INST_0/O
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/m_axis_xge_tx_tlast. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/CO[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words_sent_max_carry__1_i_1_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words_sent_max0[27]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words_sent_max0_carry_i_3_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/xgetxpkt_reg_reg[30][25]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1. Optimizations did not improve timing on the net.
Phase 31 Critical Path Optimization | Checksum: 1a4d27137

Time (s): cpu = 00:16:04 ; elapsed = 00:06:30 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11851

Phase 32 BRAM Enable Optimization
Phase 32 BRAM Enable Optimization | Checksum: 1a4d27137

Time (s): cpu = 00:16:05 ; elapsed = 00:06:31 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3657 ; free virtual = 11851

Phase 33 Hold Fix Optimization
INFO: [Physopt 32-668] Estimated Timing Summary | WNS=-0.523 | TNS=-299.398 | WHS=-0.382 | THS=-502.239 |
INFO: [Physopt 32-45] Identified 83 candidate nets for hold slack optimization.
INFO: [Physopt 32-234] Optimized 83 nets. Inserted 0 new ZHOLD_DELAYs. Calibrated 0 existing ZHOLD_DELAYs. Inserted 83 buffers.

INFO: [Physopt 32-668] Estimated Timing Summary | WNS=-0.523 | TNS=-299.398 | WHS=-0.249 | THS=-477.438 |
Phase 33 Hold Fix Optimization | Checksum: 180337eab

Time (s): cpu = 00:16:46 ; elapsed = 00:06:41 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3601 ; free virtual = 11795
Netlist sorting complete. Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.43 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3610 ; free virtual = 11804
INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=-0.523 | TNS=-299.398 | WHS=-0.249 | THS=-477.438 |

Summary of Physical Synthesis Optimizations
============================================


--------------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization          |  WNS Gain (ns)  |  TNS Gain (ns)  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Fanout                |          0.000  |         -0.070  |           12  |              0  |                     2  |           0  |           3  |  00:00:11  |
|  Placement Based       |          0.235  |        101.158  |            0  |              0  |                   190  |           0  |           4  |  00:00:32  |
|  MultiInst Placement   |          0.028  |         10.455  |            0  |              0  |                    79  |           0  |           4  |  00:01:54  |
|  Rewire                |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           3  |  00:00:04  |
|  Critical Cell         |          0.044  |         10.116  |           84  |              0  |                    44  |           0  |           3  |  00:01:32  |
|  Slr Crossing          |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register          |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  BRAM Register         |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  URAM Register         |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  Shift Register        |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  Critical Pin          |          0.133  |          4.897  |            0  |              0  |                     8  |           0  |           1  |  00:00:00  |
|  Very High Fanout      |          0.000  |         -0.005  |           43  |              0  |                    23  |           4  |           1  |  00:00:48  |
|  BRAM Enable           |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           1  |  00:00:01  |
|  Critical Path         |          0.186  |         34.712  |           17  |              0  |                    98  |           0  |           2  |  00:00:47  |
|  Total                 |          0.626  |        161.262  |          156  |              0  |                   444  |           4  |          31  |  00:05:49  |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------


Summary of Hold Fix Optimizations
=================================


--------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization               |  WHS Gain (ns)  |  THS Gain (ns)  |  Added LUTs  |  Added FFs  |  Optimized Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT1 and ZHOLD Insertion   |          0.133  |         24.801  |          83  |          0  |              83  |           0  |           1  |  00:00:04  |
|  Total                      |          0.133  |         24.801  |          83  |          0  |              83  |           0  |           1  |  00:00:04  |
--------------------------------------------------------------------------------------------------------------------------------------------------------------


Ending Physical Synthesis Task | Checksum: 18cb2de83

Time (s): cpu = 00:16:47 ; elapsed = 00:06:41 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3610 ; free virtual = 11804
INFO: [Common 17-83] Releasing license: Implementation
1631 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
phys_opt_design: Time (s): cpu = 00:17:58 ; elapsed = 00:06:57 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3777 ; free virtual = 11971
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:20 ; elapsed = 00:00:08 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3469 ; free virtual = 11943
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_physopt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:07 ; elapsed = 00:00:52 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3732 ; free virtual = 12000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC PLCK-18] Clock Placer Checks: Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. 
 This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.

	control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23
	control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Checksum: PlaceDB: 53bf3cfd ConstDB: 0 ShapeSum: 66ec5e1c RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 138daf8ae

Time (s): cpu = 00:01:29 ; elapsed = 00:00:48 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3329 ; free virtual = 11598
Post Restoration Checksum: NetGraph: b3084330 NumContArr: 85d2b57e Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 138daf8ae

Time (s): cpu = 00:01:34 ; elapsed = 00:00:53 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3332 ; free virtual = 11600

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 138daf8ae

Time (s): cpu = 00:01:36 ; elapsed = 00:00:55 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3261 ; free virtual = 11530

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 138daf8ae

Time (s): cpu = 00:01:36 ; elapsed = 00:00:55 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3261 ; free virtual = 11530
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1742210f0

Time (s): cpu = 00:03:11 ; elapsed = 00:01:26 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3181 ; free virtual = 11450
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.461 | TNS=-67.976| WHS=-0.431 | THS=-13540.465|


Phase 2.5 Update Timing for Bus Skew

Phase 2.5.1 Update Timing
Phase 2.5.1 Update Timing | Checksum: 17171acae

Time (s): cpu = 00:04:17 ; elapsed = 00:01:42 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3148 ; free virtual = 11416
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.461 | TNS=-53.594| WHS=N/A    | THS=N/A    |

Phase 2.5 Update Timing for Bus Skew | Checksum: 20f6bc080

Time (s): cpu = 00:04:18 ; elapsed = 00:01:42 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3142 ; free virtual = 11410
Phase 2 Router Initialization | Checksum: 19d293d02

Time (s): cpu = 00:04:18 ; elapsed = 00:01:43 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3142 ; free virtual = 11410

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 103668a54

Time (s): cpu = 00:06:46 ; elapsed = 00:02:21 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3093 ; free virtual = 11361

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 15369
 Number of Nodes with overlaps = 2285
 Number of Nodes with overlaps = 615
 Number of Nodes with overlaps = 199
 Number of Nodes with overlaps = 69
 Number of Nodes with overlaps = 18
 Number of Nodes with overlaps = 8
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.729 | TNS=-373.846| WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: d9e64346

Time (s): cpu = 00:15:17 ; elapsed = 00:05:11 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3108 ; free virtual = 11377

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 1441
 Number of Nodes with overlaps = 382
 Number of Nodes with overlaps = 101
 Number of Nodes with overlaps = 40
 Number of Nodes with overlaps = 25
 Number of Nodes with overlaps = 16
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.701 | TNS=-374.385| WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 192c96670

Time (s): cpu = 00:18:49 ; elapsed = 00:07:13 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3106 ; free virtual = 11375

Phase 4.3 Global Iteration 2
 Number of Nodes with overlaps = 1485
Phase 4.3 Global Iteration 2 | Checksum: 17ec49698

Time (s): cpu = 00:19:56 ; elapsed = 00:07:40 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3105 ; free virtual = 11374
Phase 4 Rip-up And Reroute | Checksum: 17ec49698

Time (s): cpu = 00:19:56 ; elapsed = 00:07:40 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3105 ; free virtual = 11374

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 1a2194665

Time (s): cpu = 00:20:13 ; elapsed = 00:07:44 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3105 ; free virtual = 11374
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.701 | TNS=-245.139| WHS=N/A    | THS=N/A    |

 Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 10afc45fd

Time (s): cpu = 00:20:18 ; elapsed = 00:07:46 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3095 ; free virtual = 11364

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 10afc45fd

Time (s): cpu = 00:20:18 ; elapsed = 00:07:46 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3095 ; free virtual = 11364
Phase 5 Delay and Skew Optimization | Checksum: 10afc45fd

Time (s): cpu = 00:20:18 ; elapsed = 00:07:46 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3095 ; free virtual = 11363

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: c1785a78

Time (s): cpu = 00:20:36 ; elapsed = 00:07:51 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3101 ; free virtual = 11370
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.701 | TNS=-245.045| WHS=-0.032 | THS=-0.184 |

Phase 6.1 Hold Fix Iter | Checksum: 15b0d8537

Time (s): cpu = 00:20:38 ; elapsed = 00:07:52 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3092 ; free virtual = 11360
Phase 6 Post Hold Fix | Checksum: 1a4067059

Time (s): cpu = 00:20:39 ; elapsed = 00:07:53 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3091 ; free virtual = 11360

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 7.66597 %
  Global Horizontal Routing Utilization  = 8.57671 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 8x8 Area, Max Cong = 96.0304%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X24Y260 -> INT_R_X31Y267
   INT_L_X24Y252 -> INT_R_X31Y259
   INT_L_X32Y252 -> INT_R_X39Y259
South Dir 8x8 Area, Max Cong = 88.2883%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X24Y244 -> INT_R_X31Y251
   INT_L_X32Y244 -> INT_R_X39Y251
East Dir 4x4 Area, Max Cong = 87.6838%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X24Y252 -> INT_R_X27Y255
   INT_L_X28Y244 -> INT_R_X31Y247
   INT_L_X32Y244 -> INT_R_X35Y247
West Dir 4x4 Area, Max Cong = 88.511%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X32Y248 -> INT_R_X35Y251
   INT_L_X32Y244 -> INT_R_X35Y247

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 2
Effective congestion level: 4 Aspect Ratio: 1 Sparse Ratio: 1.375
Direction: South
----------------
Congested clusters found at Level 3
Effective congestion level: 4 Aspect Ratio: 0.5 Sparse Ratio: 0.5
Direction: East
----------------
Congested clusters found at Level 2
Effective congestion level: 3 Aspect Ratio: 0.666667 Sparse Ratio: 1
Direction: West
----------------
Congested clusters found at Level 2
Effective congestion level: 3 Aspect Ratio: 0.333333 Sparse Ratio: 0.75

Phase 7 Route finalize | Checksum: 20ac97f31

Time (s): cpu = 00:20:41 ; elapsed = 00:07:53 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3088 ; free virtual = 11357

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 20ac97f31

Time (s): cpu = 00:20:41 ; elapsed = 00:07:54 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3086 ; free virtual = 11355

Phase 9 Depositing Routes
INFO: [Route 35-467] Router swapped GT pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_gt_common_block/gthe2_common_0_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y9/GTNORTHREFCLK0
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y23/GTREFCLK1
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y5/GTREFCLK1
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y22/GTREFCLK1
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y21/GTREFCLK1
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y20/GTREFCLK1
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK0
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y4/GTSOUTHREFCLK0
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK0
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK0
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK0
Phase 9 Depositing Routes | Checksum: 1c3cfef64

Time (s): cpu = 00:20:50 ; elapsed = 00:08:02 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3102 ; free virtual = 11371

Phase 10 Post Router Timing

Phase 10.1 Update Timing
Phase 10.1 Update Timing | Checksum: 1174b4bcd

Time (s): cpu = 00:21:07 ; elapsed = 00:08:07 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3107 ; free virtual = 11376
INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.701 | TNS=-245.045| WHS=0.010  | THS=0.000  |

WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 1174b4bcd

Time (s): cpu = 00:21:08 ; elapsed = 00:08:07 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3107 ; free virtual = 11376
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:21:08 ; elapsed = 00:08:08 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3283 ; free virtual = 11551

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
1661 Infos, 162 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:21:29 ; elapsed = 00:08:23 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3283 ; free virtual = 11551
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 2857 ; free virtual = 11479
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_routed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:07 ; elapsed = 00:00:52 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3169 ; free virtual = 11528
INFO: [runtcl-4] Executing : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:46 ; elapsed = 00:00:15 . Memory (MB): peak = 5563.586 ; gain = 0.000 ; free physical = 3062 ; free virtual = 11421
INFO: [runtcl-4] Executing : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 8 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:03:17 ; elapsed = 00:00:42 . Memory (MB): peak = 5634.605 ; gain = 71.020 ; free physical = 2123 ; free virtual = 10483
INFO: [runtcl-4] Executing : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
1673 Infos, 163 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:01:28 ; elapsed = 00:00:35 . Memory (MB): peak = 5920.883 ; gain = 286.277 ; free physical = 1946 ; free virtual = 10322
INFO: [runtcl-4] Executing : report_route_status -file top_route_status.rpt -pb top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:34 ; elapsed = 00:00:09 . Memory (MB): peak = 5975.855 ; gain = 54.973 ; free physical = 1872 ; free virtual = 10254
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_clock_utilization_routed.rpt
report_clock_utilization: Time (s): cpu = 00:00:54 ; elapsed = 00:00:54 . Memory (MB): peak = 5975.855 ; gain = 0.000 ; free physical = 1869 ; free virtual = 10252
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Command: phys_opt_design -directive AggressiveExplore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 99.4% nets are fully routed)
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AggressiveExplore
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Netlist sorting complete. Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.28 . Memory (MB): peak = 6007.871 ; gain = 0.000 ; free physical = 1865 ; free virtual = 10249

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.697 | TNS=-236.007 | WHS=0.010 | THS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 2c45ed33a

Time (s): cpu = 00:01:31 ; elapsed = 00:00:25 . Memory (MB): peak = 6007.871 ; gain = 0.000 ; free physical = 1721 ; free virtual = 10105
WARNING: [Physopt 32-745] Physical Optimization has determined that the magnitude of the negative slack is too large and it is highly unlikely that slack will be improved. Post-Route Physical Optimization is most effective when WNS is above -0.5ns

Phase 2 Critical Path Optimization
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.697 | TNS=-236.007 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-716] Net axi_clocking_i/clk_wiz_i/inst/clk_out1 has constraints that cannot be copied, and hence, it cannot be cloned. The constraint blocking the replication is set_data_check @ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc:76
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[392]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[1]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.573 | TNS=-235.774 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_5.  Re-placed instance nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_5__0_replica_5
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[0]_repN_5. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.542 | TNS=-235.722 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12_2[3]_repN_1. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-710] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_n_0. Critial path length was reduced through logic transformation on cell nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_10__0_comp.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_28__2_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.535 | TNS=-235.355 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN_1. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[49]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-235.326 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[49]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/xgetxpkt_reg[25]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[4]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[4].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[4]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-234.851 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[9]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[9].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[9]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-234.560 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[3]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[3].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[3]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-234.299 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[7]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[7].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[7]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-233.813 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[13]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[13].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[13]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-233.237 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[5]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[5].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[5]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-233.207 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[17]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[17].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[17]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-232.500 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[21]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[21].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[21]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-232.305 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[4]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[4].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[4]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-232.141 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[9]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[9].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[9]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-232.059 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[3]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[3].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[3]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.983 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[7]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[7].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[7]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.894 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[13]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[13].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[13]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.866 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-703] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[25]. Clock skew was adjusted for instance control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send_reg[25].
INFO: [Physopt 32-735] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/riffa_to_axis_conv/words2send[25]. Optimization improves timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.847 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/douta[356]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/gen_wr_b.gen_word_narrow.mem_reg_12[2]_repN_1. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_12_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_Hash_Lookup_inst/xpm_memory_tdpram_inst_i_47_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/doutb[49]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.847 | WHS=0.010 | THS=0.000 |
Phase 2 Critical Path Optimization | Checksum: 2c45ed33a

Time (s): cpu = 00:30:31 ; elapsed = 00:27:20 . Memory (MB): peak = 6833.941 ; gain = 826.070 ; free physical = 1706 ; free virtual = 10091

Phase 3 Hold Fix Optimization
INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.847 | WHS=0.010 | THS=0.000 |
INFO: [Physopt 32-45] Identified 3 candidate nets for hold slack optimization.
INFO: [Physopt 32-234] Optimized 3 nets. Inserted 0 new ZHOLD_DELAYs. Calibrated 0 existing ZHOLD_DELAYs. Inserted 3 buffers.

INFO: [Physopt 32-668] Current Timing Summary | WNS=-0.534 | TNS=-231.847 | WHS=0.010 | THS=0.000 |
Phase 3 Hold Fix Optimization | Checksum: 2c45ed33a

Time (s): cpu = 00:30:54 ; elapsed = 00:27:40 . Memory (MB): peak = 6833.941 ; gain = 826.070 ; free physical = 1702 ; free virtual = 10088
Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 6833.941 ; gain = 0.000 ; free physical = 1702 ; free virtual = 10088
INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=-0.534 | TNS=-231.847 | WHS=0.010 | THS=0.000 |

Summary of Physical Synthesis Optimizations
============================================


-------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization   |  WNS Gain (ns)  |  TNS Gain (ns)  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Critical Path  |          0.164  |          4.160  |            0  |              0  |                    18  |           0  |           1  |  00:26:54  |
-------------------------------------------------------------------------------------------------------------------------------------------------------------


Summary of Hold Fix Optimizations
=================================


--------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization               |  WHS Gain (ns)  |  THS Gain (ns)  |  Added LUTs  |  Added FFs  |  Optimized Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT1 and ZHOLD Insertion   |          0.000  |          0.000  |           3  |          0  |               3  |           0  |           1  |  00:00:19  |
|  Total                      |          0.000  |          0.000  |           3  |          0  |               3  |           0  |           1  |  00:00:19  |
--------------------------------------------------------------------------------------------------------------------------------------------------------------


Ending Physical Synthesis Task | Checksum: 2c45ed33a

Time (s): cpu = 00:30:55 ; elapsed = 00:27:40 . Memory (MB): peak = 6833.941 ; gain = 826.070 ; free physical = 1707 ; free virtual = 10092
INFO: [Common 17-83] Releasing license: Implementation
1767 Infos, 165 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
phys_opt_design: Time (s): cpu = 00:31:00 ; elapsed = 00:27:45 . Memory (MB): peak = 6833.941 ; gain = 858.086 ; free physical = 2127 ; free virtual = 10512
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:22 ; elapsed = 00:00:09 . Memory (MB): peak = 6865.957 ; gain = 0.000 ; free physical = 1713 ; free virtual = 10452
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_postroute_physopt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:08 ; elapsed = 00:00:52 . Memory (MB): peak = 6865.957 ; gain = 32.016 ; free physical = 2021 ; free virtual = 10496
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -warn_on_violation -file top_timing_summary_postroute_physopted.rpt -pb top_timing_summary_postroute_physopted.pb -rpx top_timing_summary_postroute_physopted.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:01:44 ; elapsed = 00:00:20 . Memory (MB): peak = 6865.957 ; gain = 0.000 ; free physical = 2065 ; free virtual = 10546
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_postroute_physopted.rpt -pb top_bus_skew_postroute_physopted.pb -rpx top_bus_skew_postroute_physopted.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
Command: write_bitstream -force top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.

Evaluation cores found in this design:
    IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features:
        IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
        IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
    IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
    IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features:
        IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
        IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
    IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.

Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1 is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica. Remove non-muxed BUFG if it is not desired
WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica_1. Remove non-muxed BUFG if it is not desired
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed).
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_25) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_26) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_27) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [Common 17-14] Message 'DRC REQP-181' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 53 Warnings, 126 Advisories
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 125573888 bits.
Writing bitstream ./top.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
1949 Infos, 219 Warnings, 2 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:04:04 ; elapsed = 00:03:23 . Memory (MB): peak = 6921.984 ; gain = 56.027 ; free physical = 2037 ; free virtual = 10534
INFO: [Common 17-206] Exiting Vivado at Thu Jul 25 01:18:44 2019...

*** Running vivado
    with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace


****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source top.tcl -notrace
Command: open_checkpoint top_postroute_physopt.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1176.738 ; gain = 0.000 ; free physical = 6852 ; free virtual = 15364
INFO: [Netlist 29-17] Analyzing 4406 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3480.551 ; gain = 181.945 ; free physical = 4677 ; free virtual = 13188
Restored from archive | CPU: 8.890000 secs | Memory: 207.106659 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3480.551 ; gain = 181.945 ; free physical = 4677 ; free virtual = 13188
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 754 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
  LUT6_2 => LUT6_2 (LUT5, LUT6): 79 instances
  RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 365 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances
  RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 211 instances
  RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 38 instances
  SRLC16E => SRL16E: 1 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2018.2 (64-bit) build 2258646
open_checkpoint: Time (s): cpu = 00:01:21 ; elapsed = 00:02:22 . Memory (MB): peak = 3480.551 ; gain = 2303.812 ; free physical = 4743 ; free virtual = 13255
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_nat64_0/realmain_nat64_0_t_Wrap_inst/realmain_nat64_0_t_IntTop_inst/realmain_nat64_0_t_Lookup_inst/realmain_nat64_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_lookup_table_0/realmain_lookup_table_0_t_Wrap_inst/realmain_lookup_table_0_t_IntTop_inst/realmain_lookup_table_0_t_Lookup_inst/realmain_lookup_table_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/kty4eu99g0lcln2zjl4dm8w48s9_2303/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/mvz7xkeut076iznclj71pbiykw6_1202/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/j4ljiyl61srd3ect0w0_1048/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/te3fcfez76chzmfek_1821/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/nczo24ruhk6u3b1ok20l9jc3z6zpaw_782/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/mjjip2n5ms3clnld2wphvbc0_2464/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/z9lcgcecur72ty6e3hwewxm68okrwjkz_836/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/w5y7682mjw2ipu44fcs95o4cqw9j_321/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/oifasqvrhgnf3x3oyfx42u_1092/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/lyq1o92avk5w3720fvrfdo_576/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/c7982oxn1ft1zx03d0_1883/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xlxy2vk2641yoha3e_1822/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ooy32m177bv6ya8qd36kkxz9ae9s_566/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lah2fef13rfm7lr6x_454/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uaw8hbzp8uthjy28n20bk_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/t539xkdlyz0yc8oovx06y8hcclnmjtr_2504/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jx2gwgarhcldkoh6_10/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
Command: write_bitstream -force top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.

Evaluation cores found in this design:
    IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features:
        IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
        IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
    IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
    IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features:
        IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
        IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
    IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.

Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1 is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica. Remove non-muxed BUFG if it is not desired
WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica_1. Remove non-muxed BUFG if it is not desired
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed).
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_25) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_26) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_27) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [Common 17-14] Message 'DRC REQP-181' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 53 Warnings, 126 Advisories
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/app.elf 
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 124888384 bits.
Writing bitstream ./top.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
189 Infos, 53 Warnings, 1 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:04:03 ; elapsed = 00:03:27 . Memory (MB): peak = 4527.492 ; gain = 1038.938 ; free physical = 4483 ; free virtual = 13008
INFO: [Common 17-206] Exiting Vivado at Thu Jul 25 01:28:03 2019...
[Thu Jul 25 01:28:04 2019] impl_1 finished
wait_on_run: Time (s): cpu = 00:05:31 ; elapsed = 00:05:57 . Memory (MB): peak = 2176.453 ; gain = 0.000 ; free physical = 6979 ; free virtual = 15507
# open_run impl_1
INFO: [Netlist 29-17] Analyzing 4406 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3688.289 ; gain = 178.945 ; free physical = 4879 ; free virtual = 13408
Restored from archive | CPU: 8.840000 secs | Memory: 207.107361 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3688.289 ; gain = 178.945 ; free physical = 4879 ; free virtual = 13408
Generating merged BMM file for the design top 'top'...
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/app.elf 
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 754 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
  LUT6_2 => LUT6_2 (LUT5, LUT6): 79 instances
  RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 24 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 365 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances
  RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 211 instances
  RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 38 instances
  SRLC16E => SRL16E: 1 instances

open_run: Time (s): cpu = 00:01:20 ; elapsed = 00:02:22 . Memory (MB): peak = 3688.289 ; gain = 1511.836 ; free physical = 4945 ; free virtual = 13474
# write_bitstream -force ../bitfiles/$design.bit
Command: write_bitstream -force ../bitfiles/simple_sume_switch.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.

Evaluation cores found in this design:
    IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features:
        IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
        IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
    IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
    IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features:
        IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
        IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
    IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.

Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1 is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica. Remove non-muxed BUFG if it is not desired
WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica is driven by another global buffer control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1_i1.usrclk1_i1_replica_1. Remove non-muxed BUFG if it is not desired
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
    control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed).
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_lookup_table_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_nat64_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/floqxoej5aicutpz7i0zfl3a2yo_1736/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ioexwad3y5i2qhphqmb2ken4km02_773/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k6j2b0g89m17enc7130a7tltr1s_699/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/k9vs7qqzhhdv2zey1_659/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_11) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_12) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mpjcdkflu7yrzqmbuolk5m3_440/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/aup6zkcizv14pimeye6t4q44_717/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dnamqnvcoxbq1q8d4ajs2o9r82uvt_186/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dvkcxpj9tgydwxf0uaacewfj1lgs44n_577/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jmn7mgem3iz1kdmn9sqw93_2107/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m7o3hoymg8uqcdqizeadzv8k_2122/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/osh9yoxxjklf0zptis9c_990/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_14) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/rqi3coc7d6nfo9vpmtw1osvanvjfag_1667/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/akxg1tfymljerus1vpcnepyv8wl7y_170/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/i4bhqagkugyabg8pt4qtyisoea79s5_80/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/kmx85e9k8hls511lexi9vcc3n9opnyf_1703/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/ufi21gd9cod5i8zmbsn_386/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/viwe29jpldowrxiyo9oh20jjqtzx6c6_1217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/lkis63w9hmt3fpru78meaacsu_1457/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/of49eycjluhg2js6xdhgiiy1js06gv_1190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/onctbgj1uc88lix0_190/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/rrx2o92507e60rsejcoaqy_2580/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/x59vx3wada7a411ba31_2374/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/hyrzp6taloqmmwij4f4sj4ghvca_564/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/wlrpvy4rsdrfl6s4u7kkyypl3_198/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/la3bvivtp1cnzub8_1029/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/s487z0rob4coa34tq19uftml_2207/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/xob1479vc8hxdsk2seqzos5lpnt7wwh_1463/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_25) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_26) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_27) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [Common 17-14] Message 'DRC REQP-181' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 53 Warnings, 126 Advisories
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Generating merged BMM file for the design top 'top'...
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/app.elf 
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 124888384 bits.
Writing bitstream ../bitfiles/simple_sume_switch.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
119 Infos, 53 Warnings, 1 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:04:01 ; elapsed = 00:03:26 . Memory (MB): peak = 4705.738 ; gain = 1017.449 ; free physical = 4730 ; free virtual = 13272
# exit
INFO: [Common 17-206] Exiting Vivado at Thu Jul 25 01:33:52 2019...
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
+ date
Don Jul 25 01:33:52 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles
+ mv simple_sume_switch.bit minip4.bit
+ cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.sh ./
+ date
Don Jul 25 01:33:52 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles/
+ pwd -P
+ chmod u+x /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles/program_switch.sh
+ pwd -P
+ sudo bash -c . /home/nico/master-thesis/netpfga/bashinit && /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles/program_switch.sh
++ which vivado
+ xilinx_tool_path=/opt/Xilinx/Vivado/2018.2/bin/vivado
+ bitimage=minip4.bit
+ configWrites=config_writes.sh
+ '[' -z minip4.bit ']'
+ '[' -z config_writes.sh ']'
+ '[' /opt/Xilinx/Vivado/2018.2/bin/vivado == '' ']'
+ rmmod sume_riffa
rmmod: ERROR: Module sume_riffa is not currently loaded
+ xsct /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl -tclargs minip4.bit
rlwrap: warning: your $TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
RUN loading image file.
minip4.bit
attempting to launch hw_server

****** Xilinx hw_server v2018.2
  **** Build date : Jun 14 2018-20:18:37
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application

INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121


initializing
  0%    0MB   0.0MB/s  ??:?? ETA
  8%    1MB   2.0MB/s  ??:?? ETA
 15%    1MB   1.8MB/s  ??:?? ETA
 22%    2MB   1.8MB/s  ??:?? ETA
 29%    3MB   1.7MB/s  ??:?? ETA
 36%    4MB   1.8MB/s  ??:?? ETA
 43%    5MB   1.7MB/s  00:04 ETA
 50%    6MB   1.7MB/s  00:03 ETA
 56%    7MB   1.7MB/s  00:03 ETA
 63%    7MB   1.7MB/s  00:02 ETA
 70%    8MB   1.7MB/s  00:02 ETA
 78%    9MB   1.7MB/s  00:01 ETA
 84%   10MB   1.7MB/s  00:01 ETA
 91%   11MB   1.7MB/s  00:00 ETA
 98%   12MB   1.7MB/s  00:00 ETA
100%   12MB   1.7MB/s  00:07    
fpga configuration failed. DONE PIN is not HIGH
    invoked from within
"::tcf::eval -progress ::xsdb::print_progress {::tcf::cache_enter tcfchan#0 {tcf_cache_eval {process_tcf_actions_cache_client ::tcfclient#0::arg}}}"
    (procedure "::tcf::cache_eval_with_progress" line 2)
    invoked from within
"::tcf::cache_eval_with_progress [dict get $arg chan]  [list process_tcf_actions_cache_client $argvar] $progress"
    (procedure "process_tcf_actions" line 1)
    invoked from within
"process_tcf_actions $arg ::xsdb::print_progress"
    (procedure "fpga" line 430)
    invoked from within
"fpga -f $bitimage"
    (file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl" line 33)
+ bash /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/pci_rescan_run.sh
Check programming FPGA or Reboot machine !
+ rmmod sume_riffa
rmmod: ERROR: Module sume_riffa is not currently loaded
+ modprobe sume_riffa
modprobe: FATAL: Module sume_riffa not found in directory /lib/modules/4.15.0-54-generic
+ ifconfig nf0 up
nf0: ERROR while getting interface flags: No such device
+ ifconfig nf1 up
nf1: ERROR while getting interface flags: No such device
+ ifconfig nf2 up
nf2: ERROR while getting interface flags: No such device
+ ifconfig nf3 up
nf3: ERROR while getting interface flags: No such device
+ bash config_writes.sh