9616 lines
655 KiB
Text
9616 lines
655 KiB
Text
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+ echo First source all variables and THEN run this script
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First source all variables and THEN run this script
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+ read something
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f ./nf_sume_sdnet_ip/SimpleSumeSwitch/xvlog.log
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
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minip4_solution.p4(51): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when TopParser terminates
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out metadata meta,
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^^^^
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minip4_solution.p4(49)
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parser TopParser(packet_in packet,
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^^^^^^^^^
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minip4_solution.p4(52): [--Wwarn=uninitialized_out_param] warning: out parameter digest_data may be uninitialized when TopParser terminates
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out digest_data_t digest_data,
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^^^^^^^^^^^
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minip4_solution.p4(49)
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parser TopParser(packet_in packet,
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^^^^^^^^^
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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./gen_testdata.py
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Applying pkt on nf0 at 1:
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nf0_applied times: [1]
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nf1_applied times: []
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nf2_applied times: []
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nf3_applied times: []
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
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Xilinx SDNet Compiler version 2018.2, build 2342300
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Compilation successful
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_externs.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ ./testdata/ ./sw/ --base_address 0x44020000
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_API.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_CLI.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
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cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
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cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
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cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
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# The following command only applies if running P4_SWITCH Questa Simulation with Ubuntu
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sed -i 's/vsim/vsim \-ldflags \"\-B\/usr\/lib\/x86\_64\-linux-gnu\"/g' nf_sume_sdnet_ip/SimpleSumeSwitch/questa.bash
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# modify the P4_SWITCH_tb so that it writes the table configuration writes to a file
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/modify_P4_SWITCH_tb.py nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv
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# Fix introduced for SDNet 2017.4
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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# Fix introduced for SDNet 2018.2
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sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp testdata/*.axi nf_sume_sdnet_ip/SimpleSumeSwitch/
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch
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+ ./vivado_sim.bash
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+ tee LOG
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+ find -name '*.v' -o -name '*.vp' -o -name '*.sv'
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+ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv %
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_dummy_table_for_netpfga_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_dummy_table_for_netpfga_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_dummy_table_for_netpfga_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port_0_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_increment_offset
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work
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INFO: [VRFC 10-311] analyzing module xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module xpm_counter_updn
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
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INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
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INFO: [VRFC 10-311] analyzing module xpm_fifo_async
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INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work
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INFO: [VRFC 10-311] analyzing module xpm_memory_base
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INFO: [VRFC 10-311] analyzing module asym_bwe_bb
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INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
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INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
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INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
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INFO: [VRFC 10-311] analyzing module xpm_memory_spram
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INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
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INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
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INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
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INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
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INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
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INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work
|
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request.vp" into library work
|
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|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_base
|
|||
|
|
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v" into library work
|
|||
|
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INFO: [VRFC 10-311] analyzing module glbl
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_dummy_table_for_netpfga_req_lookup_request_key
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp" into library work
|
|||
|
|
ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TB_System_Stim
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module Check
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch_tb
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute__STRUCT_ethertype
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_10_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_task
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_ingress_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_ethertype
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute__STRUCT_table_id
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_9_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_3_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_version
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ihl
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_diff_serv
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ecn
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_totalLen
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_identification
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_flags
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_fragOffset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_ttl
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_protocol
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute__STRUCT_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_8_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_4_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_version
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_traffic_class
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_flow_label
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_payload_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_next_header
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_hop_limit
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute__STRUCT_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_7_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_hw_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_protocol
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_hw_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_protocol_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_opcode
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_src_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_src_ipv4_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_dst_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute__STRUCT_dst_ipv4_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_6_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_6_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_seqNo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ackNo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_data_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_res
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_cwr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ece
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_urg
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_ack
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_psh
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_syn
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_fin
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_window
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute__STRUCT_urgentPtr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_5_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_7_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_payload_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute__STRUCT_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_4_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_8_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_code
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute__STRUCT_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_3_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_9_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_code
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute__STRUCT_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_2_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_10_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_router
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_solicitated
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_override
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_reserved
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute__STRUCT_target_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_1_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_11_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_ll_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_12_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_RESETTER_line
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_RESETTER_control
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_Engine
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_icmp6_na_ns
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_ipv4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_udp_v6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_udp_v4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_tcp_v6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_chk_tcp_v4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_v4sum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_v6sum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_meta_headerdiff
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_ethertype
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_reject
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ExtractShifter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_version
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ihl
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_diff_serv
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ecn
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_totalLen
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_identification
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_flags
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_fragOffset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_ttl
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_protocol
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_hdr_ipv4_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_TopParser_extracts_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_meta_length_without_ip_header
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv4_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_version
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_traffic_class
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_flow_label
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_payload_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_next_header
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_hop_limit
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_hdr_ipv6_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_TopParser_extracts_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_meta_length_without_ip_header
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_ipv6_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_hw_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_protocol
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_hw_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_protocol_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_opcode
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_src_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_src_ipv4_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_dst_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_hdr_arp_dst_ipv4_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_TopParser_extracts_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_arp_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_TupleForward
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_ExtractShifter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_code
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_hdr_icmp6_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_TopParser_extracts_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_seqNo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ackNo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_data_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_res
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_cwr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ece
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_urg
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_ack
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_psh
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_syn
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_fin
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_window
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_hdr_tcp_urgentPtr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_TopParser_extracts_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_tcp_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_udp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_payload_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_hdr_udp_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_TopParser_extracts_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_udp_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_code
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_hdr_icmp_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_TopParser_extracts_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_2_TupleForward
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_ExtractShifter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_router
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_solicitated
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_override
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_reserved
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_na_ns_target_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_ll_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_hdr_icmp6_option_link_layer_addr_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_TopParser_extracts_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_icmp6_neighbor_solicitation_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_3_TupleForward
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_4_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_accept
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp" into library work
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp" into library work
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/dummy_table_for_netpfga_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Wrap
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_IntTop
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Lookup
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Hash_Lookup
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_RamR1RW1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Cam
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Update
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Hash_Update
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod4_Rnd
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod5
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_Randmod5_Rnd
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t_csr
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_base
|
|||
|
|
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_cdc.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/dummy_table_for_netpfga_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module dummy_table_for_netpfga_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch
|
|||
|
|
+ true
|
|||
|
|
+ mkdir -p xsim.dir/xsc
|
|||
|
|
+ find -name '*.c'
|
|||
|
|
+ xargs /opt/Xilinx/Vivado/2018.2/bin/xsc -mt off -v 1
|
|||
|
|
Turned off multi-threading.
|
|||
|
|
Running compilation flow
|
|||
|
|
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR
|
|||
|
|
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/user.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -DXILINX_SIMULATOR
|
|||
|
|
./Testbench/user.c: In function ‘register_write_control’:
|
|||
|
|
./Testbench/user.c:37:5: warning: implicit declaration of function ‘SV_write_control’ [-Wimplicit-function-declaration]
|
|||
|
|
SV_write_control(&sv_addr, &sv_data);
|
|||
|
|
^~~~~~~~~~~~~~~~
|
|||
|
|
./Testbench/user.c: In function ‘register_read_control’:
|
|||
|
|
./Testbench/user.c:51:5: warning: implicit declaration of function ‘SV_read_control’ [-Wimplicit-function-declaration]
|
|||
|
|
SV_read_control(&sv_addr, &sv_data);
|
|||
|
|
^~~~~~~~~~~~~~~
|
|||
|
|
./Testbench/user.c: In function ‘CAM_Init’:
|
|||
|
|
./Testbench/user.c:88:76: warning: passing argument 9 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
|
|||
|
|
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
|
|||
|
|
^~~~~~~~~~~~~~
|
|||
|
|
In file included from ./Testbench/user.c:7:0:
|
|||
|
|
./Testbench/CAM.h:169:5: note: expected ‘void (*)(addr_t, uint32_t) {aka void (*)(long long unsigned int, unsigned int)}’ but argument is of type ‘void (*)(uint32_t, uint32_t) {aka void (*)(unsigned int, unsigned int)}’
|
|||
|
|
int CAM_Init_ValidateContext(
|
|||
|
|
^~~~~~~~~~~~~~~~~~~~~~~~
|
|||
|
|
./Testbench/user.c:88:92: warning: passing argument 10 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
|
|||
|
|
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
|
|||
|
|
^~~~~~~~~~~~~
|
|||
|
|
In file included from ./Testbench/user.c:7:0:
|
|||
|
|
./Testbench/CAM.h:169:5: note: expected ‘uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)}’ but argument is of type ‘uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}’
|
|||
|
|
int CAM_Init_ValidateContext(
|
|||
|
|
^~~~~~~~~~~~~~~~~~~~~~~~
|
|||
|
|
Done compilation
|
|||
|
|
Linking with command:
|
|||
|
|
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/
|
|||
|
|
|
|||
|
|
Running command : /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/
|
|||
|
|
Done linking: "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so"
|
|||
|
|
+ /opt/Xilinx/Vivado/2018.2/bin/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
|
|||
|
|
Vivado Simulator 2018.2
|
|||
|
|
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
|
|||
|
|
Multi-threading is on. Using 6 slave threads.
|
|||
|
|
Starting static elaboration
|
|||
|
|
Completed static elaboration
|
|||
|
|
Starting simulation data flow analysis
|
|||
|
|
Completed simulation data flow analysis
|
|||
|
|
Time Resolution for simulation is 1ps
|
|||
|
|
Compiling module work.S_RESETTER_line
|
|||
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Compiling module work.S_RESETTER_lookup
|
|||
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Compiling module work.S_RESETTER_control
|
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Compiling module work.TopParser_t_EngineStage_0_ErrorC...
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Compiling module work.TopParser_t_start_compute_meta_c...
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Compiling module work.TopParser_t_start_compute_meta_c...
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Compiling module work.TopParser_t_start_compute_meta_c...
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Compiling module work.TopParser_t_start_compute_meta_c...
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Compiling module work.TopParser_t_start_compute_meta_c...
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Compiling module work.TopParser_t_start_compute_meta_c...
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Compiling module work.TopParser_t_start_compute_meta_c...
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Compiling module work.TopParser_t_start_compute_meta_c...
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Compiling module work.TopParser_t_start_compute_meta_v...
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Compiling module work.TopParser_t_start_compute_meta_v...
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Compiling module work.TopParser_t_start_compute_meta_h...
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Compiling module work.TopParser_t_start_compute_hdr_et...
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Compiling module work.TopParser_t_start_compute_hdr_et...
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Compiling module work.TopParser_t_start_compute_hdr_et...
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Compiling module work.TopParser_t_start_compute_hdr_et...
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Compiling module work.TopParser_t_start_compute_TopPar...
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Compiling module work.TopParser_t_start_compute_contro...
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Compiling module work.TopParser_t_start_compute_contro...
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Compiling module work.TopParser_t_start
|
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Compiling module work.TopParser_t_reject_compute_contr...
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Compiling module work.TopParser_t_reject_compute_contr...
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Compiling module work.TopParser_t_reject
|
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Compiling module work.TopParser_t_EngineStage_0_TupleF...
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Compiling module work.TopParser_t_EngineStage_0
|
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Compiling module work.TopParser_t_EngineStage_1_ErrorC...
|
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Compiling module work.TopParser_t_EngineStage_1_Extrac...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv4_compute_hdr_ipv...
|
|||
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Compiling module work.TopParser_t_ipv4_compute_TopPars...
|
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|
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Compiling module work.TopParser_t_ipv4_compute_meta_le...
|
|||
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Compiling module work.TopParser_t_ipv4_compute_control...
|
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Compiling module work.TopParser_t_ipv4_compute_control...
|
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Compiling module work.TopParser_t_ipv4
|
|||
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Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
|
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Compiling module work.TopParser_t_ipv6_compute_hdr_ipv...
|
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|
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Compiling module work.TopParser_t_ipv6_compute_TopPars...
|
|||
|
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Compiling module work.TopParser_t_ipv6_compute_meta_le...
|
|||
|
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Compiling module work.TopParser_t_ipv6_compute_control...
|
|||
|
|
Compiling module work.TopParser_t_ipv6_compute_control...
|
|||
|
|
Compiling module work.TopParser_t_ipv6
|
|||
|
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Compiling module work.TopParser_t_arp_compute_hdr_arp_...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_hdr_arp_...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_TopParse...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_control_...
|
|||
|
|
Compiling module work.TopParser_t_arp_compute_control_...
|
|||
|
|
Compiling module work.TopParser_t_arp
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_1_TupleF...
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_1
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_2_ErrorC...
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_2_Extrac...
|
|||
|
|
Compiling module work.TopParser_t_icmp6_compute_hdr_ic...
|
|||
|
|
Compiling module work.TopParser_t_icmp6_compute_hdr_ic...
|
|||
|
|
Compiling module work.TopParser_t_icmp6_compute_hdr_ic...
|
|||
|
|
Compiling module work.TopParser_t_icmp6_compute_hdr_ic...
|
|||
|
|
Compiling module work.TopParser_t_icmp6_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_icmp6_compute_contro...
|
|||
|
|
Compiling module work.TopParser_t_icmp6_compute_contro...
|
|||
|
|
Compiling module work.TopParser_t_icmp6
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_hdr_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_TopParse...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_control_...
|
|||
|
|
Compiling module work.TopParser_t_tcp_compute_control_...
|
|||
|
|
Compiling module work.TopParser_t_tcp
|
|||
|
|
Compiling module work.TopParser_t_udp_compute_hdr_udp_...
|
|||
|
|
Compiling module work.TopParser_t_udp_compute_hdr_udp_...
|
|||
|
|
Compiling module work.TopParser_t_udp_compute_hdr_udp_...
|
|||
|
|
Compiling module work.TopParser_t_udp_compute_hdr_udp_...
|
|||
|
|
Compiling module work.TopParser_t_udp_compute_hdr_udp_...
|
|||
|
|
Compiling module work.TopParser_t_udp_compute_TopParse...
|
|||
|
|
Compiling module work.TopParser_t_udp_compute_control_...
|
|||
|
|
Compiling module work.TopParser_t_udp_compute_control_...
|
|||
|
|
Compiling module work.TopParser_t_udp
|
|||
|
|
Compiling module work.TopParser_t_icmp_compute_hdr_icm...
|
|||
|
|
Compiling module work.TopParser_t_icmp_compute_hdr_icm...
|
|||
|
|
Compiling module work.TopParser_t_icmp_compute_hdr_icm...
|
|||
|
|
Compiling module work.TopParser_t_icmp_compute_hdr_icm...
|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_icmp_compute_control...
|
|||
|
|
Compiling module work.TopParser_t_icmp_compute_control...
|
|||
|
|
Compiling module work.TopParser_t_icmp
|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_EngineStage_2
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_icmp6_neighbor_solic...
|
|||
|
|
Compiling module work.TopParser_t_icmp6_neighbor_solic...
|
|||
|
|
Compiling module work.TopParser_t_icmp6_neighbor_solic...
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_EngineStage_3
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_EngineStage_4
|
|||
|
|
Compiling module work.TopParser_t_Engine
|
|||
|
|
Compiling module work.TopParser_t
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopPipe_lvl_t_setup
|
|||
|
|
Compiling module work.TopPipe_lvl_t_EngineStage_0
|
|||
|
|
Compiling module work.TopPipe_lvl_t_Engine
|
|||
|
|
Compiling module work.TopPipe_lvl_t
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_Hash_L...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_SIZE=992,...
|
|||
|
|
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=99...
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_RamR1R...
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_Cam
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_Lookup
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_Hash_U...
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_Randmo...
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_Randmo...
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_Randmo...
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_Randmo...
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_Update
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_IntTop
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_Wrap
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t_csr
|
|||
|
|
Compiling module work.dummy_table_for_netpfga_t
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_dummy_table_for_...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_dummy_table_for_...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_dummy_table_for_...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_EngineStage_0
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_...
|
|||
|
|
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|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_...
|
|||
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Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_send_to_port_0_s...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_send_to_port_0_s...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_send_to_port_0_s...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_send_to_port_0_s...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_EngineStage_1
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_sink_compute_con...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_sink_compute_con...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_sink
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_EngineStage_2
|
|||
|
|
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|
|||
|
|
Compiling module work.TopPipe_lvl_0_t
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Erro...
|
|||
|
|
Compiling module work.TopDeparser_t_extract_headers_se...
|
|||
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|
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|
|||
|
|
Compiling module work.TopDeparser_t_extract_headers_se...
|
|||
|
|
Compiling module work.TopDeparser_t_extract_headers_se...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_0
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_1_Erro...
|
|||
|
|
Compiling module work.TopDeparser_t_act_sec_compute_co...
|
|||
|
|
Compiling module work.TopDeparser_t_act_sec_compute_co...
|
|||
|
|
Compiling module work.TopDeparser_t_act_sec
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_1
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_2_Erro...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_10_compute_co...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_10_compute__S...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_10_compute__S...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_10_compute__S...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_10_compute_co...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_10_compute_co...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_10
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_2
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Erro...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_9_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_9_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_9_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_9_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_9_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_9_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_9_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_9
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_3
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Erro...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_8
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_4
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Erro...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_7
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_5
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Erro...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_6
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_6
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Erro...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_5
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_7_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_7
|
|||
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Compiling module work.TopDeparser_t_EngineStage_8_Erro...
|
|||
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Compiling module work.TopDeparser_t_emit_4_compute_con...
|
|||
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Compiling module work.TopDeparser_t_emit_4_compute__ST...
|
|||
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Compiling module work.TopDeparser_t_emit_4_compute__ST...
|
|||
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Compiling module work.TopDeparser_t_emit_4_compute__ST...
|
|||
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Compiling module work.TopDeparser_t_emit_4_compute__ST...
|
|||
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Compiling module work.TopDeparser_t_emit_4_compute_con...
|
|||
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Compiling module work.TopDeparser_t_emit_4_compute_con...
|
|||
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Compiling module work.TopDeparser_t_emit_4
|
|||
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_8_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_8
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Erro...
|
|||
|
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Compiling module work.TopDeparser_t_emit_3_compute_con...
|
|||
|
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Compiling module work.TopDeparser_t_emit_3_compute__ST...
|
|||
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Compiling module work.TopDeparser_t_emit_3_compute__ST...
|
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Compiling module work.TopDeparser_t_emit_3_compute__ST...
|
|||
|
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Compiling module work.TopDeparser_t_emit_3_compute_con...
|
|||
|
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Compiling module work.TopDeparser_t_emit_3_compute_con...
|
|||
|
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Compiling module work.TopDeparser_t_emit_3
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
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|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_9_Edit...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_9
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Err...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_2_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_2_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_2_compute__ST...
|
|||
|
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Compiling module work.TopDeparser_t_emit_2_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_2_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_2_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_2
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_10
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Err...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_1_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_1_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_1_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_1_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_1_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_1_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_1_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_1_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_1
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_11
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Err...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_0_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_0_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_0_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_0_compute__ST...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_0_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_0_compute_con...
|
|||
|
|
Compiling module work.TopDeparser_t_emit_0
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12_Edi...
|
|||
|
|
Compiling module work.TopDeparser_t_EngineStage_12
|
|||
|
|
Compiling module work.TopDeparser_t_Engine
|
|||
|
|
Compiling module work.TopDeparser_t
|
|||
|
|
Compiling module work.xpm_cdc_sync_rst(DEST_SYNC_FF=2,...
|
|||
|
|
Compiling module work.xpm_fifo_rst(COMMON_CLOCK=0)
|
|||
|
|
Compiling module work.xpm_fifo_reg_bit
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
|
|||
|
|
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=8)
|
|||
|
|
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
|
|||
|
|
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=9)
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.S_BRIDGER_for_dummy_table_for_ne...
|
|||
|
|
Compiling module work.S_PROTOCOL_ADAPTER_INGRESS
|
|||
|
|
Compiling module work.S_PROTOCOL_ADAPTER_EGRESS
|
|||
|
|
Compiling module work.xpm_fifo_rst_default
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1...
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=2...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.S_SYNCER_for_TopParser
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7...
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7...
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
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Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=7)
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Compiling module work.glbl
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Built simulation snapshot work.SimpleSumeSwitch_tb#work.glbl
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****** Webtalk v2018.2 (64-bit)
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/xsim_webtalk.tcl -notrace
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INFO: [Common 17-186] '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Sun Jul 21 12:29:51 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html.
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INFO: [Common 17-206] Exiting Webtalk at Sun Jul 21 12:29:51 2019...
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+ /opt/Xilinx/Vivado/2018.2/bin/xsim --runall SimpleSumeSwitch_tb#work.glbl
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****** xsim v2018.2 (64-bit)
|
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
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source xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsim_script.tcl
|
|||
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# xsim {work.SimpleSumeSwitch_tb#work.glbl} -autoloadwcfg -runall
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Vivado Simulator 2018.2
|
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Time resolution is 1 ps
|
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run -all
|
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.dummy_table_for_netpfga.dummy_table_for_netpfga_t_Wrap_inst.dummy_table_for_netpfga_t_IntTop_inst.dummy_table_for_netpfga_t_Lookup_inst.dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/dummy_table_for_netpfga/dummy_table_for_netpfga_t_Wrap_inst/dummy_table_for_netpfga_t_IntTop_inst/dummy_table_for_netpfga_t_Lookup_inst/dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_678 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.dummy_table_for_netpfga.dummy_table_for_netpfga_t_Wrap_inst.dummy_table_for_netpfga_t_IntTop_inst.dummy_table_for_netpfga_t_Lookup_inst.dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/dummy_table_for_netpfga/dummy_table_for_netpfga_t_Wrap_inst/dummy_table_for_netpfga_t_IntTop_inst/dummy_table_for_netpfga_t_Lookup_inst/dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_678 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.dummy_table_for_netpfga.dummy_table_for_netpfga_t_Wrap_inst.dummy_table_for_netpfga_t_IntTop_inst.dummy_table_for_netpfga_t_Lookup_inst.dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/dummy_table_for_netpfga/dummy_table_for_netpfga_t_Wrap_inst/dummy_table_for_netpfga_t_IntTop_inst/dummy_table_for_netpfga_t_Lookup_inst/dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_678 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.dummy_table_for_netpfga.dummy_table_for_netpfga_t_Wrap_inst.dummy_table_for_netpfga_t_IntTop_inst.dummy_table_for_netpfga_t_Lookup_inst.dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/dummy_table_for_netpfga/dummy_table_for_netpfga_t_Wrap_inst/dummy_table_for_netpfga_t_IntTop_inst/dummy_table_for_netpfga_t_Lookup_inst/dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_678 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.dummy_table_for_netpfga.dummy_table_for_netpfga_t_Wrap_inst.dummy_table_for_netpfga_t_IntTop_inst.dummy_table_for_netpfga_t_Lookup_inst.dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/dummy_table_for_netpfga/dummy_table_for_netpfga_t_Wrap_inst/dummy_table_for_netpfga_t_IntTop_inst/dummy_table_for_netpfga_t_Lookup_inst/dummy_table_for_netpfga_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_678 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4843 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.s5bmz14npk0z94gxkyzk5l_27.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/s5bmz14npk0z94gxkyzk5l_27/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4936 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.gjdiceryiraqomnicoa0j5rufp0p_2642.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/gjdiceryiraqomnicoa0j5rufp0p_2642/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4966 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.djvou3m2j6cfc0c7l1f6c5i_1976.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/djvou3m2j6cfc0c7l1f6c5i_1976/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.twgh4sp06o3q9gw20mcvqodzxcn_178.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/twgh4sp06o3q9gw20mcvqodzxcn_178/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5114 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.mm31mpklp0460juck0nt6ycmpxr5j_1.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mm31mpklp0460juck0nt6ycmpxr5j_1/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4936 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.abexgpl35l8zcy0hmjmsw1m3cdi_680.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/abexgpl35l8zcy0hmjmsw1m3cdi_680/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4966 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.e899jj9x8yd221iv05_2602.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/e899jj9x8yd221iv05_2602/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5295 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.b5w6bepi8noyyst8xcra5m_1080.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/b5w6bepi8noyyst8xcra5m_1080/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5379 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.r10i77xiwhcb1w89ky_1346.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/r10i77xiwhcb1w89ky_1346/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5463 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.wmj6wa76a9u78od7rtsyh84zjcv_1097.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/wmj6wa76a9u78od7rtsyh84zjcv_1097/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.svun3qsf654iiqjv4s9yum_588.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/svun3qsf654iiqjv4s9yum_588/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5114 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.lrx70boem4x1tkqqwoxma8kx26k_1514.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lrx70boem4x1tkqqwoxma8kx26k_1514/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5715 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.qea9xcv7hk6o1jesk_46.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/qea9xcv7hk6o1jesk_46/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4936 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.j703hwddhzclqfzobpkb79qwf5ci_488.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/j703hwddhzclqfzobpkb79qwf5ci_488/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4966 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.h4lu1v786dk1m1av15_2260.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/h4lu1v786dk1m1av15_2260/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5463 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.vq5atyez4usgnofdp04t4g8_1664.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/vq5atyez4usgnofdp04t4g8_1664/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5295 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.ede4gnv1nytkfujkc2k_193.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/ede4gnv1nytkfujkc2k_193/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6068 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
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|||
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.w2mklmhjbr1ecgxu_2171.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/w2mklmhjbr1ecgxu_2171/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5379 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.k9rcgym4z3xsryzel9eezcncvu8gg3m_2315.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/k9rcgym4z3xsryzel9eezcncvu8gg3m_2315/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.x736kykk3whvcpod2isjwfqq_920.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/x736kykk3whvcpod2isjwfqq_920/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_6320 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.h9cg34o08kof6j8etj_430.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/h9cg34o08kof6j8etj_430/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5114 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.luv1iw9qdr343ujd19ffns5cqdv1k_1372.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/luv1iw9qdr343ujd19ffns5cqdv1k_1372/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5715 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.f1pqm86uah1sv21j8_97.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/f1pqm86uah1sv21j8_97/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4936 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.pjbm9u80hu6wcg6ib00uc3o_1599.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/pjbm9u80hu6wcg6ib00uc3o_1599/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4966 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.n139skedri8d4cskwqdmxvkk_701.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/n139skedri8d4cskwqdmxvkk_701/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5295 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.r8mcl5br6age31ldl6mkxprn6g11vkp_1924.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/r8mcl5br6age31ldl6mkxprn6g11vkp_1924/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5379 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.mqkoor9cs6cnw8msodmpy2lqaebetm_219.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/mqkoor9cs6cnw8msodmpy2lqaebetm_219/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5463 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.m0fvqpk7pv4ete77_2263.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/m0fvqpk7pv4ete77_2263/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.incjuv5t6k1xmbd45ancivu35_1705.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/incjuv5t6k1xmbd45ancivu35_1705/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5114 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.rxq2v7jnc74g0ove56_1060.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/rxq2v7jnc74g0ove56_1060/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5715 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.iie4wxyiz8dksexi6oddekiyu_2388.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/iie4wxyiz8dksexi6oddekiyu_2388/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_7174 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.h78qxc1eybq5jsdtip53ndhby9_379.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/h78qxc1eybq5jsdtip53ndhby9_379/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4966 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.os7lvu34sd201vrunt54cgk3na_1430.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/os7lvu34sd201vrunt54cgk3na_1430/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5463 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.ekglq5r9etiuye0is7oqc8wc7d7_495.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/ekglq5r9etiuye0is7oqc8wc7d7_495/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_5030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/xpm_memory.sv
|
|||
|
|
[SW] CAM_Init() - start
|
|||
|
|
[SW] CAM_Init() - done
|
|||
|
|
[SW] CAM_EnableDevice() - start
|
|||
|
|
SV_write_control()- start
|
|||
|
|
SV_write_control()- done
|
|||
|
|
SV_read_control()- start
|
|||
|
|
SV_read_control()- done
|
|||
|
|
SV_write_control()- start
|
|||
|
|
SV_write_control()- done
|
|||
|
|
[SW] CAM_EnableDevice() - done
|
|||
|
|
[2260762] INFO: finished packet stimulus file
|
|||
|
|
[3728508] INFO: packet 1 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
|
|||
|
|
[3728508] INFO: packet 1 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
|
|||
|
|
[3731840] INFO: packet 1 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
|
|||
|
|
[7067172] INFO: stopping simulation after 1000 idle cycles
|
|||
|
|
[7067172] INFO: all expected data successfully received
|
|||
|
|
[7067172] INFO: TEST PASSED
|
|||
|
|
$finish called at time : 7067172 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" Line 207
|
|||
|
|
exit
|
|||
|
|
INFO: [Common 17-206] Exiting xsim at Sun Jul 21 12:30:03 2019...
|
|||
|
|
+ grep ^expected LOG
|
|||
|
|
+ sed -e s/.*= <// -e s/.*= (//
|
|||
|
|
+ expected_line=
|
|||
|
|
+ grep ^actual LOG
|
|||
|
|
+ sed -e s/.*= <// -e s/.*= (//
|
|||
|
|
+ actual_line=
|
|||
|
|
+ [ != ]
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|||
|
|
+ make config_writes
|
|||
|
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata
|
|||
|
|
orig dic: OrderedDict([(0, ('00000020', '00000001')), (1, ('00000020', '00000000'))])
|
|||
|
|
new dic: OrderedDict()
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|||
|
|
+ make uninstall_sdnet
|
|||
|
|
rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip
|
|||
|
|
+ make install_sdnet
|
|||
|
|
rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip
|
|||
|
|
cp -r nf_sume_sdnet_ip /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/
|
|||
|
|
mkdir /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/hdl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper/
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/tcl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/Makefile /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
|
|||
|
|
make -C /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
|
|||
|
|
rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip
|
|||
|
|
vivado -mode batch -source nf_sume_sdnet.tcl
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source nf_sume_sdnet.tcl
|
|||
|
|
# set design nf_sume_sdnet
|
|||
|
|
# set top nf_sume_sdnet
|
|||
|
|
# set device xc7vx690t-3-ffg1761
|
|||
|
|
# set proj_dir ./ip_proj
|
|||
|
|
# set ip_version 1.00
|
|||
|
|
# set lib_name NetFPGA
|
|||
|
|
# create_project -name ${design} -force -dir "./${proj_dir}" -part ${device}
|
|||
|
|
# set_property source_mgmt_mode All [current_project]
|
|||
|
|
# set_property top ${top} [current_fileset]
|
|||
|
|
# set_property ip_repo_paths $::env(SUME_FOLDER)/lib/hw/ [current_fileset]
|
|||
|
|
# update_ip_catalog
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
|
|||
|
|
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
|
|||
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
|||
|
|
# puts "nf_sume_sdnet"
|
|||
|
|
nf_sume_sdnet
|
|||
|
|
# read_verilog "./wrapper/sume_to_sdnet.v"
|
|||
|
|
# read_verilog "./wrapper/nf_sume_sdnet.v"
|
|||
|
|
# read_verilog "./wrapper/changeEndian.v"
|
|||
|
|
# add_files -scan_for_includes ./SimpleSumeSwitch/
|
|||
|
|
# import_files -force
|
|||
|
|
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
|
|||
|
|
# update_compile_order -fileset sources_1
|
|||
|
|
update_compile_order: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1252.852 ; gain = 4.000 ; free physical = 9758 ; free virtual = 15444
|
|||
|
|
# update_compile_order -fileset sim_1
|
|||
|
|
update_compile_order: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1254.852 ; gain = 2.000 ; free physical = 9758 ; free virtual = 15443
|
|||
|
|
# ipx::package_project
|
|||
|
|
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/wrapper/changeEndian.v'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.h'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/dpi.h'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM.h'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM_INST0.h'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request.vp'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv'.
|
|||
|
|
INFO: [IP_Flow 19-5169] Module 'nf_sume_sdnet' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'axis_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'S_AXI'.
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'.
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'S_AXI_ARESETN'.
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'axis_resetn'.
|
|||
|
|
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
|||
|
|
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
|||
|
|
ipx::package_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1314.492 ; gain = 32.000 ; free physical = 9741 ; free virtual = 15427
|
|||
|
|
# set_property name ${design} [ipx::current_core]
|
|||
|
|
# set_property library ${lib_name} [ipx::current_core]
|
|||
|
|
# set_property vendor_display_name {NetFPGA} [ipx::current_core]
|
|||
|
|
# set_property company_url {http://www.netfpga.org} [ipx::current_core]
|
|||
|
|
# set_property vendor {NetFPGA} [ipx::current_core]
|
|||
|
|
# set_property supported_families {{virtex7} {Production}} [ipx::current_core]
|
|||
|
|
# set_property taxonomy {{/NetFPGA/Generic}} [ipx::current_core]
|
|||
|
|
# set_property version ${ip_version} [ipx::current_core]
|
|||
|
|
# set_property display_name ${design} [ipx::current_core]
|
|||
|
|
# set_property description ${design} [ipx::current_core]
|
|||
|
|
# ipx::add_user_parameter {C_M_AXIS_DATA_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_M_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {256} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {C_S_AXIS_DATA_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_S_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {256} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {C_M_AXIS_TUSER_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_M_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {128} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {C_S_AXIS_TUSER_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_S_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {128} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {C_S_AXI_DATA_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_S_AXI_DATA_WIDTH} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {32} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {C_S_AXI_ADDR_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_S_AXI_ADDR_WIDTH} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {12} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {SDNET_ADDR_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {SDNET_ADDR_WIDTH} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {11} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]]
|
|||
|
|
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]]
|
|||
|
|
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]]
|
|||
|
|
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]]
|
|||
|
|
# update_ip_catalog -rebuild
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
|
|||
|
|
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
|
|||
|
|
# ipx::infer_user_parameters [ipx::current_core]
|
|||
|
|
# ipx::check_integrity [ipx::current_core]
|
|||
|
|
INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
|
|||
|
|
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
|||
|
|
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
|||
|
|
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
|
|||
|
|
# ipx::save_core [ipx::current_core]
|
|||
|
|
# update_ip_catalog
|
|||
|
|
# close_project
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 21 12:30:35 2019...
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default
|
|||
|
|
+ make
|
|||
|
|
rm -f config_writes.py*
|
|||
|
|
rm -f *.pyc
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA
|
|||
|
|
+ ./tools/scripts/nf_test.py sim --major switch --minor default
|
|||
|
|
make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
|
|||
|
|
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl
|
|||
|
|
# set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
# set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
# set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
# set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
# set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
# set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
# set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
# set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
# set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
# set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
# set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
# set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
# set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
# set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
# set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
# set M00_BASEADDR 0x44000000
|
|||
|
|
# set M00_HIGHADDR 0x44000FFF
|
|||
|
|
# set M00_SIZEADDR 0x1000
|
|||
|
|
# set M01_BASEADDR 0x44010000
|
|||
|
|
# set M01_HIGHADDR 0x44010FFF
|
|||
|
|
# set M01_SIZEADDR 0x1000
|
|||
|
|
# set M02_BASEADDR 0x44020000
|
|||
|
|
# set M02_HIGHADDR 0x44020FFF
|
|||
|
|
# set M02_SIZEADDR 0x1000
|
|||
|
|
# set M03_BASEADDR 0x44030000
|
|||
|
|
# set M03_HIGHADDR 0x44030FFF
|
|||
|
|
# set M03_SIZEADDR 0x1000
|
|||
|
|
# set M04_BASEADDR 0x44040000
|
|||
|
|
# set M04_HIGHADDR 0x44040FFF
|
|||
|
|
# set M04_SIZEADDR 0x1000
|
|||
|
|
# set M05_BASEADDR 0x44050000
|
|||
|
|
# set M05_HIGHADDR 0x44050FFF
|
|||
|
|
# set M05_SIZEADDR 0x1000
|
|||
|
|
# set M06_BASEADDR 0x44060000
|
|||
|
|
# set M06_HIGHADDR 0x44060FFF
|
|||
|
|
# set M06_SIZEADDR 0x1000
|
|||
|
|
# set M07_BASEADDR 0x44070000
|
|||
|
|
# set M07_HIGHADDR 0x44070FFF
|
|||
|
|
# set M07_SIZEADDR 0x1000
|
|||
|
|
# set M08_BASEADDR 0x44080000
|
|||
|
|
# set M08_HIGHADDR 0x44080FFF
|
|||
|
|
# set M08_SIZEADDR 0x1000
|
|||
|
|
# set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
# set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
# set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
# set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
# set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
# set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
# set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
# set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
# set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
# set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
# set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
# set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
# set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
# set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
# set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
# set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
# set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
# set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
# set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
# set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
# set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
# set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
# set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
# set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
# set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
# set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
# set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 21 12:30:41 2019...
|
|||
|
|
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl
|
|||
|
|
# set DEF_LIST {
|
|||
|
|
# {MICROBLAZE_AXI_IIC 0 0 ""} \
|
|||
|
|
# {MICROBLAZE_UARTLITE 0 0 ""} \
|
|||
|
|
# {MICROBLAZE_DLMB_BRAM 0 0 ""} \
|
|||
|
|
# {MICROBLAZE_ILMB_BRAM 0 0 ""} \
|
|||
|
|
# {MICROBLAZE_AXI_INTC 0 0 ""} \
|
|||
|
|
# {INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \
|
|||
|
|
# {OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \
|
|||
|
|
# {OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \
|
|||
|
|
# {NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \
|
|||
|
|
# {NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
# {NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
# {NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
# {NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \
|
|||
|
|
#
|
|||
|
|
#
|
|||
|
|
# }
|
|||
|
|
# set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/
|
|||
|
|
# set target_file $target_path/sume_register_defines.h
|
|||
|
|
# proc write_header { target_file } {
|
|||
|
|
#
|
|||
|
|
# # creat a blank header file
|
|||
|
|
# # do a fresh rewrite in case the file already exits
|
|||
|
|
# file delete -force $target_file
|
|||
|
|
# open $target_file "w"
|
|||
|
|
# set h_file [open $target_file "w"]
|
|||
|
|
#
|
|||
|
|
#
|
|||
|
|
# puts $h_file "//-"
|
|||
|
|
# puts $h_file "// Copyright (c) 2015 University of Cambridge"
|
|||
|
|
# puts $h_file "// All rights reserved."
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory "
|
|||
|
|
# puts $h_file "// under National Science Foundation under Grant No. CNS-0855268,"
|
|||
|
|
# puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and"
|
|||
|
|
# puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), "
|
|||
|
|
# puts $h_file "// as part of the DARPA MRC research programme."
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// @NETFPGA_LICENSE_HEADER_START@"
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor"
|
|||
|
|
# puts $h_file "// license agreements. See the NOTICE file distributed with this work for"
|
|||
|
|
# puts $h_file "// additional information regarding copyright ownership. NetFPGA licenses this"
|
|||
|
|
# puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the"
|
|||
|
|
# puts $h_file "// \"License\"); you may not use this file except in compliance with the"
|
|||
|
|
# puts $h_file "// License. You may obtain a copy of the License at:"
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// http://www.netfpga-cic.org"
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed"
|
|||
|
|
# puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR"
|
|||
|
|
# puts $h_file "// CONDITIONS OF ANY KIND, either express or implied. See the License for the"
|
|||
|
|
# puts $h_file "// specific language governing permissions and limitations under the License."
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// @NETFPGA_LICENSE_HEADER_END@"
|
|||
|
|
# puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
|
|||
|
|
# puts $h_file "// This is an automatically generated header definitions file"
|
|||
|
|
# puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
|
|||
|
|
# puts $h_file ""
|
|||
|
|
#
|
|||
|
|
# close $h_file
|
|||
|
|
#
|
|||
|
|
# };
|
|||
|
|
# proc write_core {target_file prefix id has_registers lib_name} {
|
|||
|
|
#
|
|||
|
|
#
|
|||
|
|
# set h_file [open $target_file "a"]
|
|||
|
|
#
|
|||
|
|
# #First, read the memory map information from the reference_project defines file
|
|||
|
|
# source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
|
|||
|
|
#
|
|||
|
|
#
|
|||
|
|
# set baseaddr [set $prefix\_BASEADDR]
|
|||
|
|
# set highaddr [set $prefix\_HIGHADDR]
|
|||
|
|
# set sizeaddr [set $prefix\_SIZEADDR]
|
|||
|
|
#
|
|||
|
|
# puts $h_file "//######################################################"
|
|||
|
|
# puts $h_file "//# Definitions for $prefix"
|
|||
|
|
# puts $h_file "//######################################################"
|
|||
|
|
#
|
|||
|
|
# puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr"
|
|||
|
|
# puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr"
|
|||
|
|
# puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr"
|
|||
|
|
# puts $h_file ""
|
|||
|
|
#
|
|||
|
|
# #Second, read the registers information from the library defines file
|
|||
|
|
# if $has_registers {
|
|||
|
|
# set lib_path "$public_repo_dir/std/cores/$lib_name"
|
|||
|
|
# set regs_h_define_file $lib_path
|
|||
|
|
# set regs_h_define_file_read [open $regs_h_define_file r]
|
|||
|
|
# set regs_h_define_file_data [read $regs_h_define_file_read]
|
|||
|
|
# close $regs_h_define_file_read
|
|||
|
|
# set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"]
|
|||
|
|
#
|
|||
|
|
# foreach read_line $regs_h_define_file_data_line {
|
|||
|
|
# if {[regexp "#define" $read_line]} {
|
|||
|
|
# puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]"
|
|||
|
|
# }
|
|||
|
|
# }
|
|||
|
|
# }
|
|||
|
|
# puts $h_file ""
|
|||
|
|
# close $h_file
|
|||
|
|
# };
|
|||
|
|
# write_header $target_file
|
|||
|
|
# foreach lib_item $DEF_LIST {
|
|||
|
|
# write_core $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3]
|
|||
|
|
# }
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 21 12:30:47 2019...
|
|||
|
|
cd ../sw/embedded/src && cp /home/nico/projects/P4-NetFPGA/tools/scripts/xparam2regdefines.py . && python xparam2regdefines.py
|
|||
|
|
cd ../sw/embedded/src && rm -f xparam2regdefines.py && mv reg_defines.h ../
|
|||
|
|
cd ../sw/embedded && cp /home/nico/projects/P4-NetFPGA/tools/scripts/python_parser.py . && python python_parser.py
|
|||
|
|
cd ../sw/embedded && rm -f python_parser.py && mv reg_defines.py ../../test/reg_defines_simple_sume_switch.py
|
|||
|
|
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
|
|||
|
|
make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
|
|||
|
|
rm -rf proj_* vivado*.* *.*~ .Xil* /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/
|
|||
|
|
rm -rf *[0-9]_{stim,expected,log}.axi
|
|||
|
|
rm -f *.axi
|
|||
|
|
rm -f portconfig.sim
|
|||
|
|
rm -f seed
|
|||
|
|
rm -f *.log
|
|||
|
|
rm -f ../test/Makefile
|
|||
|
|
rm -rf ../test/*.log
|
|||
|
|
rm -rf ../test/*.axi
|
|||
|
|
rm -rf ../test/seed
|
|||
|
|
rm -rf ../test/*.sim
|
|||
|
|
rm -rf ../test/proj_*
|
|||
|
|
rm -rf ../test/ip_repo
|
|||
|
|
rm -f ../test/vivado*.*
|
|||
|
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.py
|
|||
|
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.pyc
|
|||
|
|
rm -f ../hw/create_ip/id_rom16x32.coe
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
|
|||
|
|
echo 16028002 >> rom_data.txt
|
|||
|
|
echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt
|
|||
|
|
grep: ../../../RELEASE_NOTES: No such file or directory
|
|||
|
|
echo 00000204 >> rom_data.txt
|
|||
|
|
echo 0000FFFF >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py
|
|||
|
|
16
|
|||
|
|
|
|||
|
|
mv -f id_rom16x32.coe ../hw/create_ip/
|
|||
|
|
mv -f rom_data.txt ../hw/create_ip/
|
|||
|
|
cp -f /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_defines_simple_sume_switch.py /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/reg_defines_simple_sume_switch.py
|
|||
|
|
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl -tclargs sim_switch_default
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl
|
|||
|
|
# set design $::env(NF_PROJECT_NAME)
|
|||
|
|
# set top top_sim
|
|||
|
|
# set sim_top top_tb
|
|||
|
|
# set device xc7vx690t-3-ffg1761
|
|||
|
|
# set proj_dir ./project
|
|||
|
|
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
|
|||
|
|
# set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/
|
|||
|
|
# set repo_dir ./ip_repo
|
|||
|
|
# set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc
|
|||
|
|
# set project_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_general.xdc
|
|||
|
|
# set nf_10g_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_10g.xdc
|
|||
|
|
# set test_name [lindex $argv 0]
|
|||
|
|
# source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
# create_project -name ${design} -force -dir "$::env(NF_DESIGN_DIR)/hw/${proj_dir}" -part ${device}
|
|||
|
|
# set_property source_mgmt_mode DisplayOnly [current_project]
|
|||
|
|
# set_property top ${top} [current_fileset]
|
|||
|
|
# puts "Creating User Datapath reference project"
|
|||
|
|
Creating User Datapath reference project
|
|||
|
|
# create_fileset -constrset -quiet constraints
|
|||
|
|
# file copy ${public_repo_dir}/ ${repo_dir}
|
|||
|
|
# set_property ip_repo_paths ${repo_dir} [current_fileset]
|
|||
|
|
# add_files -fileset constraints -norecurse ${bit_settings}
|
|||
|
|
# add_files -fileset constraints -norecurse ${project_constraints}
|
|||
|
|
# add_files -fileset constraints -norecurse ${nf_10g_constraints}
|
|||
|
|
# set_property is_enabled true [get_files ${project_constraints}]
|
|||
|
|
# set_property is_enabled true [get_files ${bit_settings}]
|
|||
|
|
# set_property is_enabled true [get_files ${project_constraints}]
|
|||
|
|
# update_ip_catalog
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/ip_repo'.
|
|||
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
|||
|
|
# create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci]
|
|||
|
|
# reset_target all [get_ips nf_sume_sdnet_ip]
|
|||
|
|
# generate_target all [get_ips nf_sume_sdnet_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
# create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip
|
|||
|
|
# set_property -dict [list CONFIG.C_BASEADDR $INPUT_ARBITER_BASEADDR] [get_ips input_arbiter_ip]
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci]
|
|||
|
|
# reset_target all [get_ips input_arbiter_ip]
|
|||
|
|
# generate_target all [get_ips input_arbiter_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'input_arbiter_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'input_arbiter_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'input_arbiter_ip'...
|
|||
|
|
# create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip
|
|||
|
|
# set_property -dict [list CONFIG.C_BASEADDR $OUTPUT_QUEUES_BASEADDR] [get_ips sss_output_queues_ip]
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci]
|
|||
|
|
# reset_target all [get_ips sss_output_queues_ip]
|
|||
|
|
# generate_target all [get_ips sss_output_queues_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'sss_output_queues_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'sss_output_queues_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'sss_output_queues_ip'...
|
|||
|
|
# create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip
|
|||
|
|
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
|
|||
|
|
create_ip: Time (s): cpu = 00:00:22 ; elapsed = 00:00:59 . Memory (MB): peak = 1690.250 ; gain = 390.395 ; free physical = 9703 ; free virtual = 15099
|
|||
|
|
# set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {1024} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip]
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files identifier_ip.xci]
|
|||
|
|
# reset_target all [get_ips identifier_ip]
|
|||
|
|
# generate_target all [get_ips identifier_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'identifier_ip'...
|
|||
|
|
# create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip
|
|||
|
|
# set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip]
|
|||
|
|
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '5.000' to '5.0' has been ignored for IP 'clk_wiz_ip'
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci]
|
|||
|
|
# reset_target all [get_ips clk_wiz_ip]
|
|||
|
|
# generate_target all [get_ips clk_wiz_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_ip'...
|
|||
|
|
# create_ip -name barrier -vendor NetFPGA -library NetFPGA -module_name barrier_ip
|
|||
|
|
# reset_target all [get_ips barrier_ip]
|
|||
|
|
# generate_target all [get_ips barrier_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'barrier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'barrier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'barrier_ip'...
|
|||
|
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip0
|
|||
|
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_0_log.axi] [get_ips axis_sim_record_ip0]
|
|||
|
|
# reset_target all [get_ips axis_sim_record_ip0]
|
|||
|
|
# generate_target all [get_ips axis_sim_record_ip0]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip0'...
|
|||
|
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip1
|
|||
|
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_1_log.axi] [get_ips axis_sim_record_ip1]
|
|||
|
|
# reset_target all [get_ips axis_sim_record_ip1]
|
|||
|
|
# generate_target all [get_ips axis_sim_record_ip1]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip1'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip1'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip1'...
|
|||
|
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip2
|
|||
|
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_2_log.axi] [get_ips axis_sim_record_ip2]
|
|||
|
|
# reset_target all [get_ips axis_sim_record_ip2]
|
|||
|
|
# generate_target all [get_ips axis_sim_record_ip2]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip2'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip2'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip2'...
|
|||
|
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip3
|
|||
|
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_3_log.axi] [get_ips axis_sim_record_ip3]
|
|||
|
|
# reset_target all [get_ips axis_sim_record_ip3]
|
|||
|
|
# generate_target all [get_ips axis_sim_record_ip3]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip3'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip3'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip3'...
|
|||
|
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip4
|
|||
|
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/dma_0_log.axi] [get_ips axis_sim_record_ip4]
|
|||
|
|
# reset_target all [get_ips axis_sim_record_ip4]
|
|||
|
|
# generate_target all [get_ips axis_sim_record_ip4]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip4'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip4'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip4'...
|
|||
|
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip0
|
|||
|
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_0_stim.axi] [get_ips axis_sim_stim_ip0]
|
|||
|
|
# generate_target all [get_ips axis_sim_stim_ip0]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip0'...
|
|||
|
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip1
|
|||
|
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_1_stim.axi] [get_ips axis_sim_stim_ip1]
|
|||
|
|
# generate_target all [get_ips axis_sim_stim_ip1]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip1'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip1'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip1'...
|
|||
|
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip2
|
|||
|
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_2_stim.axi] [get_ips axis_sim_stim_ip2]
|
|||
|
|
# generate_target all [get_ips axis_sim_stim_ip2]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip2'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip2'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip2'...
|
|||
|
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip3
|
|||
|
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_3_stim.axi] [get_ips axis_sim_stim_ip3]
|
|||
|
|
# generate_target all [get_ips axis_sim_stim_ip3]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip3'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip3'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip3'...
|
|||
|
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip4
|
|||
|
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/dma_0_stim.axi] [get_ips axis_sim_stim_ip4]
|
|||
|
|
# generate_target all [get_ips axis_sim_stim_ip4]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip4'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip4'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip4'...
|
|||
|
|
# create_ip -name axi_sim_transactor -vendor NetFPGA -library NetFPGA -module_name axi_sim_transactor_ip
|
|||
|
|
# set_property -dict [list CONFIG.STIM_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.axi CONFIG.EXPECT_FILE $::env(NF_DESIGN_DIR)/test/reg_expect.axi CONFIG.LOG_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.log] [get_ips axi_sim_transactor_ip]
|
|||
|
|
# reset_target all [get_ips axi_sim_transactor_ip]
|
|||
|
|
# generate_target all [get_ips axi_sim_transactor_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_sim_transactor_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_sim_transactor_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_sim_transactor_ip'...
|
|||
|
|
# update_ip_catalog
|
|||
|
|
# source $::env(NF_DESIGN_DIR)/hw/tcl/control_sub_sim.tcl
|
|||
|
|
## set scripts_vivado_version 2018.2
|
|||
|
|
## set current_vivado_version [version -short]
|
|||
|
|
## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
|||
|
|
## puts ""
|
|||
|
|
## puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
|
|||
|
|
##
|
|||
|
|
## return 1
|
|||
|
|
## }
|
|||
|
|
## set design_name control_sub
|
|||
|
|
## if { [get_projects -quiet] eq "" } {
|
|||
|
|
## puts "ERROR: Please open or create a project!"
|
|||
|
|
## return 1
|
|||
|
|
## }
|
|||
|
|
## set errMsg ""
|
|||
|
|
## set nRet 0
|
|||
|
|
## set cur_design [current_bd_design -quiet]
|
|||
|
|
## set list_cells [get_bd_cells -quiet]
|
|||
|
|
## if { ${design_name} eq "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 1) Design_name not set
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
|
|||
|
|
## set nRet 1
|
|||
|
|
##
|
|||
|
|
## } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 2): Current design opened AND is empty AND names same.
|
|||
|
|
## # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
|||
|
|
## # 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
|||
|
|
##
|
|||
|
|
## if { $cur_design ne $design_name } {
|
|||
|
|
## puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
|||
|
|
## set design_name [get_property NAME $cur_design]
|
|||
|
|
## }
|
|||
|
|
## puts "INFO: Constructing design in IPI design <$cur_design>..."
|
|||
|
|
##
|
|||
|
|
## } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 5) Current design opened AND has components AND same names.
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
|||
|
|
## set nRet 1
|
|||
|
|
## } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 6) Current opened design, has components, but diff names, design_name exists in project.
|
|||
|
|
## # 7) No opened design, design_name exists in project.
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
|||
|
|
## set nRet 2
|
|||
|
|
##
|
|||
|
|
## } else {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 8) No opened design, design_name not in project.
|
|||
|
|
## # 9) Current opened design, has components, but diff names, design_name not in project.
|
|||
|
|
##
|
|||
|
|
## puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
|
|||
|
|
##
|
|||
|
|
## create_bd_design $design_name
|
|||
|
|
##
|
|||
|
|
## puts "INFO: Making design <$design_name> as current_bd_design."
|
|||
|
|
## current_bd_design $design_name
|
|||
|
|
##
|
|||
|
|
## }
|
|||
|
|
INFO: Currently there is no design <control_sub> in project, so creating one...
|
|||
|
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
|||
|
|
INFO: Making design <control_sub> as current_bd_design.
|
|||
|
|
## puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
|
|||
|
|
INFO: Currently the variable <design_name> is equal to "control_sub".
|
|||
|
|
## if { $nRet != 0 } {
|
|||
|
|
## puts $errMsg
|
|||
|
|
## return $nRet
|
|||
|
|
## }
|
|||
|
|
## proc create_root_design { parentCell } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" } {
|
|||
|
|
## set parentCell [get_bd_cells /]
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create interface ports
|
|||
|
|
## set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI
|
|||
|
|
## set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M01_AXI
|
|||
|
|
## set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M02_AXI
|
|||
|
|
## set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M03_AXI
|
|||
|
|
## set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M04_AXI
|
|||
|
|
## set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M05_AXI
|
|||
|
|
## set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M06_AXI
|
|||
|
|
## set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M07_AXI
|
|||
|
|
## set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.CLK_DOMAIN {} CONFIG.DATA_WIDTH {32} CONFIG.FREQ_HZ {100000000} CONFIG.ID_WIDTH {0} CONFIG.MAX_BURST_LENGTH {256} CONFIG.NUM_READ_OUTSTANDING {2} CONFIG.NUM_WRITE_OUTSTANDING {2} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0} ] $S00_AXI
|
|||
|
|
##
|
|||
|
|
## # Create ports
|
|||
|
|
## set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ]
|
|||
|
|
## set axi_lite_areset [ create_bd_port -dir I -type rst axi_lite_areset ]
|
|||
|
|
## set core_clk [ create_bd_port -dir I -type clk core_clk ]
|
|||
|
|
## set_property -dict [ list CONFIG.FREQ_HZ {200000000} ] $core_clk
|
|||
|
|
## set core_resetn [ create_bd_port -dir I -type rst core_resetn ]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create instance: axi_interconnect_0, and set properties
|
|||
|
|
## set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
|
|||
|
|
## set_property -dict [ list CONFIG.NUM_MI {8} CONFIG.TRANSLATION_MODE {0} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Add AXI clock converter
|
|||
|
|
## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0
|
|||
|
|
## connect_bd_intf_net [get_bd_intf_ports S00_AXI] [get_bd_intf_pins axi_clock_converter_0/S_AXI]
|
|||
|
|
## connect_bd_intf_net [get_bd_intf_pins axi_clock_converter_0/M_AXI] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI]
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI]
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk] [get_bd_pins axi_clock_converter_0/s_axi_aclk]
|
|||
|
|
## connect_bd_net -net core_clk_1 [get_bd_ports core_clk] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK]
|
|||
|
|
## connect_bd_net -net axi_lite_areset_1 [get_bd_ports axi_lite_areset] [get_bd_pins axi_clock_converter_0/s_axi_aresetn]
|
|||
|
|
## connect_bd_net -net core_resetn_1 [get_bd_ports core_resetn] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN]
|
|||
|
|
##
|
|||
|
|
## # Create address segments
|
|||
|
|
## source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
## assign_bd_address [get_bd_addr_segs {M00_AXI/Reg }]
|
|||
|
|
## set_property offset $M00_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}]
|
|||
|
|
## set_property range $M00_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}]
|
|||
|
|
##
|
|||
|
|
## assign_bd_address [get_bd_addr_segs {M01_AXI/Reg }]
|
|||
|
|
## set_property offset $M01_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}]
|
|||
|
|
## set_property range $M01_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## assign_bd_address [get_bd_addr_segs {M02_AXI/Reg }]
|
|||
|
|
## set_property offset $M02_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}]
|
|||
|
|
## set_property range $M02_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}]
|
|||
|
|
##
|
|||
|
|
## assign_bd_address [get_bd_addr_segs {M03_AXI/Reg }]
|
|||
|
|
## set_property offset $M03_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}]
|
|||
|
|
## set_property range $M03_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
##
|
|||
|
|
## save_bd_design
|
|||
|
|
## }
|
|||
|
|
## create_root_design ""
|
|||
|
|
CRITICAL WARNING: [BD 41-737] Cannot set the parameter TRANSLATION_MODE on /axi_interconnect_0. It is read-only.
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
</M00_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
|
|||
|
|
</M01_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
|
|||
|
|
</M02_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
|
|||
|
|
</M03_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
|
|||
|
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
|||
|
|
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/axi_clocking.v"
|
|||
|
|
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/nf_datapath.v"
|
|||
|
|
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_sim.v"
|
|||
|
|
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_tb.v"
|
|||
|
|
# update_compile_order -fileset sources_1
|
|||
|
|
# update_compile_order -fileset sim_1
|
|||
|
|
# set_property top ${sim_top} [get_filesets sim_1]
|
|||
|
|
# set_property include_dirs ${proj_dir} [get_filesets sim_1]
|
|||
|
|
# set_property simulator_language Mixed [current_project]
|
|||
|
|
# set_property verilog_define { {SIMULATION=1} } [get_filesets sim_1]
|
|||
|
|
# set_property -name xsim.more_options -value {-testplusarg TESTNAME=basic_test} -objects [get_filesets sim_1]
|
|||
|
|
# set_property runtime {} [get_filesets sim_1]
|
|||
|
|
# set_property target_simulator xsim [current_project]
|
|||
|
|
# set_property compxlib.xsim_compiled_library_dir {} [current_project]
|
|||
|
|
# set_property top_lib xil_defaultlib [get_filesets sim_1]
|
|||
|
|
# update_compile_order -fileset sim_1
|
|||
|
|
update_compile_order: Time (s): cpu = 00:00:21 ; elapsed = 00:00:11 . Memory (MB): peak = 2029.406 ; gain = 8.012 ; free physical = 9571 ; free virtual = 14987
|
|||
|
|
loading libsume..
|
|||
|
|
Traceback (most recent call last):
|
|||
|
|
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py", line 42, in <module>
|
|||
|
|
import config_writes
|
|||
|
|
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py", line 7
|
|||
|
|
|
|||
|
|
^
|
|||
|
|
IndentationError: expected an indented block
|
|||
|
|
while executing
|
|||
|
|
"exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py"
|
|||
|
|
invoked from within
|
|||
|
|
"set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]"
|
|||
|
|
(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 177)
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 21 12:32:19 2019...
|
|||
|
|
Makefile:120: recipe for target 'sim' failed
|
|||
|
|
make: *** [sim] Error 1
|
|||
|
|
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_stim.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_expected.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_stim.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_expected.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_stim.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_expected.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_stim.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_expected.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_expected.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.log': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_expect.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.axi': No such file or directory
|
|||
|
|
NetFPGA environment:
|
|||
|
|
Root dir: /home/nico/projects/P4-NetFPGA
|
|||
|
|
Project name: simple_sume_switch
|
|||
|
|
Project dir: /tmp/nico/test/simple_sume_switch
|
|||
|
|
Work dir: /tmp/nico
|
|||
|
|
512
|
|||
|
|
=== Work directory is /tmp/nico/test/simple_sume_switch
|
|||
|
|
=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
|
|||
|
|
=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
|
|||
|
|
+ [ = no ]
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch
|
|||
|
|
+ make
|
|||
|
|
make -C hw distclean
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
rm -rf proj_* vivado*.* *.*~ .Xil* /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/
|
|||
|
|
rm -rf *[0-9]_{stim,expected,log}.axi
|
|||
|
|
rm -f *.axi
|
|||
|
|
rm -f portconfig.sim
|
|||
|
|
rm -f seed
|
|||
|
|
rm -f *.log
|
|||
|
|
rm -f ../test/Makefile
|
|||
|
|
rm -rf ../test/*.log
|
|||
|
|
rm -rf ../test/*.axi
|
|||
|
|
rm -rf ../test/seed
|
|||
|
|
rm -rf ../test/*.sim
|
|||
|
|
rm -rf ../test/proj_*
|
|||
|
|
rm -rf ../test/ip_repo
|
|||
|
|
rm -f ../test/vivado*.*
|
|||
|
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.py
|
|||
|
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.pyc
|
|||
|
|
rm -rfv project;\
|
|||
|
|
rm -rfv ../sw/embedded/project;\
|
|||
|
|
rm -rfv vivado*;\
|
|||
|
|
rm -rfv *.log;\
|
|||
|
|
rm -rfv .Xil;\
|
|||
|
|
rm -rfv ..rej;\
|
|||
|
|
rm -rfv .srcs;\
|
|||
|
|
rm -rfv webtalk*;\
|
|||
|
|
rm -rfv *.*~;\
|
|||
|
|
rm -rfv ip_repo;\
|
|||
|
|
rm -rfv ip_proj;\
|
|||
|
|
rm -rfv std;\
|
|||
|
|
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
make -C sw/embedded/ distclean
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
|
|||
|
|
rm -rf `find . -name "SDK_Workspace"`
|
|||
|
|
rm -rf `find . -name "*.log"`
|
|||
|
|
rm -rf `find . -name "*.jou"`
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
|
|||
|
|
rm -rfv vivado*;\
|
|||
|
|
|
|||
|
|
make -C hw project
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
rm -f ../hw/create_ip/id_rom16x32.coe
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
|
|||
|
|
echo 16028002 >> rom_data.txt
|
|||
|
|
echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt
|
|||
|
|
grep: ../../../RELEASE_NOTES: No such file or directory
|
|||
|
|
echo 00000204 >> rom_data.txt
|
|||
|
|
echo 0000FFFF >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py
|
|||
|
|
16
|
|||
|
|
|
|||
|
|
mv -f id_rom16x32.coe ../hw/create_ip/
|
|||
|
|
mv -f rom_data.txt ../hw/create_ip/
|
|||
|
|
echo "Create reference project under folder /project";\
|
|||
|
|
if test -d project/; then\
|
|||
|
|
echo "Project already exists"; \
|
|||
|
|
else \
|
|||
|
|
vivado -mode batch -source tcl/simple_sume_switch.tcl;\
|
|||
|
|
if [ -f patch/simple_sume_switch.patch ]; then\
|
|||
|
|
patch -p1 < patch/simple_sume_switch.patch;\
|
|||
|
|
fi;\
|
|||
|
|
fi;\
|
|||
|
|
|
|||
|
|
Create reference project under folder /project
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source tcl/simple_sume_switch.tcl
|
|||
|
|
# set design $::env(NF_PROJECT_NAME)
|
|||
|
|
# set top top
|
|||
|
|
# set device xc7vx690t-3-ffg1761
|
|||
|
|
# set proj_dir ./project
|
|||
|
|
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
|
|||
|
|
# set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/
|
|||
|
|
# set repo_dir ./ip_repo
|
|||
|
|
# set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc
|
|||
|
|
# set project_constraints ./constraints/nf_sume_general.xdc
|
|||
|
|
# set nf_10g_constraints ./constraints/nf_sume_10g.xdc
|
|||
|
|
# source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
# source ./tcl/export_registers.tcl
|
|||
|
|
## set DEF_LIST {
|
|||
|
|
## {MICROBLAZE_AXI_IIC 0 0 ""} \
|
|||
|
|
## {MICROBLAZE_UARTLITE 0 0 ""} \
|
|||
|
|
## {MICROBLAZE_DLMB_BRAM 0 0 ""} \
|
|||
|
|
## {MICROBLAZE_ILMB_BRAM 0 0 ""} \
|
|||
|
|
## {MICROBLAZE_AXI_INTC 0 0 ""} \
|
|||
|
|
## {INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \
|
|||
|
|
## {OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \
|
|||
|
|
## {OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \
|
|||
|
|
## {NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \
|
|||
|
|
## {NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
## {NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
## {NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
## {NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## }
|
|||
|
|
## set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/
|
|||
|
|
## set target_file $target_path/sume_register_defines.h
|
|||
|
|
## proc write_header { target_file } {
|
|||
|
|
##
|
|||
|
|
## # creat a blank header file
|
|||
|
|
## # do a fresh rewrite in case the file already exits
|
|||
|
|
## file delete -force $target_file
|
|||
|
|
## open $target_file "w"
|
|||
|
|
## set h_file [open $target_file "w"]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## puts $h_file "//-"
|
|||
|
|
## puts $h_file "// Copyright (c) 2015 University of Cambridge"
|
|||
|
|
## puts $h_file "// All rights reserved."
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory "
|
|||
|
|
## puts $h_file "// under National Science Foundation under Grant No. CNS-0855268,"
|
|||
|
|
## puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and"
|
|||
|
|
## puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), "
|
|||
|
|
## puts $h_file "// as part of the DARPA MRC research programme."
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// @NETFPGA_LICENSE_HEADER_START@"
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor"
|
|||
|
|
## puts $h_file "// license agreements. See the NOTICE file distributed with this work for"
|
|||
|
|
## puts $h_file "// additional information regarding copyright ownership. NetFPGA licenses this"
|
|||
|
|
## puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the"
|
|||
|
|
## puts $h_file "// \"License\"); you may not use this file except in compliance with the"
|
|||
|
|
## puts $h_file "// License. You may obtain a copy of the License at:"
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// http://www.netfpga-cic.org"
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed"
|
|||
|
|
## puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR"
|
|||
|
|
## puts $h_file "// CONDITIONS OF ANY KIND, either express or implied. See the License for the"
|
|||
|
|
## puts $h_file "// specific language governing permissions and limitations under the License."
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// @NETFPGA_LICENSE_HEADER_END@"
|
|||
|
|
## puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
|
|||
|
|
## puts $h_file "// This is an automatically generated header definitions file"
|
|||
|
|
## puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
|
|||
|
|
## puts $h_file ""
|
|||
|
|
##
|
|||
|
|
## close $h_file
|
|||
|
|
##
|
|||
|
|
## };
|
|||
|
|
## proc write_core {target_file prefix id has_registers lib_name} {
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## set h_file [open $target_file "a"]
|
|||
|
|
##
|
|||
|
|
## #First, read the memory map information from the reference_project defines file
|
|||
|
|
## source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
## set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## set baseaddr [set $prefix\_BASEADDR]
|
|||
|
|
## set highaddr [set $prefix\_HIGHADDR]
|
|||
|
|
## set sizeaddr [set $prefix\_SIZEADDR]
|
|||
|
|
##
|
|||
|
|
## puts $h_file "//######################################################"
|
|||
|
|
## puts $h_file "//# Definitions for $prefix"
|
|||
|
|
## puts $h_file "//######################################################"
|
|||
|
|
##
|
|||
|
|
## puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr"
|
|||
|
|
## puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr"
|
|||
|
|
## puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr"
|
|||
|
|
## puts $h_file ""
|
|||
|
|
##
|
|||
|
|
## #Second, read the registers information from the library defines file
|
|||
|
|
## if $has_registers {
|
|||
|
|
## set lib_path "$public_repo_dir/std/cores/$lib_name"
|
|||
|
|
## set regs_h_define_file $lib_path
|
|||
|
|
## set regs_h_define_file_read [open $regs_h_define_file r]
|
|||
|
|
## set regs_h_define_file_data [read $regs_h_define_file_read]
|
|||
|
|
## close $regs_h_define_file_read
|
|||
|
|
## set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"]
|
|||
|
|
##
|
|||
|
|
## foreach read_line $regs_h_define_file_data_line {
|
|||
|
|
## if {[regexp "#define" $read_line]} {
|
|||
|
|
## puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]"
|
|||
|
|
## }
|
|||
|
|
## }
|
|||
|
|
## }
|
|||
|
|
## puts $h_file ""
|
|||
|
|
## close $h_file
|
|||
|
|
## };
|
|||
|
|
## write_header $target_file
|
|||
|
|
## foreach lib_item $DEF_LIST {
|
|||
|
|
## write_core $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3]
|
|||
|
|
## }
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
# create_project -name ${design} -force -dir "./${proj_dir}" -part ${device}
|
|||
|
|
# set_property source_mgmt_mode DisplayOnly [current_project]
|
|||
|
|
# set_property top ${top} [current_fileset]
|
|||
|
|
# puts "Creating User Datapath reference project"
|
|||
|
|
Creating User Datapath reference project
|
|||
|
|
# create_fileset -constrset -quiet constraints
|
|||
|
|
# file copy ${public_repo_dir}/ ${repo_dir}
|
|||
|
|
# set_property ip_repo_paths ${repo_dir} [current_fileset]
|
|||
|
|
# add_files -fileset constraints -norecurse ${bit_settings}
|
|||
|
|
# add_files -fileset constraints -norecurse ${project_constraints}
|
|||
|
|
# add_files -fileset constraints -norecurse ${nf_10g_constraints}
|
|||
|
|
# set_property is_enabled true [get_files ${project_constraints}]
|
|||
|
|
# set_property is_enabled true [get_files ${bit_settings}]
|
|||
|
|
# set_property is_enabled true [get_files ${nf_10g_constraints}]
|
|||
|
|
# set_property constrset constraints [get_runs synth_1]
|
|||
|
|
# set_property constrset constraints [get_runs impl_1]
|
|||
|
|
# update_ip_catalog
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
|
|||
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
|||
|
|
# create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci]
|
|||
|
|
# reset_target all [get_ips input_arbiter_ip]
|
|||
|
|
# generate_target all [get_ips input_arbiter_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'input_arbiter_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'input_arbiter_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'input_arbiter_ip'...
|
|||
|
|
# create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci]
|
|||
|
|
# reset_target all [get_ips sss_output_queues_ip]
|
|||
|
|
# generate_target all [get_ips sss_output_queues_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'sss_output_queues_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'sss_output_queues_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'sss_output_queues_ip'...
|
|||
|
|
# source ./tcl/control_sub.tcl
|
|||
|
|
## set scripts_vivado_version 2018.2
|
|||
|
|
## set current_vivado_version [version -short]
|
|||
|
|
## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
|||
|
|
## puts ""
|
|||
|
|
## puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
|
|||
|
|
##
|
|||
|
|
## return 1
|
|||
|
|
## }
|
|||
|
|
## set design_name control_sub
|
|||
|
|
## if { [get_projects -quiet] eq "" } {
|
|||
|
|
## puts "ERROR: Please open or create a project!"
|
|||
|
|
## return 1
|
|||
|
|
## }
|
|||
|
|
## set errMsg ""
|
|||
|
|
## set nRet 0
|
|||
|
|
## set cur_design [current_bd_design -quiet]
|
|||
|
|
## set list_cells [get_bd_cells -quiet]
|
|||
|
|
## if { ${design_name} eq "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 1) Design_name not set
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
|
|||
|
|
## set nRet 1
|
|||
|
|
##
|
|||
|
|
## } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 2): Current design opened AND is empty AND names same.
|
|||
|
|
## # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
|||
|
|
## # 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
|||
|
|
##
|
|||
|
|
## if { $cur_design ne $design_name } {
|
|||
|
|
## puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
|||
|
|
## set design_name [get_property NAME $cur_design]
|
|||
|
|
## }
|
|||
|
|
## puts "INFO: Constructing design in IPI design <$cur_design>..."
|
|||
|
|
##
|
|||
|
|
## } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 5) Current design opened AND has components AND same names.
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
|||
|
|
## set nRet 1
|
|||
|
|
## } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 6) Current opened design, has components, but diff names, design_name exists in project.
|
|||
|
|
## # 7) No opened design, design_name exists in project.
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
|||
|
|
## set nRet 2
|
|||
|
|
##
|
|||
|
|
## } else {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 8) No opened design, design_name not in project.
|
|||
|
|
## # 9) Current opened design, has components, but diff names, design_name not in project.
|
|||
|
|
##
|
|||
|
|
## puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
|
|||
|
|
##
|
|||
|
|
## create_bd_design $design_name
|
|||
|
|
##
|
|||
|
|
## puts "INFO: Making design <$design_name> as current_bd_design."
|
|||
|
|
## current_bd_design $design_name
|
|||
|
|
##
|
|||
|
|
## }
|
|||
|
|
INFO: Currently there is no design <control_sub> in project, so creating one...
|
|||
|
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
|||
|
|
INFO: Making design <control_sub> as current_bd_design.
|
|||
|
|
## puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
|
|||
|
|
INFO: Currently the variable <design_name> is equal to "control_sub".
|
|||
|
|
## if { $nRet != 0 } {
|
|||
|
|
## puts $errMsg
|
|||
|
|
## return $nRet
|
|||
|
|
## }
|
|||
|
|
## proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" || $nameHier eq "" } {
|
|||
|
|
## puts "ERROR: create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
## # Create cell and set as current instance
|
|||
|
|
## set hier_obj [create_bd_cell -type hier $nameHier]
|
|||
|
|
## current_bd_instance $hier_obj
|
|||
|
|
##
|
|||
|
|
## # Create interface pins
|
|||
|
|
## create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB
|
|||
|
|
## create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB
|
|||
|
|
##
|
|||
|
|
## # Create pins
|
|||
|
|
## create_bd_pin -dir I -type clk LMB_Clk
|
|||
|
|
## create_bd_pin -dir I -from 0 -to 0 -type rst LMB_Rst
|
|||
|
|
##
|
|||
|
|
## # Create instance: dlmb_bram_if_cntlr, and set properties
|
|||
|
|
## set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_ECC {0} ] $dlmb_bram_if_cntlr
|
|||
|
|
##
|
|||
|
|
## # Create instance: dlmb_v10, and set properties
|
|||
|
|
## set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: ilmb_bram_if_cntlr, and set properties
|
|||
|
|
## set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_ECC {0} ] $ilmb_bram_if_cntlr
|
|||
|
|
##
|
|||
|
|
## # Create instance: ilmb_v10, and set properties
|
|||
|
|
## set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: lmb_bram, and set properties
|
|||
|
|
## set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ]
|
|||
|
|
## set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller} ] $lmb_bram
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk]
|
|||
|
|
## connect_bd_net -net microblaze_0_LMB_Rst [get_bd_pins LMB_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst]
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
## }
|
|||
|
|
## proc create_hier_cell_mbsys { parentCell nameHier } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" || $nameHier eq "" } {
|
|||
|
|
## puts "ERROR: create_hier_cell_mbsys() - Empty argument(s)!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
## # Create cell and set as current instance
|
|||
|
|
## set hier_obj [create_bd_cell -type hier $nameHier]
|
|||
|
|
## current_bd_instance $hier_obj
|
|||
|
|
##
|
|||
|
|
## # Create interface pins
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI
|
|||
|
|
##
|
|||
|
|
## # Create pins
|
|||
|
|
## create_bd_pin -dir I -type clk Clk
|
|||
|
|
## create_bd_pin -dir I -from 0 -to 0 In0
|
|||
|
|
## create_bd_pin -dir I -from 0 -to 0 In1
|
|||
|
|
## create_bd_pin -dir I dcm_locked
|
|||
|
|
## create_bd_pin -dir I -type rst ext_reset_in
|
|||
|
|
## create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn
|
|||
|
|
##
|
|||
|
|
## # Create instance: mdm_1, and set properties
|
|||
|
|
## set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: microblaze_0, and set properties
|
|||
|
|
## set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:10.0 microblaze_0 ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_DEBUG_ENABLED {1} CONFIG.C_D_AXI {1} CONFIG.C_D_LMB {1} CONFIG.C_I_LMB {1} ] $microblaze_0
|
|||
|
|
##
|
|||
|
|
## # Create instance: microblaze_0_axi_intc, and set properties
|
|||
|
|
## set microblaze_0_axi_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 microblaze_0_axi_intc ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_HAS_FAST {1} ] $microblaze_0_axi_intc
|
|||
|
|
##
|
|||
|
|
## # Create instance: microblaze_0_axi_periph, and set properties
|
|||
|
|
## set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]
|
|||
|
|
## set_property -dict [ list CONFIG.NUM_MI {3} ] $microblaze_0_axi_periph
|
|||
|
|
##
|
|||
|
|
## # Create instance: microblaze_0_local_memory
|
|||
|
|
## create_hier_cell_microblaze_0_local_memory $hier_obj microblaze_0_local_memory
|
|||
|
|
##
|
|||
|
|
## # Create instance: microblaze_0_xlconcat, and set properties
|
|||
|
|
## set microblaze_0_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 microblaze_0_xlconcat ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: rst_clk_wiz_1_100M, and set properties
|
|||
|
|
## set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ]
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins M01_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins M02_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_intc_axi [get_bd_intf_pins microblaze_0_axi_intc/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins microblaze_0/INTERRUPT] [get_bd_intf_pins microblaze_0_axi_intc/interrupt]
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net In0_1 [get_bd_pins In0] [get_bd_pins microblaze_0_xlconcat/In0]
|
|||
|
|
## connect_bd_net -net In1_1 [get_bd_pins In1] [get_bd_pins microblaze_0_xlconcat/In1]
|
|||
|
|
## connect_bd_net -net clk_wiz_1_locked [get_bd_pins dcm_locked] [get_bd_pins rst_clk_wiz_1_100M/dcm_locked]
|
|||
|
|
## connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst]
|
|||
|
|
## connect_bd_net -net microblaze_0_Clk [get_bd_pins Clk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_intc/processor_clk] [get_bd_pins microblaze_0_axi_intc/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk]
|
|||
|
|
## connect_bd_net -net microblaze_0_intr [get_bd_pins microblaze_0_axi_intc/intr] [get_bd_pins microblaze_0_xlconcat/dout]
|
|||
|
|
## connect_bd_net -net reset_1 [get_bd_pins ext_reset_in] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]
|
|||
|
|
## connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/LMB_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset]
|
|||
|
|
## connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn]
|
|||
|
|
## connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins microblaze_0_axi_intc/processor_rst] [get_bd_pins rst_clk_wiz_1_100M/mb_reset]
|
|||
|
|
## connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins peripheral_aresetn] [get_bd_pins microblaze_0_axi_intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn]
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
## }
|
|||
|
|
## proc create_hier_cell_nf_mbsys { parentCell nameHier } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" || $nameHier eq "" } {
|
|||
|
|
## puts "ERROR: create_hier_cell_nf_mbsys() - Empty argument(s)!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
## # Create cell and set as current instance
|
|||
|
|
## set hier_obj [create_bd_cell -type hier $nameHier]
|
|||
|
|
## current_bd_instance $hier_obj
|
|||
|
|
##
|
|||
|
|
## # Create interface pins
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart
|
|||
|
|
##
|
|||
|
|
## # Create pins
|
|||
|
|
## create_bd_pin -dir O -from 1 -to 0 iic_reset
|
|||
|
|
## create_bd_pin -dir I -type rst reset
|
|||
|
|
## create_bd_pin -dir I -type clk sysclk
|
|||
|
|
##
|
|||
|
|
## # Create instance: axi_iic_0, and set properties
|
|||
|
|
## set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_GPO_WIDTH {2} CONFIG.C_SCL_INERTIAL_DELAY {5} CONFIG.C_SDA_INERTIAL_DELAY {5} ] $axi_iic_0
|
|||
|
|
##
|
|||
|
|
## # Create instance: axi_uartlite_0, and set properties
|
|||
|
|
## set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_BAUDRATE {115200} ] $axi_uartlite_0
|
|||
|
|
##
|
|||
|
|
## # Create instance: clk_wiz_1, and set properties
|
|||
|
|
## set clk_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_1 ]
|
|||
|
|
## # set_property -dict [ list CONFIG.PRIM_IN_FREQ {200.000} CONFIG.PRIM_SOURCE {No_buffer} ] $clk_wiz_1
|
|||
|
|
##
|
|||
|
|
## # config 100MHz input clk
|
|||
|
|
## set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} CONFIG.PRIM_SOURCE {No_buffer} \
|
|||
|
|
## CONFIG.CLKIN1_JITTER_PS {100.0} CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \
|
|||
|
|
## CONFIG.MMCM_CLKIN1_PERIOD {10.0} CONFIG.CLKOUT1_JITTER {130.958} \
|
|||
|
|
## CONFIG.CLKOUT1_PHASE_ERROR {98.575}] $clk_wiz_1
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create instance: mbsys
|
|||
|
|
## create_hier_cell_mbsys $hier_obj mbsys
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_pins iic_fpga] [get_bd_intf_pins axi_iic_0/IIC]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_pins uart] [get_bd_intf_pins axi_uartlite_0/UART]
|
|||
|
|
## connect_bd_intf_net -intf_net mbsys_M01_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins mbsys/M01_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net mbsys_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins mbsys/M02_AXI]
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net axi_iic_0_gpo [get_bd_pins iic_reset] [get_bd_pins axi_iic_0/gpo]
|
|||
|
|
## connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins mbsys/In0]
|
|||
|
|
## connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins mbsys/In1]
|
|||
|
|
## connect_bd_net -net clk_wiz_1_locked [get_bd_pins clk_wiz_1/locked] [get_bd_pins mbsys/dcm_locked]
|
|||
|
|
## connect_bd_net -net mbsys_peripheral_aresetn [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins mbsys/peripheral_aresetn]
|
|||
|
|
## connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins clk_wiz_1/clk_out1] [get_bd_pins mbsys/Clk]
|
|||
|
|
## connect_bd_net -net reset_1 [get_bd_pins reset] [get_bd_pins clk_wiz_1/reset] [get_bd_pins mbsys/ext_reset_in]
|
|||
|
|
## connect_bd_net -net sysclk_1 [get_bd_pins sysclk] [get_bd_pins clk_wiz_1/clk_in1]
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
## }
|
|||
|
|
## proc create_hier_cell_dma_sub { parentCell nameHier } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" || $nameHier eq "" } {
|
|||
|
|
## puts "ERROR: create_hier_cell_dma_sub() - Empty argument(s)!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
## # Create cell and set as current instance
|
|||
|
|
## set hier_obj [create_bd_cell -type hier $nameHier]
|
|||
|
|
## current_bd_instance $hier_obj
|
|||
|
|
##
|
|||
|
|
## # Create interface pins
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma_tx
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_7x_mgt
|
|||
|
|
## create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma_rx
|
|||
|
|
##
|
|||
|
|
## # Create pins
|
|||
|
|
## create_bd_pin -dir I -type clk axi_lite_aclk
|
|||
|
|
## create_bd_pin -dir I -type rst axi_lite_aresetn
|
|||
|
|
## create_bd_pin -dir I -type clk axis_datapath_aclk
|
|||
|
|
## create_bd_pin -dir I -type rst axis_datapath_aresetn
|
|||
|
|
## create_bd_pin -dir I -type clk sys_clk
|
|||
|
|
## create_bd_pin -dir I -type rst sys_reset
|
|||
|
|
##
|
|||
|
|
## create_bd_pin -dir I -type clk M00_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M00_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M01_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M01_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M02_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M02_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M03_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M03_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M04_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M04_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M05_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M05_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M06_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M06_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M07_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M07_ARESETN
|
|||
|
|
##
|
|||
|
|
## # Create instance: axi_interconnect_0, and set properties
|
|||
|
|
## set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
|
|||
|
|
## set_property -dict [ list CONFIG.NUM_MI {9} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M08_HAS_REGSLICE {3} CONFIG.M08_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
##
|
|||
|
|
## # AXIS: clock domain crossing FIFO, TX (PCIe->FPGA) user_fifo_reset (user_clk)
|
|||
|
|
## set pcie_reset_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic pcie_reset_inv]
|
|||
|
|
## set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {not}] [get_bd_cells pcie_reset_inv]
|
|||
|
|
##
|
|||
|
|
## # Create instance: axis_dwidth_converter
|
|||
|
|
## set axis_dwidth_dma_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_dma_tx]
|
|||
|
|
## set_property -dict [list CONFIG.HAS_TKEEP.VALUE_SRC USER CONFIG.HAS_TLAST.VALUE_SRC USER \
|
|||
|
|
## CONFIG.HAS_TSTRB.VALUE_SRC USER CONFIG.S_TDATA_NUM_BYTES.VALUE_SRC USER \
|
|||
|
|
## CONFIG.TUSER_BITS_PER_BYTE.VALUE_SRC USER] $axis_dwidth_dma_tx
|
|||
|
|
##
|
|||
|
|
## set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {16} CONFIG.M_TDATA_NUM_BYTES {32} \
|
|||
|
|
## CONFIG.TUSER_BITS_PER_BYTE {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TSTRB {0} \
|
|||
|
|
## CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1}] $axis_dwidth_dma_tx
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## set axis_dwidth_dma_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_dma_rx]
|
|||
|
|
##
|
|||
|
|
## set_property -dict [list CONFIG.HAS_TKEEP.VALUE_SRC USER CONFIG.HAS_TLAST.VALUE_SRC USER \
|
|||
|
|
## CONFIG.HAS_TSTRB.VALUE_SRC USER CONFIG.S_TDATA_NUM_BYTES.VALUE_SRC USER \
|
|||
|
|
## CONFIG.TUSER_BITS_PER_BYTE.VALUE_SRC USER] $axis_dwidth_dma_rx
|
|||
|
|
##
|
|||
|
|
## set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {32} CONFIG.M_TDATA_NUM_BYTES {16} \
|
|||
|
|
## CONFIG.TUSER_BITS_PER_BYTE {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TSTRB {0} \
|
|||
|
|
## CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1}] $axis_dwidth_dma_rx
|
|||
|
|
##
|
|||
|
|
## # Create instance: axis_fifo_10g_rx, and set properties
|
|||
|
|
## set axis_fifo_10g_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_fifo_10g_rx]
|
|||
|
|
## set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.TUSER_WIDTH {128} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32}] $axis_fifo_10g_rx
|
|||
|
|
##
|
|||
|
|
## # Create instance: axis_fifo_10g_tx, and set properties
|
|||
|
|
## set axis_fifo_10g_tx [create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_fifo_10g_tx]
|
|||
|
|
## set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.TUSER_WIDTH {128} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32}] $axis_fifo_10g_tx
|
|||
|
|
##
|
|||
|
|
## # Create instance: nf_riffa_dma_1, and set properties
|
|||
|
|
## set nf_riffa_dma_1 [ create_bd_cell -type ip -vlnv NetFPGA:NetFPGA:nf_riffa_dma:1.0 nf_riffa_dma_1 ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: axi_clock_converter_0, and set properties
|
|||
|
|
## set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: pcie3_7x_1, and set properties
|
|||
|
|
## set pcie3_7x_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:pcie3_7x:4.3 pcie3_7x_1 ]
|
|||
|
|
## set_property -dict [ list CONFIG.PF0_DEVICE_ID {7028} \
|
|||
|
|
## CONFIG.PF0_INTERRUPT_PIN {NONE} CONFIG.PF1_DEVICE_ID {7011} \
|
|||
|
|
## CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {5.0_GT/s} CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
|
|||
|
|
## CONFIG.axisten_freq {250} CONFIG.axisten_if_enable_client_tag {false} \
|
|||
|
|
## CONFIG.axisten_if_width {128_bit} CONFIG.cfg_ctl_if {false} \
|
|||
|
|
## CONFIG.cfg_ext_if {false} CONFIG.cfg_mgmt_if {false} \
|
|||
|
|
## CONFIG.cfg_tx_msg_if {false} CONFIG.en_ext_clk {false} \
|
|||
|
|
## CONFIG.extended_tag_field {true} CONFIG.gen_x0y0 {false} \
|
|||
|
|
## CONFIG.mode_selection {Advanced} CONFIG.pcie_blk_locn {X0Y1} \
|
|||
|
|
## CONFIG.per_func_status_if {false} CONFIG.pf0_bar0_size {1} \
|
|||
|
|
## CONFIG.pf0_dev_cap_max_payload {128_bytes} CONFIG.rcv_msg_if {false} \
|
|||
|
|
## CONFIG.tx_fc_if {false} CONFIG.xlnx_ref_board {None} \
|
|||
|
|
## ] $pcie3_7x_1
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI]
|
|||
|
|
##
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_dma_rx [get_bd_intf_pins s_axis_dma_rx] [get_bd_intf_pins axis_dwidth_dma_rx/S_AXIS]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_fifo_dwidth_rx [get_bd_intf_pins axis_fifo_10g_rx/S_AXIS] [get_bd_intf_pins axis_dwidth_dma_rx/M_AXIS]
|
|||
|
|
## connect_bd_intf_net -intf_net axis_fifo_10g_rx_M_AXIS [get_bd_intf_pins axis_fifo_10g_rx/M_AXIS] [get_bd_intf_pins nf_riffa_dma_1/s_axis_xge_rx]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_m_axis_dma_tx [get_bd_intf_pins m_axis_dma_tx] [get_bd_intf_pins axis_dwidth_dma_tx/M_AXIS]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_fifo_dwidth_tx [get_bd_intf_pins axis_fifo_10g_tx/M_AXIS] [get_bd_intf_pins axis_dwidth_dma_tx/S_AXIS]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_dwidth_conv_tx [get_bd_intf_pins axis_fifo_10g_tx/S_AXIS] [get_bd_intf_pins nf_riffa_dma_1/m_axis_xge_tx]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_interrupt [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_interrupt]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_msi [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt_msi] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_msi]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_status [get_bd_intf_pins nf_riffa_dma_1/cfg] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_status]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie_cfg_fc [get_bd_intf_pins nf_riffa_dma_1/cfg_fc] [get_bd_intf_pins pcie3_7x_1/pcie_cfg_fc]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_cc [get_bd_intf_pins nf_riffa_dma_1/s_axis_cc] [get_bd_intf_pins pcie3_7x_1/s_axis_cc]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_rq [get_bd_intf_pins nf_riffa_dma_1/s_axis_rq] [get_bd_intf_pins pcie3_7x_1/s_axis_rq]
|
|||
|
|
## connect_bd_intf_net -intf_net pcie3_7x_1_m_axis_cq [get_bd_intf_pins nf_riffa_dma_1/m_axis_cq] [get_bd_intf_pins pcie3_7x_1/m_axis_cq]
|
|||
|
|
## connect_bd_intf_net -intf_net pcie3_7x_1_m_axis_rc [get_bd_intf_pins nf_riffa_dma_1/m_axis_rc] [get_bd_intf_pins pcie3_7x_1/m_axis_rc]
|
|||
|
|
## connect_bd_intf_net -intf_net pcie3_7x_1_pcie_7x_mgt [get_bd_intf_pins pcie_7x_mgt] [get_bd_intf_pins pcie3_7x_1/pcie_7x_mgt]
|
|||
|
|
## connect_bd_intf_net -intf_net s00_axi_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins nf_riffa_dma_1/m_axi_lite]
|
|||
|
|
##
|
|||
|
|
## #Clock converter connections
|
|||
|
|
## connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins nf_riffa_dma_1/s_axi_lite]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M08_AXI]
|
|||
|
|
## set_property -dict [ list CONFIG.FREQ_HZ {250000000} ] [get_bd_intf_pins nf_riffa_dma_1/s_axi_lite]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net axi_lite_clk_1 [get_bd_pins axi_lite_aclk] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins nf_riffa_dma_1/m_axi_lite_aclk]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net M00_ACLK_i [get_bd_pins M00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK]
|
|||
|
|
## connect_bd_net -net M01_ACLK_i [get_bd_pins M01_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK]
|
|||
|
|
## connect_bd_net -net M02_ACLK_i [get_bd_pins M02_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK]
|
|||
|
|
## connect_bd_net -net M03_ACLK_i [get_bd_pins M03_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK]
|
|||
|
|
## connect_bd_net -net M04_ACLK_i [get_bd_pins M04_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK]
|
|||
|
|
## connect_bd_net -net M05_ACLK_i [get_bd_pins M05_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK]
|
|||
|
|
## connect_bd_net -net M06_ACLK_i [get_bd_pins M06_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK]
|
|||
|
|
## connect_bd_net -net M07_ACLK_i [get_bd_pins M07_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net axi_lite_rstn_1 [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_lite_aresetn] [get_bd_pins nf_riffa_dma_1/m_axi_lite_aresetn]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net M00_ARESETN_i [get_bd_pins M00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN]
|
|||
|
|
## connect_bd_net -net M01_ARESETN_i [get_bd_pins M01_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN]
|
|||
|
|
## connect_bd_net -net M02_ARESETN_i [get_bd_pins M02_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN]
|
|||
|
|
## connect_bd_net -net M03_ARESETN_i [get_bd_pins M03_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN]
|
|||
|
|
## connect_bd_net -net M04_ARESETN_i [get_bd_pins M04_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN]
|
|||
|
|
## connect_bd_net -net M05_ARESETN_i [get_bd_pins M05_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN]
|
|||
|
|
## connect_bd_net -net M06_ARESETN_i [get_bd_pins M06_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN]
|
|||
|
|
## connect_bd_net -net M07_ARESETN_i [get_bd_pins M07_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net axis_10g_clk_1 [get_bd_pins axis_datapath_aclk] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axis_dwidth_dma_rx/aclk] [get_bd_pins axis_dwidth_dma_tx/aclk] [get_bd_pins axis_fifo_10g_rx/s_axis_aclk] [get_bd_pins axis_fifo_10g_tx/m_axis_aclk]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net axis_rx_sys_reset_0_peripheral_aresetn [get_bd_pins axis_datapath_aresetn] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axis_dwidth_dma_rx/aresetn] [get_bd_pins axis_dwidth_dma_tx/aresetn] [get_bd_pins axis_fifo_10g_rx/s_axis_aresetn] [get_bd_pins axis_fifo_10g_tx/m_axis_aresetn]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net axis_tx_sys_reset_0_peripheral_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axis_fifo_10g_rx/m_axis_aresetn] [get_bd_pins axis_fifo_10g_tx/s_axis_aresetn] [get_bd_pins pcie_reset_inv/Res]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net pcie3_7x_1_user_clk [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axis_fifo_10g_rx/m_axis_aclk] [get_bd_pins axis_fifo_10g_tx/s_axis_aclk] [get_bd_pins nf_riffa_dma_1/user_clk] [get_bd_pins pcie3_7x_1/user_clk]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net pcie3_7x_1_user_lnk_up [get_bd_pins nf_riffa_dma_1/user_lnk_up] [get_bd_pins pcie3_7x_1/user_lnk_up]
|
|||
|
|
## connect_bd_net -net pcie3_7x_1_user_reset [get_bd_pins pcie_reset_inv/Op1] [get_bd_pins nf_riffa_dma_1/user_reset] [get_bd_pins pcie3_7x_1/user_reset]
|
|||
|
|
## connect_bd_net -net sys_clk_1 [get_bd_pins sys_clk] [get_bd_pins pcie3_7x_1/sys_clk]
|
|||
|
|
## connect_bd_net -net sys_reset_1 [get_bd_pins sys_reset] [get_bd_pins pcie3_7x_1/sys_reset]
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
## }
|
|||
|
|
## proc create_root_design { parentCell } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" } {
|
|||
|
|
## set parentCell [get_bd_cells /]
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create interface ports
|
|||
|
|
## set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI
|
|||
|
|
## set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M01_AXI
|
|||
|
|
## set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M02_AXI
|
|||
|
|
## set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M03_AXI
|
|||
|
|
## set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M04_AXI
|
|||
|
|
## set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M05_AXI
|
|||
|
|
## set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M06_AXI
|
|||
|
|
## set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M07_AXI
|
|||
|
|
## set iic_fpga [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga ]
|
|||
|
|
## set m_axis_dma_tx [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma_tx ]
|
|||
|
|
## set pcie_7x_mgt [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_7x_mgt ]
|
|||
|
|
## set s_axis_dma_rx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma_rx ]
|
|||
|
|
## set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} CONFIG.HAS_TREADY {1} CONFIG.HAS_TSTRB {0} CONFIG.LAYERED_METADATA {undef} CONFIG.PHASE {0.000} CONFIG.TDATA_NUM_BYTES {32} CONFIG.TDEST_WIDTH {0} CONFIG.TID_WIDTH {0} CONFIG.TUSER_WIDTH {128} ] $s_axis_dma_rx
|
|||
|
|
## set uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart ]
|
|||
|
|
##
|
|||
|
|
## # Create ports
|
|||
|
|
## set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ]
|
|||
|
|
## set axi_lite_aresetn [ create_bd_port -dir I -type rst axi_lite_aresetn ]
|
|||
|
|
## set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}] $axi_lite_aresetn
|
|||
|
|
## set axis_datapath_aclk [ create_bd_port -dir I -type clk axis_datapath_aclk ]
|
|||
|
|
## set axis_datapath_aresetn [ create_bd_port -dir I -type rst axis_datapath_aresetn ]
|
|||
|
|
## set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $axis_datapath_aresetn
|
|||
|
|
## set iic_reset [ create_bd_port -dir O -from 1 -to 0 iic_reset ]
|
|||
|
|
## set sys_clk [ create_bd_port -dir I -type clk sys_clk ]
|
|||
|
|
## set_property -dict [ list CONFIG.FREQ_HZ {100000000} ] $sys_clk
|
|||
|
|
## set sys_reset [ create_bd_port -dir I -type rst sys_reset ]
|
|||
|
|
## set_property -dict [ list CONFIG.POLARITY {ACTIVE_HIGH} ] $sys_reset
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create instance: dma_sub
|
|||
|
|
## create_hier_cell_dma_sub [current_bd_instance .] dma_sub
|
|||
|
|
##
|
|||
|
|
## # Create instance: nf_mbsys
|
|||
|
|
## create_hier_cell_nf_mbsys [current_bd_instance .] nf_mbsys
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins dma_sub/M00_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins dma_sub/M01_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins dma_sub/M02_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins dma_sub/M03_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins dma_sub/M04_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins dma_sub/M05_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins dma_sub/M06_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins dma_sub/M07_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_m_axis_dma_tx [get_bd_intf_ports m_axis_dma_tx] [get_bd_intf_pins dma_sub/m_axis_dma_tx]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_pcie_7x_mgt [get_bd_intf_ports pcie_7x_mgt] [get_bd_intf_pins dma_sub/pcie_7x_mgt]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_mbsys_iic_fpga [get_bd_intf_ports iic_fpga] [get_bd_intf_pins nf_mbsys/iic_fpga]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_mbsys_uart [get_bd_intf_ports uart] [get_bd_intf_pins nf_mbsys/uart]
|
|||
|
|
## connect_bd_intf_net -intf_net s_axis_dma_rx_1 [get_bd_intf_ports s_axis_dma_rx] [get_bd_intf_pins dma_sub/s_axis_dma_rx]
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk] [get_bd_pins dma_sub/axi_lite_aclk]
|
|||
|
|
## connect_bd_net -net axi_lite_aresetn_1 [get_bd_ports axi_lite_aresetn] [get_bd_pins dma_sub/axi_lite_aresetn]
|
|||
|
|
## connect_bd_net -net axis_datapath_aclk_1 [get_bd_ports axis_datapath_aclk] [get_bd_pins dma_sub/axis_datapath_aclk] [get_bd_pins dma_sub/M00_ACLK] [get_bd_pins dma_sub/M01_ACLK] [get_bd_pins dma_sub/M02_ACLK] [get_bd_pins dma_sub/M03_ACLK] [get_bd_pins dma_sub/M04_ACLK] [get_bd_pins dma_sub/M05_ACLK] [get_bd_pins dma_sub/M06_ACLK] [get_bd_pins dma_sub/M07_ACLK]
|
|||
|
|
## connect_bd_net -net axis_datapath_aresetn_1 [get_bd_ports axis_datapath_aresetn] [get_bd_pins dma_sub/axis_datapath_aresetn] [get_bd_pins dma_sub/M00_ARESETN] [get_bd_pins dma_sub/M01_ARESETN] [get_bd_pins dma_sub/M02_ARESETN] [get_bd_pins dma_sub/M03_ARESETN] [get_bd_pins dma_sub/M04_ARESETN] [get_bd_pins dma_sub/M05_ARESETN] [get_bd_pins dma_sub/M06_ARESETN] [get_bd_pins dma_sub/M07_ARESETN]
|
|||
|
|
## connect_bd_net -net nf_mbsys_iic_reset [get_bd_ports iic_reset] [get_bd_pins nf_mbsys/iic_reset]
|
|||
|
|
## connect_bd_net -net sys_clk_1 [get_bd_ports sys_clk] [get_bd_pins dma_sub/sys_clk] [get_bd_pins nf_mbsys/sysclk]
|
|||
|
|
## connect_bd_net -net sys_reset_1 [get_bd_ports sys_reset] [get_bd_pins dma_sub/sys_reset] [get_bd_pins nf_mbsys/reset]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create address segments
|
|||
|
|
## source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
## create_bd_addr_seg -range $M00_SIZEADDR -offset $M00_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M01_SIZEADDR -offset $M01_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M01_AXI/Reg] SEG_M01_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M02_SIZEADDR -offset $M02_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M02_AXI/Reg] SEG_M02_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M03_SIZEADDR -offset $M03_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M03_AXI/Reg] SEG_M03_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M04_SIZEADDR -offset $M04_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M04_AXI/Reg] SEG_M04_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M05_SIZEADDR -offset $M05_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M05_AXI/Reg] SEG_M05_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M06_SIZEADDR -offset $M06_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M06_AXI/Reg] SEG_M06_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M07_SIZEADDR -offset $M07_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M07_AXI/Reg] SEG_M07_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M08_SIZEADDR -offset $M08_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs dma_sub/nf_riffa_dma_1/s_axi_lite/reg0] SEG_nf_riffa_dma_1_reg0
|
|||
|
|
##
|
|||
|
|
## create_bd_addr_seg -range $MICROBLAZE_AXI_IIC_SIZEADDR -offset $MICROBLAZE_AXI_IIC_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg
|
|||
|
|
## create_bd_addr_seg -range $MICROBLAZE_UARTLITE_SIZEADDR -offset $MICROBLAZE_UARTLITE_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
|
|||
|
|
## create_bd_addr_seg -range $MICROBLAZE_DLMB_BRAM_SIZEADDR -offset $MICROBLAZE_DLMB_BRAM_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem
|
|||
|
|
## create_bd_addr_seg -range $MICROBLAZE_ILMB_BRAM_SIZEADDR -offset $MICROBLAZE_ILMB_BRAM_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Instruction] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem
|
|||
|
|
## create_bd_addr_seg -range $MICROBLAZE_AXI_INTC_SIZEADDR -offset $MICROBLAZE_AXI_INTC_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_axi_intc/s_axi/Reg] SEG_microblaze_0_axi_intc_Reg
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
##
|
|||
|
|
## save_bd_design
|
|||
|
|
## }
|
|||
|
|
## create_root_design ""
|
|||
|
|
CRITICAL WARNING: [BD 41-737] Cannot set the parameter FREQ_HZ on /dma_sub/nf_riffa_dma_1/s_axi_lite. It is read-only.
|
|||
|
|
create_bd_cell: Time (s): cpu = 00:00:23 ; elapsed = 00:00:58 . Memory (MB): peak = 1702.613 ; gain = 287.730 ; free physical = 9686 ; free virtual = 15058
|
|||
|
|
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '10.000' to '10.0' has been ignored for IP 'nf_mbsys/clk_wiz_1'
|
|||
|
|
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
|||
|
|
# create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci]
|
|||
|
|
# reset_target all [get_ips nf_sume_sdnet_ip]
|
|||
|
|
# generate_target all [get_ips nf_sume_sdnet_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
# source ./create_ip/nf_10ge_interface.tcl
|
|||
|
|
## set sharedLogic "FALSE"
|
|||
|
|
## set tdataWidth 256
|
|||
|
|
## set convWidth [expr $tdataWidth/8]
|
|||
|
|
## if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } {
|
|||
|
|
## set supportLevel 1
|
|||
|
|
## } else {
|
|||
|
|
## set supportLevel 0
|
|||
|
|
## }
|
|||
|
|
## create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_nonshared
|
|||
|
|
WARNING: [IP_Flow 19-4832] The IP name 'axi_10g_ethernet_nonshared' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues.
|
|||
|
|
## set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
|
|||
|
|
## set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
|
|||
|
|
## set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
## set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
## set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
## set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
## set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_nonshared.xci]
|
|||
|
|
## reset_target all [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
## generate_target all [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_10g_ethernet_nonshared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_10g_ethernet_nonshared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_10g_ethernet_nonshared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_10g_ethernet_nonshared'...
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/hw_handoff/axi_10g_ethernet_nonshared.hwh
|
|||
|
|
Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/hw_handoff/axi_10g_ethernet_nonshared_bd.tcl
|
|||
|
|
Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/synth/axi_10g_ethernet_nonshared.hwdef
|
|||
|
|
generate_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1942.477 ; gain = 43.977 ; free physical = 9425 ; free virtual = 14841
|
|||
|
|
## create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_status
|
|||
|
|
## set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Performance_Options {First_Word_Fall_Through}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Input_Data_Width {458} CONFIG.Input_Depth {16}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Reset_Pin {false}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Output_Data_Width {458} CONFIG.Output_Depth {16}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Full_Flags_Reset_Value {0}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Use_Dout_Reset {false}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Data_Count_Width {4}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Write_Data_Count_Width {4}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Read_Data_Count_Width {4}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Full_Threshold_Assert_Value {15}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Full_Threshold_Negate_Value {14}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Empty_Threshold_Assert_Value {4}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Empty_Threshold_Negate_Value {5}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property generate_synth_checkpoint false [get_files fifo_generator_status.xci]
|
|||
|
|
## reset_target all [get_ips fifo_generator_status]
|
|||
|
|
## generate_target all [get_ips fifo_generator_status]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fifo_generator_status'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_generator_status'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fifo_generator_status'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fifo_generator_status'...
|
|||
|
|
## create_ip -name util_vector_logic -vendor xilinx.com -library ip -version 2.0 -module_name inverter_0
|
|||
|
|
WARNING: [Coretcl 2-1618] The 'xilinx.com:ip:util_vector_logic:2.0' IP is intended for use in IPI only.
|
|||
|
|
## set_property -dict [list CONFIG.C_SIZE {1}] [get_ips inverter_0]
|
|||
|
|
## set_property -dict [list CONFIG.C_OPERATION {not}] [get_ips inverter_0]
|
|||
|
|
## set_property generate_synth_checkpoint false [get_files inverter_0.xci]
|
|||
|
|
## reset_target all [get_ips inverter_0]
|
|||
|
|
## generate_target all [get_ips inverter_0]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'inverter_0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'inverter_0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'inverter_0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'inverter_0'...
|
|||
|
|
## create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_1_9
|
|||
|
|
## set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM} CONFIG.Performance_Options {First_Word_Fall_Through} CONFIG.Input_Data_Width {1} CONFIG.Input_Depth {16} CONFIG.Output_Data_Width {1} CONFIG.Output_Depth {16} CONFIG.Data_Count_Width {4} CONFIG.Write_Data_Count_Width {4} CONFIG.Read_Data_Count_Width {4} CONFIG.Full_Threshold_Assert_Value {13} CONFIG.Full_Threshold_Negate_Value {12}] [get_ips fifo_generator_1_9]
|
|||
|
|
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Assert_Value' from '15' to '13' has been ignored for IP 'fifo_generator_1_9'
|
|||
|
|
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Negate_Value' from '14' to '12' has been ignored for IP 'fifo_generator_1_9'
|
|||
|
|
## set_property generate_synth_checkpoint false [get_files fifo_generator_1_9.xci]
|
|||
|
|
## reset_target all [get_ips fifo_generator_1_9]
|
|||
|
|
## generate_target all [get_ips fifo_generator_1_9]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fifo_generator_1_9'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_generator_1_9'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fifo_generator_1_9'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fifo_generator_1_9'...
|
|||
|
|
# create_ip -name nf_10ge_interface -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_ip
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files nf_10g_interface_ip.xci]
|
|||
|
|
# reset_target all [get_ips nf_10g_interface_ip]
|
|||
|
|
# generate_target all [get_ips nf_10g_interface_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_10g_interface_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_10g_interface_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_10g_interface_ip'...
|
|||
|
|
generate_target: Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1987.285 ; gain = 38.785 ; free physical = 9357 ; free virtual = 14831
|
|||
|
|
# source ./create_ip/nf_10ge_interface_shared.tcl
|
|||
|
|
## set sharedLogic "TRUE"
|
|||
|
|
## set tdataWidth 256
|
|||
|
|
## set convWidth [expr $tdataWidth/8]
|
|||
|
|
## if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } {
|
|||
|
|
## set supportLevel 1
|
|||
|
|
## } else {
|
|||
|
|
## set supportLevel 0
|
|||
|
|
## }
|
|||
|
|
## create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_shared
|
|||
|
|
## set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
|
|||
|
|
## set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
|
|||
|
|
## set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
WARNING: [BD 41-1306] The connection to interface pin /xpcs/refclk_p is being overridden by the user. This pin will not be connected as a part of interface connection refclk_diff_port
|
|||
|
|
WARNING: [BD 41-1306] The connection to interface pin /xpcs/refclk_n is being overridden by the user. This pin will not be connected as a part of interface connection refclk_diff_port
|
|||
|
|
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
|
|||
|
|
## set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
## set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
## set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
## set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_shared.xci]
|
|||
|
|
## reset_target all [get_ips axi_10g_ethernet_shared]
|
|||
|
|
## generate_target all [get_ips axi_10g_ethernet_shared]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_10g_ethernet_shared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_10g_ethernet_shared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_10g_ethernet_shared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_10g_ethernet_shared'...
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/hw_handoff/axi_10g_ethernet_shared.hwh
|
|||
|
|
Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/hw_handoff/axi_10g_ethernet_shared_bd.tcl
|
|||
|
|
Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/synth/axi_10g_ethernet_shared.hwdef
|
|||
|
|
generate_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2002.617 ; gain = 15.328 ; free physical = 9301 ; free virtual = 14781
|
|||
|
|
# create_ip -name nf_10ge_interface_shared -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_shared_ip
|
|||
|
|
WARNING: [IP_Flow 19-4832] The IP name 'nf_10g_interface_shared_ip' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues.
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files nf_10g_interface_shared_ip.xci]
|
|||
|
|
# reset_target all [get_ips nf_10g_interface_shared_ip]
|
|||
|
|
# generate_target all [get_ips nf_10g_interface_shared_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_10g_interface_shared_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_10g_interface_shared_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_10g_interface_shared_ip'...
|
|||
|
|
generate_target: Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 2040.145 ; gain = 37.527 ; free physical = 9281 ; free virtual = 14780
|
|||
|
|
# create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip
|
|||
|
|
# set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip]
|
|||
|
|
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '5.000' to '5.0' has been ignored for IP 'clk_wiz_ip'
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci]
|
|||
|
|
# reset_target all [get_ips clk_wiz_ip]
|
|||
|
|
# generate_target all [get_ips clk_wiz_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_ip'...
|
|||
|
|
# create_ip -name proc_sys_reset -vendor xilinx.com -library ip -version 5.0 -module_name proc_sys_reset_ip
|
|||
|
|
# set_property -dict [list CONFIG.C_EXT_RESET_HIGH {0} CONFIG.C_AUX_RESET_HIGH {0}] [get_ips proc_sys_reset_ip]
|
|||
|
|
# set_property -dict [list CONFIG.C_NUM_PERP_RST {1} CONFIG.C_NUM_PERP_ARESETN {1}] [get_ips proc_sys_reset_ip]
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files proc_sys_reset_ip.xci]
|
|||
|
|
# reset_target all [get_ips proc_sys_reset_ip]
|
|||
|
|
# generate_target all [get_ips proc_sys_reset_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'proc_sys_reset_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'proc_sys_reset_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'proc_sys_reset_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'proc_sys_reset_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'proc_sys_reset_ip'...
|
|||
|
|
# create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip
|
|||
|
|
# set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {4096} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip]
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files identifier_ip.xci]
|
|||
|
|
# reset_target all [get_ips identifier_ip]
|
|||
|
|
# generate_target all [get_ips identifier_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'identifier_ip'...
|
|||
|
|
# read_verilog "./hdl/axi_clocking.v"
|
|||
|
|
# read_verilog "./hdl/nf_datapath.v"
|
|||
|
|
# read_verilog "./hdl/top.v"
|
|||
|
|
# create_run -flow {Vivado Synthesis 2018} synth
|
|||
|
|
Run is defaulting to srcset: sources_1
|
|||
|
|
Run is defaulting to constrset: constraints
|
|||
|
|
Run is defaulting to part: xc7vx690tffg1761-3
|
|||
|
|
# create_run impl -parent_run synth -flow {Vivado Implementation 2018}
|
|||
|
|
Run is defaulting to parent run srcset: sources_1
|
|||
|
|
Run is defaulting to parent run constrset: constraints
|
|||
|
|
Run is defaulting to parent run part: xc7vx690tffg1761-3
|
|||
|
|
# set_property steps.phys_opt_design.is_enabled true [get_runs impl_1]
|
|||
|
|
# set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE ExploreWithHoldFix [get_runs impl_1]
|
|||
|
|
# set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
|
|||
|
|
# set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.is_enabled true [get_runs impl_1]
|
|||
|
|
# set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
|||
|
|
# set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
|
|||
|
|
# launch_runs synth
|
|||
|
|
INFO: [xilinx.com:ip:axi_intc:4.1-1] /nf_mbsys/mbsys/microblaze_0_axi_intc: The AXI INTC core has been configured to operate with synchronous clocks.
|
|||
|
|
INFO: [xilinx.com:ip:axi_intc:4.1-1] /nf_mbsys/mbsys/microblaze_0_axi_intc: The AXI INTC core has been configured to operate with synchronous clocks.
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/dma_sub/nf_riffa_dma_1/cfg_interrupt_sent
|
|||
|
|
|
|||
|
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
|||
|
|
VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v
|
|||
|
|
VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/sim/control_sub.v
|
|||
|
|
VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hdl/control_sub_wrapper.v
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/axi_iic_0 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/axi_uartlite_0 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/clk_wiz_1 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/mdm_1 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_axi_intc .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_xlconcat .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/rst_clk_wiz_1_100M .
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INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr .
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10 .
|
|||
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|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr .
|
|||
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|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10 .
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram .
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_axi_periph/xbar .
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/pcie_reset_inv .
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_dwidth_dma_tx .
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_dwidth_dma_rx .
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_fifo_10g_rx .
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_fifo_10g_tx .
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/nf_riffa_dma_1 .
|
|||
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|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_ooc.xdc'
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_clock_converter_0 .
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/pcie3_7x_1 .
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/xbar .
|
|||
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|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0_ooc.xdc'
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo .
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|||
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0_ooc.xdc'
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo .
|
|||
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0_ooc.xdc'
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo .
|
|||
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0_ooc.xdc'
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo .
|
|||
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0_ooc.xdc'
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo .
|
|||
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0_ooc.xdc'
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo .
|
|||
|
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0_ooc.xdc'
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo .
|
|||
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0_ooc.xdc'
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo .
|
|||
|
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0_ooc.xdc'
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo .
|
|||
|
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0_ooc.xdc'
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_ooc.xdc'
|
|||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/s00_couplers/auto_cc .
|
|||
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|
Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hw_handoff/control_sub.hwh
|
|||
|
|
Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hw_handoff/control_sub_bd.tcl
|
|||
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|
Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.hwdef
|
|||
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|
[Sun Jul 21 12:34:52 2019] Launched control_sub_m07_data_fifo_0_synth_1, control_sub_mdm_1_0_synth_1, control_sub_clk_wiz_1_0_synth_1, control_sub_axi_uartlite_0_0_synth_1, control_sub_axi_iic_0_0_synth_1, control_sub_ilmb_v10_0_synth_1, control_sub_lmb_bram_0_synth_1, control_sub_xbar_1_synth_1, control_sub_pcie_reset_inv_0_synth_1, control_sub_axis_dwidth_dma_tx_0_synth_1, control_sub_axis_dwidth_dma_rx_0_synth_1, control_sub_axis_fifo_10g_rx_0_synth_1, control_sub_axis_fifo_10g_tx_0_synth_1, control_sub_nf_riffa_dma_1_0_synth_1, control_sub_axi_clock_converter_0_0_synth_1, control_sub_pcie3_7x_1_0_synth_1, control_sub_xbar_0_synth_1, control_sub_microblaze_0_0_synth_1, control_sub_microblaze_0_axi_intc_0_synth_1, control_sub_microblaze_0_xlconcat_0_synth_1, control_sub_rst_clk_wiz_1_100M_0_synth_1, control_sub_dlmb_bram_if_cntlr_0_synth_1, control_sub_dlmb_v10_0_synth_1, control_sub_ilmb_bram_if_cntlr_0_synth_1, control_sub_m08_data_fifo_0_synth_1, control_sub_m06_data_fifo_0_synth_1, control_sub_m05_data_fifo_0_synth_1, control_sub_m04_data_fifo_0_synth_1, control_sub_m03_data_fifo_0_synth_1, control_sub_m02_data_fifo_0_synth_1, control_sub_m01_data_fifo_0_synth_1, control_sub_m00_data_fifo_0_synth_1, control_sub_s00_data_fifo_0_synth_1, control_sub_auto_cc_0_synth_1...
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Run output will be captured here:
|
|||
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control_sub_m07_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m07_data_fifo_0_synth_1/runme.log
|
|||
|
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control_sub_mdm_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_mdm_1_0_synth_1/runme.log
|
|||
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control_sub_clk_wiz_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_clk_wiz_1_0_synth_1/runme.log
|
|||
|
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control_sub_axi_uartlite_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_uartlite_0_0_synth_1/runme.log
|
|||
|
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control_sub_axi_iic_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_iic_0_0_synth_1/runme.log
|
|||
|
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control_sub_ilmb_v10_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_v10_0_synth_1/runme.log
|
|||
|
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control_sub_lmb_bram_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_lmb_bram_0_synth_1/runme.log
|
|||
|
|
control_sub_xbar_1_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_1_synth_1/runme.log
|
|||
|
|
control_sub_pcie_reset_inv_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie_reset_inv_0_synth_1/runme.log
|
|||
|
|
control_sub_axis_dwidth_dma_tx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_tx_0_synth_1/runme.log
|
|||
|
|
control_sub_axis_dwidth_dma_rx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_rx_0_synth_1/runme.log
|
|||
|
|
control_sub_axis_fifo_10g_rx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_rx_0_synth_1/runme.log
|
|||
|
|
control_sub_axis_fifo_10g_tx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_tx_0_synth_1/runme.log
|
|||
|
|
control_sub_nf_riffa_dma_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_nf_riffa_dma_1_0_synth_1/runme.log
|
|||
|
|
control_sub_axi_clock_converter_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_clock_converter_0_0_synth_1/runme.log
|
|||
|
|
control_sub_pcie3_7x_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie3_7x_1_0_synth_1/runme.log
|
|||
|
|
control_sub_xbar_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_0_synth_1/runme.log
|
|||
|
|
control_sub_microblaze_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_0_synth_1/runme.log
|
|||
|
|
control_sub_microblaze_0_axi_intc_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_axi_intc_0_synth_1/runme.log
|
|||
|
|
control_sub_microblaze_0_xlconcat_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_xlconcat_0_synth_1/runme.log
|
|||
|
|
control_sub_rst_clk_wiz_1_100M_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_rst_clk_wiz_1_100M_0_synth_1/runme.log
|
|||
|
|
control_sub_dlmb_bram_if_cntlr_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_bram_if_cntlr_0_synth_1/runme.log
|
|||
|
|
control_sub_dlmb_v10_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_v10_0_synth_1/runme.log
|
|||
|
|
control_sub_ilmb_bram_if_cntlr_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_bram_if_cntlr_0_synth_1/runme.log
|
|||
|
|
control_sub_m08_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m08_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_m06_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m06_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_m05_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m05_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_m04_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m04_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_m03_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m03_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_m02_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_m01_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m01_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_m00_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m00_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_s00_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_s00_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_auto_cc_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_auto_cc_0_synth_1/runme.log
|
|||
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|
[Sun Jul 21 12:34:52 2019] Launched synth...
|
|||
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|
Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log
|
|||
|
|
launch_runs: Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2875.852 ; gain = 835.703 ; free physical = 9055 ; free virtual = 14630
|
|||
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|
# wait_on_run synth
|
|||
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|
[Sun Jul 21 12:34:52 2019] Waiting for synth to finish...
|
|||
|
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|
|||
|
|
*** Running vivado
|
|||
|
|
with args -log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl
|
|||
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|
|||
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|
|||
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|
****** Vivado v2018.2 (64-bit)
|
|||
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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source top.tcl -notrace
|
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Command: synth_design -top top -part xc7vx690tffg1761-3
|
|||
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Starting synth_design
|
|||
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WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
|
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/identifier_ip.xci
|
|||
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|
|||
|
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx690t'
|
|||
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx690t'
|
|||
|
|
INFO: Launching helper process for spawning children vivado processes
|
|||
|
|
INFO: Helper process launched with PID 14081
|
|||
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WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_single [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153]
|
|||
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WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_gray [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
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WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_handshake [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:469]
|
|||
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WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_pulse [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:715]
|
|||
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WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_array_single [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
|
|||
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|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_sync_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055]
|
|||
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|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_async_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1171]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_base [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_counter_updn [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_reg_vec [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_reg_bit [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_reg_pipe_bit [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1774]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_sync [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_async [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_axis [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2076]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_base [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module asym_bwe_bb [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6541]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_dpdistram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6600]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_dprom [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6734]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_sdpram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6888]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_spram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7043]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_sprom [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7189]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_tdpram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325]
|
|||
|
|
WARNING: [Synth 8-2507] parameter declaration becomes local in small_fifo with formal parameter declaration list [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:67]
|
|||
|
|
WARNING: [Synth 8-2507] parameter declaration becomes local in sss_small_fifo with formal parameter declaration list [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_small_fifo.v:69]
|
|||
|
|
WARNING: [Synth 8-2306] macro REG_ID_DEFAULT redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues_cpu_regs_defines.v:44]
|
|||
|
|
WARNING: [Synth 8-2306] macro REG_ID_DEFAULT redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:44]
|
|||
|
|
WARNING: [Synth 8-2306] macro REG_PKTIN_ADDR redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:75]
|
|||
|
|
WARNING: [Synth 8-2306] macro REG_PKTOUT_ADDR redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:80]
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 1470.594 ; gain = 149.371 ; free physical = 8459 ; free virtual = 14161
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'top' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:43]
|
|||
|
|
Parameter C_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter IF_SFP0 bound to: 8'b00000001
|
|||
|
|
Parameter IF_SFP1 bound to: 8'b00000100
|
|||
|
|
Parameter IF_SFP2 bound to: 8'b00010000
|
|||
|
|
Parameter IF_SFP3 bound to: 8'b01000000
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:152]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:153]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:154]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:155]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:156]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:157]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:166]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:167]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:168]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:169]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:170]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:171]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:180]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:181]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:182]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:183]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:184]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:185]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:194]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:195]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:196]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:197]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:198]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:199]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:259]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:260]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:261]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:262]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:263]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:264]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:265]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:266]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:267]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:268]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:269]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:270]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:271]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:272]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:273]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:274]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:275]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:276]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:277]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:431]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'OBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:27275]
|
|||
|
|
Parameter CAPACITANCE bound to: DONT_CARE - type: string
|
|||
|
|
Parameter DRIVE bound to: 12 - type: integer
|
|||
|
|
Parameter IOSTANDARD bound to: DEFAULT - type: string
|
|||
|
|
Parameter SLEW bound to: SLOW - type: string
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'OBUF' (1#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:27275]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19473]
|
|||
|
|
Parameter CAPACITANCE bound to: DONT_CARE - type: string
|
|||
|
|
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
|
|||
|
|
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
|
|||
|
|
Parameter IOSTANDARD bound to: DEFAULT - type: string
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19473]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'IBUFDS_GTE2' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19625]
|
|||
|
|
Parameter CLKCM_CFG bound to: TRUE - type: string
|
|||
|
|
Parameter CLKRCV_TRST bound to: TRUE - type: string
|
|||
|
|
Parameter CLKSWING_CFG bound to: 2'b11
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'IBUFDS_GTE2' (3#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19625]
|
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INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:22660]
|
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Parameter DRIVE bound to: 12 - type: integer
|
|||
|
|
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
|
|||
|
|
Parameter IOSTANDARD bound to: DEFAULT - type: string
|
|||
|
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Parameter SLEW bound to: SLOW - type: string
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (4#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:22660]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'axi_clocking' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/axi_clocking.v:44]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488]
|
|||
|
|
Parameter CAPACITANCE bound to: DONT_CARE - type: string
|
|||
|
|
Parameter DIFF_TERM bound to: FALSE - type: string
|
|||
|
|
Parameter DQS_BIAS bound to: FALSE - type: string
|
|||
|
|
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
|
|||
|
|
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
|
|||
|
|
Parameter IOSTANDARD bound to: DEFAULT - type: string
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (5#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'clk_wiz_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.v:70]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'clk_wiz_ip_clk_wiz' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:68]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:126]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:126]
|
|||
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INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762]
|
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|
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Parameter BANDWIDTH bound to: OPTIMIZED - type: string
|
|||
|
|
Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: float
|
|||
|
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Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
|
|||
|
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Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
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Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float
|
|||
|
|
Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT0_DIVIDE_F bound to: 5.000000 - type: float
|
|||
|
|
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter COMPENSATION bound to: ZHOLD - type: string
|
|||
|
|
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter IS_CLKINSEL_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_PSEN_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_PSINCDEC_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_PWRDWN_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_RST_INVERTED bound to: 1'b0
|
|||
|
|
Parameter REF_JITTER1 bound to: 0.010000 - type: float
|
|||
|
|
Parameter REF_JITTER2 bound to: 0.010000 - type: float
|
|||
|
|
Parameter SS_EN bound to: FALSE - type: string
|
|||
|
|
Parameter SS_MODE bound to: CENTER_HIGH - type: string
|
|||
|
|
Parameter SS_MOD_PERIOD bound to: 10000 - type: integer
|
|||
|
|
Parameter STARTUP_WAIT bound to: FALSE - type: string
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (6#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (7#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'BUFGCE' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:619]
|
|||
|
|
Parameter CE_TYPE bound to: SYNC - type: string
|
|||
|
|
Parameter IS_CE_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_I_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'BUFGCE' (8#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:619]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'BUFH' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:808]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'BUFH' (9#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:808]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_ip_clk_wiz' (10#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:68]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_ip' (11#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.v:70]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'axi_clocking' (12#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/axi_clocking.v:44]
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:74]
|
|||
|
|
Parameter C_FAMILY bound to: virtex7 - type: string
|
|||
|
|
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_EXT_RESET_HIGH bound to: 1'b0
|
|||
|
|
Parameter C_AUX_RESET_HIGH bound to: 1'b0
|
|||
|
|
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
|
|||
|
|
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:129]
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
|
|||
|
|
Parameter C_FAMILY bound to: virtex7 - type: string
|
|||
|
|
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_EXT_RESET_HIGH bound to: 1'b0
|
|||
|
|
Parameter C_AUX_RESET_HIGH bound to: 1'b0
|
|||
|
|
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
|
|||
|
|
Parameter INIT bound to: 1'b1
|
|||
|
|
Parameter IS_C_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_D_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_R_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1392]
|
|||
|
|
Parameter INIT bound to: 1'b1
|
|||
|
|
Parameter IS_C_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_D_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_R_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1408]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
Parameter IS_C_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_D_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_R_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1434]
|
|||
|
|
Parameter INIT bound to: 1'b1
|
|||
|
|
Parameter IS_C_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_D_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_R_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1457]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
Parameter IS_C_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_D_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_R_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1481]
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'lpf' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
|
|||
|
|
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_EXT_RESET_HIGH bound to: 1'b0
|
|||
|
|
Parameter C_AUX_RESET_HIGH bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-3491] module 'SRL16' declared at '/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:868]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'SRL16' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695]
|
|||
|
|
Parameter INIT bound to: 16'b0000000000000000
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (13#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695]
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:106]
|
|||
|
|
Parameter C_CDC_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter C_RESET_STATE bound to: 0 - type: integer
|
|||
|
|
Parameter C_SINGLE_BIT bound to: 1 - type: integer
|
|||
|
|
Parameter C_FLOP_INPUT bound to: 0 - type: integer
|
|||
|
|
Parameter C_VECTOR_WIDTH bound to: 2 - type: integer
|
|||
|
|
Parameter C_MTBF_STAGES bound to: 4 - type: integer
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:514]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:545]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:554]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:564]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:574]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:584]
|
|||
|
|
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (14#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:106]
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INFO: [Synth 8-256] done synthesizing module 'lpf' (15#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
|
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INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
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|
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
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Parameter C_SIZE bound to: 6 - type: integer
|
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INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (16#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
|
|||
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INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (17#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
|
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INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (18#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
|
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INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset_ip' (19#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:74]
|
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INFO: [Synth 8-6157] synthesizing module 'nf_datapath' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:44]
|
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Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
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Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
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Parameter C_BASEADDR bound to: 0 - type: integer
|
|||
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Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
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Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
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Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
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Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
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Parameter NUM_QUEUES bound to: 5 - type: integer
|
|||
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Parameter DIGEST_WIDTH bound to: 80 - type: integer
|
|||
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Parameter C_AXIS_TUSER_DIGEST_WIDTH bound to: 304 - type: integer
|
|||
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Parameter Q_SIZE_WIDTH bound to: 16 - type: integer
|
|||
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INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:194]
|
|||
|
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INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:195]
|
|||
|
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INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:196]
|
|||
|
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INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:197]
|
|||
|
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INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:198]
|
|||
|
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INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:199]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:201]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:202]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:203]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:204]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:205]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:206]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:209]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:210]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:211]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:212]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:213]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:321]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:322]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'input_arbiter_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/synth/input_arbiter_ip.v:57]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'input_arbiter' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:55]
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter NUM_QUEUES bound to: 5 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
Parameter C_BASEADDR bound to: 0 - type: integer
|
|||
|
|
Parameter NUM_QUEUES_WIDTH bound to: 3 - type: integer
|
|||
|
|
Parameter NUM_STATES bound to: 1 - type: integer
|
|||
|
|
Parameter IDLE bound to: 0 - type: integer
|
|||
|
|
Parameter WR_PKT bound to: 1 - type: integer
|
|||
|
|
Parameter MAX_PKT_SIZE bound to: 2000 - type: integer
|
|||
|
|
Parameter IN_FIFO_DEPTH_BIT bound to: 6 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'fallthrough_small_fifo' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/fallthrough_small_fifo.v:46]
|
|||
|
|
Parameter WIDTH bound to: 417 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 6 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'small_fifo' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:44]
|
|||
|
|
Parameter WIDTH bound to: 417 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 6 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 64 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'small_fifo' (20#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:44]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'fallthrough_small_fifo' (21#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/fallthrough_small_fifo.v:46]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'input_arbiter_cpu_regs' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:42]
|
|||
|
|
Parameter C_BASE_ADDRESS bound to: 0 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:305]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'input_arbiter_cpu_regs' (22#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:42]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'input_arbiter' (23#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:55]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'input_arbiter_ip' (24#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/synth/input_arbiter_ip.v:57]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'nf_sume_sdnet_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/synth/nf_sume_sdnet_ip.v:57]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'nf_sume_sdnet' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:44]
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 304 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
Parameter SDNET_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
Parameter DIGEST_WIDTH bound to: 256 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'sume_to_sdnet' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:41]
|
|||
|
|
Parameter FIRST bound to: 0 - type: integer
|
|||
|
|
Parameter WAIT bound to: 1 - type: integer
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:72]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'sume_to_sdnet' (25#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:41]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_line' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v:40]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_line' (26#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_lookup' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v:40]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_lookup' (27#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_control' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v:40]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_control' (28#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'TopParser_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v:169]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'TopParser_t' (181#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v:169]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'TopPipe_lvl_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v:172]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'TopPipe_lvl_t' (188#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v:172]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'dummy_table_for_netpfga_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/dummy_table_for_netpfga_t.v:36]
|
|||
|
|
Parameter K bound to: 48 - type: integer
|
|||
|
|
Parameter V bound to: 10 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_tdpram' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:467]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (190#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_tdpram' (191#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
|
|||
|
|
Warning: Trying to implement RAM in registers. Block RAM or DRAM implementation is not possible for one or more of the following reasons :
|
|||
|
|
1: Invalid write to RAM.
|
|||
|
|
2: Unable to determine number of words or word size in RAM.
|
|||
|
|
3: No valid read/write found for RAM.
|
|||
|
|
RAM dissolved into registers
|
|||
|
|
WARNING: [Synth 8-4767] Trying to implement RAM 'CamPtrBck_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
|
|||
|
|
Reason is one or more of the following :
|
|||
|
|
1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
|
|||
|
|
2: Unable to determine number of words or word size in RAM.
|
|||
|
|
3: No valid read/write found for RAM.
|
|||
|
|
RAM "CamPtrBck_reg" dissolved into registers
|
|||
|
|
WARNING: [Synth 8-4767] Trying to implement RAM 'CamPtrFwd_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
|
|||
|
|
Reason is one or more of the following :
|
|||
|
|
1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
|
|||
|
|
2: Unable to determine number of words or word size in RAM.
|
|||
|
|
3: No valid read/write found for RAM.
|
|||
|
|
RAM "CamPtrFwd_reg" dissolved into registers
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'dummy_table_for_netpfga_t' (204#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/dummy_table_for_netpfga_t.HDL/dummy_table_for_netpfga_t.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'TopPipe_lvl_0_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v:174]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'TopPipe_lvl_0_t' (226#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v:174]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'TopDeparser_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v:169]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'TopDeparser_t' (686#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v:169]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1651663213 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 48 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 128 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: std - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 48 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 3 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 48 - type: integer
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 48 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 128 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 48 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 3 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 48 - type: integer
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 12288 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 128 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 12288 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 48 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 48 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 48 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 48 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 48 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 48 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 48 - type: integer
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 48 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 48 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 48 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 48 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 48 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 48 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 48 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized0' (686#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
|
|
Parameter DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter INIT_SYNC_FF bound to: 1 - type: integer
|
|||
|
|
Parameter REG_OUTPUT bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 8 - type: integer
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (687#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
Parameter REG_WIDTH bound to: 8 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (688#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
|
|
Parameter DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter INIT_SYNC_FF bound to: 1 - type: integer
|
|||
|
|
Parameter REG_OUTPUT bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 9 - type: integer
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (688#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
Parameter REG_WIDTH bound to: 9 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (688#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1638]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1663]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055]
|
|||
|
|
Parameter DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter INIT bound to: 32'sb00000000000000000000000000000000
|
|||
|
|
Parameter INIT_SYNC_FF bound to: 1 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter DEF_VAL bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1107]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (689#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (690#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755]
|
|||
|
|
Parameter RST_VALUE bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (691#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (692#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 1 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (692#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (692#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (693#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async' (694#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request' (695#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_dummy_table_for_netpfga_tuple_in_request.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_PROTOCOL_ADAPTER_INGRESS' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:36]
|
|||
|
|
Parameter IDLE bound to: 1 - type: integer
|
|||
|
|
Parameter RX_SOF bound to: 2 - type: integer
|
|||
|
|
Parameter RX_SOF_EOF bound to: 3 - type: integer
|
|||
|
|
Parameter RX_PKT bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-4471] merging register 'tuple_out_control_VALID_reg' into 'packet_out_SOF_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:182]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element tuple_out_control_VALID_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:182]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_PROTOCOL_ADAPTER_INGRESS' (696#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_PROTOCOL_ADAPTER_EGRESS' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v:36]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_PROTOCOL_ADAPTER_EGRESS' (697#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_TopParser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-6104' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 136192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 129 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 129 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 136192 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 266 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 266 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 266 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 266 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 266 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 266 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 266 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 266 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 266 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 266 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 266 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 266 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 266 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized1' (697#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst__parameterized0' (697#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 10 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (697#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 1 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (697#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized4' (697#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-5772' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized0' (697#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync' (698#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: FWFT - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 512 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 127 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 127 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 2 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 512 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 1 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 1 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 1 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 1 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 1 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 1 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: yes - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 5 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 1 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element gen_rd_b.gen_doutb_pipe.enb_pipe_reg[0] was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:2588]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized2' (698#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 2 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized5' (698#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized1' (698#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized0' (698#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 32768 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 66 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 66 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 32768 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 128 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 128 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 128 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 128 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 128 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 128 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 128 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 128 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 128 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 128 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 128 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 128 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 128 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized3' (698#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized2' (698#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized0' (698#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 5120 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 5120 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 20 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 20 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 20 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 20 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 20 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 20 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 20 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 20 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 20 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 20 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 20 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 20 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: yes - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 20 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized4' (698#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized3' (698#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized1' (698#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element xhuoeccya3ga0mvk2fn6p_813_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:353]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element gh6q43ttyavjy6gwykfge9_754_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:341]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element hg81hwer7d792gfx_571_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:355]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element ecxabefqho4erjd1a_495_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:292]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_SYNCER_for_TopParser' (699#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 136192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 135 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 135 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized4' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized1' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: FWFT - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 512 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 133 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 133 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 2 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized5' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized2' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 359168 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 359168 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 1403 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 1403 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 1403 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 1403 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 1403 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 1403 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 1403 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 1403 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 1403 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 1403 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 1403 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 1403 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 1403 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized5' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized6' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized2' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 40960 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 40960 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 160 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 160 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 160 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 160 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 160 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 160 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 160 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 160 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 160 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 160 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 160 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 160 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 160 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized6' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized7' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized3' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized8' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 65536 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 65536 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 256 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 256 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 256 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 256 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 256 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 256 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 256 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 256 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 256 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 256 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 256 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 256 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized7' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized8' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized4' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized9' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 32768 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized9' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized5' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized10' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 8192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized8' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 8192 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: yes - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized8' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized10' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized6' (699#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element nneay6tkl9eghwmzlb6o45ewuyrb_362_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:557]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element ypuks2i89jrg0bm8hw3lbis_795_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:545]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element zykrkud3ec72q4ah_875_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:559]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element jdgm74vahg8fgalh5jl7lu_902_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:452]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser' (700#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_S_SYNCER_for_TopDeparser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized11' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 136192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 167 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 167 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized11' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized3' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: FWFT - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized12' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 512 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 165 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 165 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 2 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized12' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized4' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized13' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 65536 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized13' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized7' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized8' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized14' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 359168 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized14' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized8' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized9' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized15' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 4096 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized9' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 4096 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 16 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 16 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 16 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 16 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 16 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 16 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 16 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 16 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 16 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 16 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 16 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 16 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: yes - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 16 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized9' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized15' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized9' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized10' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 40960 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized16' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized10' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 32768 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized17' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized11' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 11 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 33 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 11 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 33 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 11 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 33 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 11 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 33 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 128 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 1408 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 33 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 33 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 125 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 125 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 8 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 8 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 1408 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 11 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 11 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 11 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 7 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 11 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 11 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 11 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 7 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 11 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 11 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 11 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 11 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 128 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 11 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 11 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 7 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 7 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 7 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 7 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: yes - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 11 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized10' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter INIT_SYNC_FF bound to: 1 - type: integer
|
|||
|
|
Parameter REG_OUTPUT bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 7 - type: integer
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized1' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
|
|
Parameter REG_WIDTH bound to: 7 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized1' (700#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 1 - type: integer
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 2 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 5120 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 84 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 84 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 8192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 84 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 84 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element nzjtu4zug1sug37afqq_126_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:659]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element sgr5jqi5lb8xolsvhv_125_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:647]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element jth9i5jh9dui8r21gc_400_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:661]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element babt2kvu9a59d16mnebku_549_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:532]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 136192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 143 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 143 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: FWFT - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 512 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 141 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 141 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 2 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 5120 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 72 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 72 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 8192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 72 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 72 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element ijiyaxd7a60vainv_117_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:557]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element vbimhawqr1e5w693kfobai_473_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:545]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element r13fxvdaeqoidg5l_556_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:559]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element o2qboohqi0d8p3hfc5rra5aa3ejjye_673_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:452]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 290 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 290 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 290 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 290 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 148480 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 135 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 135 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 148480 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 290 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 290 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 290 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 290 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 290 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 290 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 290 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 290 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 290 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 290 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 290 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 290 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 290 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 65536 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 66 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 66 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element xk3n5rc0kc8c2vgelk9gkz9n35k_798_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:302]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element hscw01tnwdcndpr9v65gr5a8yeug4f_851_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:300]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element c6lhz87iw5uddmz62_637_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:337]
|
|||
|
|
ERROR: [Synth 8-448] named port connection 'tuple_in_sume_metadata_VALID' does not exist for instance 'SimpleSumeSwitch_inst' of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:184]
|
|||
|
|
ERROR: [Synth 8-448] named port connection 'tuple_in_sume_metadata_DATA' does not exist for instance 'SimpleSumeSwitch_inst' of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:185]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'control_S_AXI_AWADDR' does not match port width (8) of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:189]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'control_S_AXI_ARADDR' does not match port width (8) of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:199]
|
|||
|
|
ERROR: [Synth 8-448] named port connection 'tuple_out_sume_metadata_VALID' does not exist for instance 'SimpleSumeSwitch_inst' of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:218]
|
|||
|
|
ERROR: [Synth 8-448] named port connection 'tuple_out_sume_metadata_DATA' does not exist for instance 'SimpleSumeSwitch_inst' of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:219]
|
|||
|
|
ERROR: [Synth 8-6156] failed synthesizing module 'nf_sume_sdnet' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:44]
|
|||
|
|
ERROR: [Synth 8-6156] failed synthesizing module 'nf_sume_sdnet_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/synth/nf_sume_sdnet_ip.v:57]
|
|||
|
|
ERROR: [Synth 8-6156] failed synthesizing module 'nf_datapath' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:44]
|
|||
|
|
ERROR: [Synth 8-6156] failed synthesizing module 'top' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:43]
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished RTL Elaboration : Time (s): cpu = 00:01:28 ; elapsed = 00:01:54 . Memory (MB): peak = 2437.414 ; gain = 1116.191 ; free physical = 8370 ; free virtual = 14073
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
RTL Elaboration failed
|
|||
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
|||
|
|
432 Infos, 163 Warnings, 0 Critical Warnings and 9 Errors encountered.
|
|||
|
|
synth_design failed
|
|||
|
|
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 21 13:22:42 2019...
|
|||
|
|
[Sun Jul 21 13:22:42 2019] synth finished
|
|||
|
|
wait_on_run: Time (s): cpu = 00:27:49 ; elapsed = 00:47:51 . Memory (MB): peak = 2875.852 ; gain = 0.000 ; free physical = 8922 ; free virtual = 14626
|
|||
|
|
# launch_runs impl_1 -to_step write_bitstream
|
|||
|
|
[Sun Jul 21 13:22:44 2019] Launched synth_1...
|
|||
|
|
Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth_1/runme.log
|
|||
|
|
[Sun Jul 21 13:22:44 2019] Launched impl_1...
|
|||
|
|
Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/runme.log
|
|||
|
|
# wait_on_run impl_1
|
|||
|
|
[Sun Jul 21 13:22:44 2019] Waiting for impl_1 to finish...
|
|||
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[Sun Jul 21 13:24:52 2019] impl_1 finished
|
|||
|
|
wait_on_run: Time (s): cpu = 00:01:40 ; elapsed = 00:02:08 . Memory (MB): peak = 2875.852 ; gain = 0.000 ; free physical = 8922 ; free virtual = 14627
|
|||
|
|
# exit
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 21 13:24:52 2019...
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
make -C hw export_to_sdk
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
rm -f ../hw/create_ip/id_rom16x32.coe
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
|
|||
|
|
echo 16028002 >> rom_data.txt
|
|||
|
|
echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt
|
|||
|
|
grep: ../../../RELEASE_NOTES: No such file or directory
|
|||
|
|
echo 00000204 >> rom_data.txt
|
|||
|
|
echo 0000FFFF >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py
|
|||
|
|
16
|
|||
|
|
|
|||
|
|
mv -f id_rom16x32.coe ../hw/create_ip/
|
|||
|
|
mv -f rom_data.txt ../hw/create_ip/
|
|||
|
|
if test -d project; then\
|
|||
|
|
echo "export simple_sume_switch project to SDK"; \
|
|||
|
|
vivado -mode tcl -source tcl/export_hardware.tcl -tclargs simple_sume_switch;\
|
|||
|
|
else \
|
|||
|
|
echo "Project simple_sume_switch does not exist.";\
|
|||
|
|
echo "Please run \"make project\" to create and build the project first";\
|
|||
|
|
fi;\
|
|||
|
|
|
|||
|
|
export simple_sume_switch project to SDK
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source tcl/export_hardware.tcl
|
|||
|
|
# set design [lindex $argv 0]
|
|||
|
|
# puts "\nOpening $design XPR project\n"
|
|||
|
|
|
|||
|
|
Opening simple_sume_switch XPR project
|
|||
|
|
|
|||
|
|
# open_project project/$design.xpr
|
|||
|
|
Scanning sources...
|
|||
|
|
Finished scanning sources
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
|
|||
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
|||
|
|
WARNING: [IP_Flow 19-3664] IP 'bd_7ad4_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-5509-nsg-System/coregen/bd_7ad4_xpcs_0_1/elaborate/configure_gt.tcl'. Please regenerate to continue.
|
|||
|
|
WARNING: [IP_Flow 19-3664] IP 'bd_a1aa_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-5509-nsg-System/coregen/bd_a1aa_xpcs_0_2/elaborate/configure_gt.tcl'. Please regenerate to continue.
|
|||
|
|
open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1365.707 ; gain = 188.977 ; free physical = 9649 ; free virtual = 15354
|
|||
|
|
# puts "\nOpening $design Implementation design\n"
|
|||
|
|
|
|||
|
|
Opening simple_sume_switch Implementation design
|
|||
|
|
|
|||
|
|
# open_run impl_1
|
|||
|
|
ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
|
|||
|
|
Vivado% quit
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 21 13:34:29 2019...
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
make -C sw/embedded/ project
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
|
|||
|
|
mkdir ./SDK_Workspace
|
|||
|
|
xsdk -batch -source ./tcl/simple_sume_switch_xsdk.tcl
|
|||
|
|
Starting xsdk. This could take few seconds... Eclipse: Cannot open display:
|
|||
|
|
done
|
|||
|
|
INFO: [Hsi 55-1698] elapsed time for repository loading 0 seconds
|