1325 lines
135 KiB
Plaintext
1325 lines
135 KiB
Plaintext
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+ date
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Son Jul 28 12:19:47 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
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actions_nat64_generic.p4(159): warning: Table nat64 is not used; removing
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table nat64 {
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^^^^^
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actions_nat64_generic.p4(178): warning: Table nat46 is not used; removing
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table nat46 {
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^^^^^
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minip4_solution.p4(91): warning: Table lookup_table is not used; removing
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table lookup_table {
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^^^^^^^^^^^^
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minip4_solution.p4(19): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates
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out metadata meta,
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^^^^
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minip4_solution.p4(16)
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parser RealParser(
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^^^^^^^^^^
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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./gen_testdata.py
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Applying pkt on nf0 at 1:
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Applying pkt on nf1 at 2:
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Applying pkt on nf2 at 3:
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Applying pkt on nf3 at 4:
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nf0_applied times: [1]
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nf1_applied times: [2]
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nf2_applied times: [3]
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nf3_applied times: [4]
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
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Xilinx SDNet Compiler version 2018.2, build 2342300
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Compilation successful
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_externs.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ ./testdata/ ./sw/ --base_address 0x44020000
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_API.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_CLI.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
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cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
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cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
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cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
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# The following command only applies if running P4_SWITCH Questa Simulation with Ubuntu
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sed -i 's/vsim/vsim \-ldflags \"\-B\/usr\/lib\/x86\_64\-linux-gnu\"/g' nf_sume_sdnet_ip/SimpleSumeSwitch/questa.bash
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# modify the P4_SWITCH_tb so that it writes the table configuration writes to a file
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/modify_P4_SWITCH_tb.py nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv
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# Fix introduced for SDNet 2017.4
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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# Fix introduced for SDNet 2018.2
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sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp testdata/*.axi nf_sume_sdnet_ip/SimpleSumeSwitch/
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+ date
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Son Jul 28 12:19:52 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch
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+ ./vivado_sim.bash
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+ find -name '*.v' -o -name '*.vp' -o -name '*.sv'
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+ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv %
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_TopPipe_fl_realmain_apply_v4networks_0
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_TopPipe_fl_realmain_apply_v6networks_0
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_act_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_0_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_v4_networks_0_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_v4_networks_0_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_v4_networks_0_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_3
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_3_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_3_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_3_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_2_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_2_sec_compute_user_metadata_task
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_2_sec_compute_user_metadata_ingress_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_2_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_2_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_2_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_2_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_2_sec_compute_user_metadata_table_id
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_2_sec_compute_user_metadata_task
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_2_sec_compute_user_metadata_ingress_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_2_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_2_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_2_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_2_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_2_sec_compute_user_metadata_task
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_2_sec_compute_user_metadata_ingress_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_2_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_2_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_2_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_2_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_2_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_2_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_2_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_and_mac_2_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_and_mac_2_sec_compute_p_ethernet_dst_addr
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_and_mac_2_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_and_mac_2_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_and_mac_2_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_4
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_realmain_v6_networks_0_req_lookup_request_key
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_condition_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_5
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_interm
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_interm_compute_local_state_id
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_interm_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_interm_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_interm_0
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_interm_0_compute_local_state_id
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_interm_0_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_interm_0_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_6
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_local_end_compute_control_increment_offset
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work
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INFO: [VRFC 10-311] analyzing module xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module xpm_counter_updn
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
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INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
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INFO: [VRFC 10-311] analyzing module xpm_fifo_async
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INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work
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INFO: [VRFC 10-311] analyzing module xpm_memory_base
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INFO: [VRFC 10-311] analyzing module asym_bwe_bb
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|||
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INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
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|||
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INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
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|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work
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INFO: [VRFC 10-311] analyzing module xpm_cdc_single
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|||
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
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|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|||
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work
|
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INFO: [VRFC 10-311] analyzing module glbl
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|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work
|
|||
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser
|
|||
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v6_networks_0_tuple_in_request.vp" into library work
|
|||
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv" into library work
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_fifo_base
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_counter_updn
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_fifo_async
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv" into library work
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_memory_base
|
|||
|
|
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v6_networks_0_tuple_in_request.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_v6_networks_0_tuple_in_request
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module glbl
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.vp" into library work
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_1_t.HDL/TopPipe_lvl_1_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_Engine
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_local_start_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_v6_networks_0_sec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_v6_networks_0_sec_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_v6_networks_0_sec_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_2
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_NoAction_0_sec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_NoAction_0_sec_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_NoAction_0_sec_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_sec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_sec_compute_user_metadata_task
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_sec_compute_user_metadata_ingress_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_sec_compute_sume_metadata_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_sec_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_sec_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_sec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_sec_compute_user_metadata_table_id
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_sec_compute_user_metadata_task
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_sec_compute_user_metadata_ingress_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_sec_compute_sume_metadata_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_sec_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_debug_table_id_sec_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_reply_sec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_reply_sec_compute_user_metadata_task
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_reply_sec_compute_user_metadata_ingress_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_reply_sec_compute_sume_metadata_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_reply_sec_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_controller_reply_sec_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_set_egress_port_and_mac_sec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_set_egress_port_and_mac_sec_compute_p_ethernet_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_set_egress_port_and_mac_sec_compute_sume_metadata_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_set_egress_port_and_mac_sec_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_set_egress_port_and_mac_sec_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_set_egress_port_sec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_set_egress_port_sec_compute_sume_metadata_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_set_egress_port_sec_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_realmain_set_egress_port_sec_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_EngineStage_3
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_sink
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_sink_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t_sink_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_1_t.HDL/TopPipe_lvl_1_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_1_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v6_networks_0_t.HDL/realmain_v6_networks_0_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Wrap
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_IntTop
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Lookup
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Hash_Lookup
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_RamR1RW1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Cam
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Update
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Hash_Update
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Randmod4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Randmod4_Rnd
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Randmod5
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_Randmod5_Rnd
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t_csr
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v6_networks_0_t.HDL/xpm_memory.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_base
|
|||
|
|
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v6_networks_0_t.HDL/xpm_cdc.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v6_networks_0_t.HDL/realmain_v6_networks_0_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v6_networks_0_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_realmain_v4_networks_0_req_lookup_request_key_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp" into library work
|
|||
|
|
ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TB_System_Stim
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module Check
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch_tb
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library work
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM
|
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_0_sec
|
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_0_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_0_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck
|
|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert
|
|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_dst_addr
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|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_src_addr
|
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_ethertype
|
|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection
|
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset
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|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor
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|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter
|
|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo
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|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM
|
|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer
|
|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo
|
|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM
|
|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM
|
|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown
|
|||
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INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_base
|
|||
|
|
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_cdc.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/realmain_v4_networks_0_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Wrap
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_IntTop
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Lookup
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Hash_Lookup
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_RamR1RW1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Cam
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Update
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Hash_Update
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod4_Rnd
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod5
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod5_Rnd
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_csr
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/realmain_v4_networks_0_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_RESETTER_line
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_RESETTER_control
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_Engine
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv4_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv6_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_tcp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_udp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_cpu_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_na_ns_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_arp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dma_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf3_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf2_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf1_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf0_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_send_dig_to_cpu
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_drop
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_pkt_len
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_ethertype
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_digest_data_1_unused
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_ethertype
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_version
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ihl
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_diff_serv
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ecn
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_totalLen
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_identification
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_flags
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_fragOffset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ttl
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_protocol
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_version
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_traffic_class
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_flow_label
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_payload_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_next_header
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_hop_limit
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_seqNo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ackNo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_data_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_res
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_cwr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ece
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_urg
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ack
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_psh
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_syn
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_fin
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_window
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_urgentPtr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_payload_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_code
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_task
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_ingress_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_ethertype
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_table_id
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_code
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_router
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_solicitated
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_override
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_reserved
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_target_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_ll_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_hw_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_protocol
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_hw_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_protocol_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_opcode
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_src_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_src_ipv4_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_dst_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_dst_ipv4_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_ingress_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_task
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_switch_task
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp6_na_ns
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_ipv4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_udp_v4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_udp_v6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_tcp_v4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_tcp_v6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_length_without_ip_header
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_cast_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_v4sum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_v6sum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_headerdiff
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_table_id
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_digest_data_unused
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_dma_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf3_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf2_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf1_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf0_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_send_dig_to_cpu
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_drop
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_pkt_len
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_reject
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_accept
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp" into library work
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp" into library work
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch
|
|||
|
|
+ true
|
|||
|
|
+ mkdir -p xsim.dir/xsc
|
|||
|
|
+ find -name '*.c'
|
|||
|
|
+ xargs /opt/Xilinx/Vivado/2018.2/bin/xsc -mt off -v 1
|
|||
|
|
Turned off multi-threading.
|
|||
|
|
Running compilation flow
|
|||
|
|
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR
|
|||
|
|
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/user.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -DXILINX_SIMULATOR
|
|||
|
|
./Testbench/user.c: In function ‘register_write_control’:
|
|||
|
|
./Testbench/user.c:39:5: warning: implicit declaration of function ‘SV_write_control’ [-Wimplicit-function-declaration]
|
|||
|
|
SV_write_control(&sv_addr, &sv_data);
|
|||
|
|
^~~~~~~~~~~~~~~~
|
|||
|
|
./Testbench/user.c: In function ‘register_read_control’:
|
|||
|
|
./Testbench/user.c:53:5: warning: implicit declaration of function ‘SV_read_control’ [-Wimplicit-function-declaration]
|
|||
|
|
SV_read_control(&sv_addr, &sv_data);
|
|||
|
|
^~~~~~~~~~~~~~~
|
|||
|
|
./Testbench/user.c: In function ‘CAM_Init’:
|
|||
|
|
./Testbench/user.c:101:76: warning: passing argument 9 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
|
|||
|
|
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
|
|||
|
|
^~~~~~~~~~~~~~
|
|||
|
|
In file included from ./Testbench/user.c:7:0:
|
|||
|
|
./Testbench/CAM.h:169:5: note: expected ‘void (*)(addr_t, uint32_t) {aka void (*)(long long unsigned int, unsigned int)}’ but argument is of type ‘void (*)(uint32_t, uint32_t) {aka void (*)(unsigned int, unsigned int)}’
|
|||
|
|
int CAM_Init_ValidateContext(
|
|||
|
|
^~~~~~~~~~~~~~~~~~~~~~~~
|
|||
|
|
./Testbench/user.c:101:92: warning: passing argument 10 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
|
|||
|
|
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
|
|||
|
|
^~~~~~~~~~~~~
|
|||
|
|
In file included from ./Testbench/user.c:7:0:
|
|||
|
|
./Testbench/CAM.h:169:5: note: expected ‘uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)}’ but argument is of type ‘uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}’
|
|||
|
|
int CAM_Init_ValidateContext(
|
|||
|
|
^~~~~~~~~~~~~~~~~~~~~~~~
|
|||
|
|
Done compilation
|
|||
|
|
Linking with command:
|
|||
|
|
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/
|
|||
|
|
|
|||
|
|
Running command : /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/
|
|||
|
|
Done linking: "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so"
|
|||
|
|
+ /opt/Xilinx/Vivado/2018.2/bin/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
|
|||
|
|
Vivado Simulator 2018.2
|
|||
|
|
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
|
|||
|
|
Multi-threading is on. Using 6 slave threads.
|
|||
|
|
Starting static elaboration
|
|||
|
|
Completed static elaboration
|
|||
|
|
Starting simulation data flow analysis
|
|||
|
|
Completed simulation data flow analysis
|
|||
|
|
Time Resolution for simulation is 1ps
|
|||
|
|
Compiling module work.S_RESETTER_line
|
|||
|
|
Compiling module work.S_RESETTER_lookup
|
|||
|
|
Compiling module work.S_RESETTER_control
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_0_ErrorC...
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_0_Extrac...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ethe...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ethe...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ethe...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ethe...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_udp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_udp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_udp_...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_udp_...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_udp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_cpu_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_cpu_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_cpu_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_cpu_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_cpu_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_arp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_arp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_arp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_arp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_arp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_arp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_arp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_arp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_arp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_arp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_digest...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_sume_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_sume_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_sume_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_sume_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_sume_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_sume_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_sume_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_sume_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_sume_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_sume_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_contro...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_contro...
|
|||
|
|
Compiling module work.TopParser_t_start
|
|||
|
|
Compiling module work.TopParser_t_reject_compute_contr...
|
|||
|
|
Compiling module work.TopParser_t_reject_compute_contr...
|
|||
|
|
Compiling module work.TopParser_t_reject
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_0_TupleF...
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_0
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_1_ErrorC...
|
|||
|
|
Compiling module work.TopParser_t_accept_compute_contr...
|
|||
|
|
Compiling module work.TopParser_t_accept_compute_contr...
|
|||
|
|
Compiling module work.TopParser_t_accept
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_1
|
|||
|
|
Compiling module work.TopParser_t_Engine
|
|||
|
|
Compiling module work.TopParser_t
|
|||
|
|
Compiling module work.TopPipe_lvl_t_setup_compute_real...
|
|||
|
|
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
|
|||
|
|
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
|
|||
|
|
Compiling module work.TopPipe_lvl_t_setup
|
|||
|
|
Compiling module work.TopPipe_lvl_t_EngineStage_0
|
|||
|
|
Compiling module work.TopPipe_lvl_t_Engine
|
|||
|
|
Compiling module work.TopPipe_lvl_t
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Hash_Lo...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_SIZE=2160...
|
|||
|
|
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=21...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_RamR1RW...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Cam
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Lookup
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Hash_Up...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Update
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_IntTop
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Wrap
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_csr
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_act_sec_compute_...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_act_sec_compute_...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_act_sec_compute_...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_act_sec_compute_...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_act_sec
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_EngineStage_0
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_condition_sec_0_...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_condition_sec_0_...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_condition_sec_0
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_EngineStage_1
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_v4_netw...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_v4_netw...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_v4_netw...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_EngineStage_2
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_NoAction_3_sec_c...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_NoAction_3_sec_c...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_NoAction_3_sec
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_set_egr...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_set_egr...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_set_egr...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_set_egr...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_set_egr...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_set_egr...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_set_egr...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_set_egr...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_set_egr...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_EngineStage_3
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_condition_sec_co...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_condition_sec_co...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_condition_sec_co...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_condition_sec
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_EngineStage_4
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_interm_compute_l...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_interm_compute_c...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_interm_compute_c...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_interm
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_interm_0_compute...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_interm_0_compute...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_interm_0_compute...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_interm_0
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_EngineStage_5
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_local_end_comput...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_local_end_comput...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_local_end
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_EngineStage_6
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_Engine
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_Hash_Lo...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_SIZE=3696...
|
|||
|
|
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=36...
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_RamR1RW...
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_Cam
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_Lookup
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_Hash_Up...
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_Update
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_IntTop
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_Wrap
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t_csr
|
|||
|
|
Compiling module work.realmain_v6_networks_0_t
|
|||
|
|
Compiling module work.TopPipe_lvl_1_t_local_start_comp...
|
|||
|
|
Compiling module work.TopPipe_lvl_1_t_local_start_comp...
|
|||
|
|
Compiling module work.TopPipe_lvl_1_t_local_start
|
|||
|
|
Compiling module work.TopPipe_lvl_1_t_EngineStage_0
|
|||
|
|
Compiling module work.TopPipe_lvl_1_t_realmain_v6_netw...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_v6_netw...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_v6_netw...
|
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Compiling module work.TopPipe_lvl_1_t_EngineStage_1
|
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Compiling module work.TopPipe_lvl_1_t_NoAction_0_sec_c...
|
|||
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Compiling module work.TopPipe_lvl_1_t_NoAction_0_sec_c...
|
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Compiling module work.TopPipe_lvl_1_t_NoAction_0_sec
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_control...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_set_egr...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_set_egr...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_set_egr...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_set_egr...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_set_egr...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_set_egr...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_set_egr...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_set_egr...
|
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Compiling module work.TopPipe_lvl_1_t_realmain_set_egr...
|
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|
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Compiling module work.TopPipe_lvl_1_t_EngineStage_2
|
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|
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Compiling module work.TopPipe_lvl_1_t_sink_compute_con...
|
|||
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Compiling module work.TopPipe_lvl_1_t_sink_compute_con...
|
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Compiling module work.TopPipe_lvl_1_t_sink
|
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|
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Compiling module work.TopPipe_lvl_1_t_EngineStage_3
|
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Compiling module work.TopPipe_lvl_1_t_Engine
|
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Compiling module work.TopPipe_lvl_1_t
|
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Compiling module work.TopDeparser_t_EngineStage_0_Erro...
|
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Compiling module work.TopDeparser_t_extract_headers_se...
|
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Compiling module work.TopDeparser_t_extract_headers_se...
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Compiling module work.TopDeparser_t_extract_headers_se...
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Compiling module work.TopDeparser_t_extract_headers_se...
|
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_0_Edit...
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Compiling module work.TopDeparser_t_EngineStage_0
|
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Compiling module work.TopDeparser_t_EngineStage_1_Erro...
|
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Compiling module work.TopDeparser_t_act_0_sec_compute_...
|
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Compiling module work.TopDeparser_t_act_0_sec_compute_...
|
|||
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Compiling module work.TopDeparser_t_act_0_sec
|
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Compiling module work.TopDeparser_t_EngineStage_1
|
|||
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Compiling module work.TopDeparser_t_EngineStage_2_Erro...
|
|||
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Compiling module work.TopDeparser_t_emit_0_compute_con...
|
|||
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Compiling module work.TopDeparser_t_emit_0_compute__ST...
|
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Compiling module work.TopDeparser_t_emit_0_compute__ST...
|
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Compiling module work.TopDeparser_t_emit_0_compute__ST...
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Compiling module work.TopDeparser_t_emit_0_compute_con...
|
|||
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Compiling module work.TopDeparser_t_emit_0_compute_con...
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|||
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Compiling module work.TopDeparser_t_emit_0
|
|||
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
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Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|||
|
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Compiling module work.TopDeparser_t_EngineStage_2
|
|||
|
|
Compiling module work.TopDeparser_t_Engine
|
|||
|
|
Compiling module work.TopDeparser_t
|
|||
|
|
Compiling module work.xpm_cdc_sync_rst(DEST_SYNC_FF=2,...
|
|||
|
|
Compiling module work.xpm_fifo_rst(COMMON_CLOCK=0)
|
|||
|
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Compiling module work.xpm_fifo_reg_bit
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
|
|||
|
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
|
|||
|
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
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Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
|
|||
|
|
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=8)
|
|||
|
|
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
|
|||
|
|
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=9)
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.S_BRIDGER_for_realmain_v4_networ...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.S_BRIDGER_for_realmain_v6_networ...
|
|||
|
|
Compiling module work.S_PROTOCOL_ADAPTER_INGRESS
|
|||
|
|
Compiling module work.S_PROTOCOL_ADAPTER_EGRESS
|
|||
|
|
Compiling module work.xpm_fifo_rst_default
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1...
|
|||
|
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
|
|||
|
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=2...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.S_SYNCER_for_TopParser
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7...
|
|||
|
|
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=7...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
|
|||
|
|
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=7)
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.S_SYNCER_for_S_SYNCER_for_TopDep...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.S_SYNCER_for_TopDeparser
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
|
|||
|
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|||
|
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|||
|
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|||
|
|
Compiling module work.S_SYNCER_for__OUT_
|
|||
|
|
Compiling module work.S_CONTROLLER_SimpleSumeSwitch
|
|||
|
|
Compiling module work.SimpleSumeSwitch
|
|||
|
|
Compiling module work.TB_System_Stim
|
|||
|
|
Compiling module work.Check
|
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Compiling module work.SimpleSumeSwitch_tb
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Compiling module work.glbl
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Built simulation snapshot work.SimpleSumeSwitch_tb#work.glbl
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****** Webtalk v2018.2 (64-bit)
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/xsim_webtalk.tcl -notrace
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INFO: [Common 17-186] '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Sun Jul 28 12:20:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html.
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INFO: [Common 17-206] Exiting Webtalk at Sun Jul 28 12:20:45 2019...
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+ /opt/Xilinx/Vivado/2018.2/bin/xsim --runall SimpleSumeSwitch_tb#work.glbl
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****** xsim v2018.2 (64-bit)
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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source xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsim_script.tcl
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# xsim {work.SimpleSumeSwitch_tb#work.glbl} -autoloadwcfg -runall
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Vivado Simulator 2018.2
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Time resolution is 1 ps
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run -all
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_373 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_373 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_373 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_373 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_373 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v6_networks_0.realmain_v6_networks_0_t_Wrap_inst.realmain_v6_networks_0_t_IntTop_inst.realmain_v6_networks_0_t_Lookup_inst.realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v6_networks_0/realmain_v6_networks_0_t_Wrap_inst/realmain_v6_networks_0_t_IntTop_inst/realmain_v6_networks_0_t_Lookup_inst/realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_700 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v6_networks_0.realmain_v6_networks_0_t_Wrap_inst.realmain_v6_networks_0_t_IntTop_inst.realmain_v6_networks_0_t_Lookup_inst.realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v6_networks_0/realmain_v6_networks_0_t_Wrap_inst/realmain_v6_networks_0_t_IntTop_inst/realmain_v6_networks_0_t_Lookup_inst/realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_700 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v6_networks_0.realmain_v6_networks_0_t_Wrap_inst.realmain_v6_networks_0_t_IntTop_inst.realmain_v6_networks_0_t_Lookup_inst.realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v6_networks_0/realmain_v6_networks_0_t_Wrap_inst/realmain_v6_networks_0_t_IntTop_inst/realmain_v6_networks_0_t_Lookup_inst/realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_700 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v6_networks_0.realmain_v6_networks_0_t_Wrap_inst.realmain_v6_networks_0_t_IntTop_inst.realmain_v6_networks_0_t_Lookup_inst.realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v6_networks_0/realmain_v6_networks_0_t_Wrap_inst/realmain_v6_networks_0_t_IntTop_inst/realmain_v6_networks_0_t_Lookup_inst/realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_700 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v6_networks_0.realmain_v6_networks_0_t_Wrap_inst.realmain_v6_networks_0_t_IntTop_inst.realmain_v6_networks_0_t_Lookup_inst.realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v6_networks_0/realmain_v6_networks_0_t_Wrap_inst/realmain_v6_networks_0_t_IntTop_inst/realmain_v6_networks_0_t_Lookup_inst/realmain_v6_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_700 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1456 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_v6_networks_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_v6_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1546 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.hn7tg2be77xfzkfqncvjgacn419yjz_1328.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/hn7tg2be77xfzkfqncvjgacn419yjz_1328/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1635 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.c3zv44su8u6h2xjngp2av_2217.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/c3zv44su8u6h2xjngp2av_2217/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1665 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.hhpgyko3qx2ggcdd8efgmr2z_2441.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/hhpgyko3qx2ggcdd8efgmr2z_2441/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1729 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.ych9gc7yv8b8fze2j6hh2_842.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/ych9gc7yv8b8fze2j6hh2_842/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1813 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.chf7zkihatf0l50hd0_2473.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/chf7zkihatf0l50hd0_2473/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1635 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.xjahnteqg889wxfb6_2089.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xjahnteqg889wxfb6_2089/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1665 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.jj8sga0hak6dp8n010dj28jczypjt7wa_1571.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jj8sga0hak6dp8n010dj28jczypjt7wa_1571/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1994 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v1qmm2shxbspt3pj8d52n9953_300.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/v1qmm2shxbspt3pj8d52n9953_300/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2078 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.oeeyu6unkuol1e4yinypaz57j5ryhq5_1803.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/oeeyu6unkuol1e4yinypaz57j5ryhq5_1803/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2162 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.dtd6ia8n2i19nrc8ya_2294.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dtd6ia8n2i19nrc8ya_2294/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1729 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.vgmirdwto0o8oa4mz_791.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgmirdwto0o8oa4mz_791/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1813 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.qblwfn2objfmo1ec0tejvrr9wr_1679.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/qblwfn2objfmo1ec0tejvrr9wr_1679/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2414 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.yehlpwj1gavko3mzctgmspt2rlg63ur_1815.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/yehlpwj1gavko3mzctgmspt2rlg63ur_1815/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1635 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.gxymuce2k3jr835uqw0kt8e80f_594.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/gxymuce2k3jr835uqw0kt8e80f_594/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1665 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.yp5xnukqbvq0enlmbjedny97gsk1is_1068.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/yp5xnukqbvq0enlmbjedny97gsk1is_1068/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2601 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.kej98xq2asvvaoywtd2weu0_2246.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/kej98xq2asvvaoywtd2weu0_2246/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2162 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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|||
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.ojofyus1jlp65j0vjl6o1i5ax_2014.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/ojofyus1jlp65j0vjl6o1i5ax_2014/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2769 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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|||
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.lav6fui1c2q0e380_1770.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lav6fui1c2q0e380_1770/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1994 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.hi9xp03wdcmu1dzymkbf4i1c3oc_1548.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/hi9xp03wdcmu1dzymkbf4i1c3oc_1548/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1729 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.uu51oc216ge5ljed8mxxlo_1739.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/uu51oc216ge5ljed8mxxlo_1739/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2078 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.lfrgk10z8a391kty9fmo7mjjze67cejq_1783.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lfrgk10z8a391kty9fmo7mjjze67cejq_1783/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3105 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.fq9xhshf5vwj9i3bhlj3r_397.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/fq9xhshf5vwj9i3bhlj3r_397/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1813 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.lybukudarejpb27erg12gn7b3f_685.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/lybukudarejpb27erg12gn7b3f_685/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2414 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.zx0tu2v131nvlrpgew0i5gpkauetd_74.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/zx0tu2v131nvlrpgew0i5gpkauetd_74/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1635 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.sq22539fc1zlkw5z_1949.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/sq22539fc1zlkw5z_1949/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1665 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.ws5erxml6z6sr1auxd6e41waasb4_1309.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/ws5erxml6z6sr1auxd6e41waasb4_1309/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2601 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.krveodplucnelnfrfae85bsooc_1883.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/krveodplucnelnfrfae85bsooc_1883/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2162 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.nnbzuky8cfhgjzsh7l8sm2x0ag6a_1314.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/nnbzuky8cfhgjzsh7l8sm2x0ag6a_1314/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2769 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.b32rapxmrb43ovrgten_610.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/b32rapxmrb43ovrgten_610/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1994 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.z24gjabzh6cqhq14hgakls5ifv71gozy_1098.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/z24gjabzh6cqhq14hgakls5ifv71gozy_1098/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3800 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.jrb3667qq44ic748e0v_1568.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/jrb3667qq44ic748e0v_1568/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1729 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.qffjigwip2ypf5ywkrgzxu1eygnvns_439.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/qffjigwip2ypf5ywkrgzxu1eygnvns_439/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2078 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.jfqwyfaew5npmy4av04d_813.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/jfqwyfaew5npmy4av04d_813/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3105 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.m7zxbvm1kviyza28v7s8wjgf8vwe8rv_792.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/m7zxbvm1kviyza28v7s8wjgf8vwe8rv_792/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1813 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.jo89gjmsn19kd23j3x_1762.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/jo89gjmsn19kd23j3x_1762/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2414 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.zs33d9z7cx8cybukro3olskzl94nao_1345.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/zs33d9z7cx8cybukro3olskzl94nao_1345/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1635 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.akv07ba2dz6d0hpgzopgluiwi_2263.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/akv07ba2dz6d0hpgzopgluiwi_2263/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1665 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.j41d9pve0k47e5vnw_2057.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/j41d9pve0k47e5vnw_2057/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1994 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.wy4xai6dexsonpy7k4xq_1343.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/wy4xai6dexsonpy7k4xq_1343/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2078 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.desht1fkchtf15u6ekuwjg317qlq_2629.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/desht1fkchtf15u6ekuwjg317qlq_2629/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2162 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.islagwtslolkgwcvo_739.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/islagwtslolkgwcvo_739/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1729 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.nf4sl87zupt8h8orx37ngn2_1448.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/nf4sl87zupt8h8orx37ngn2_1448/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1813 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.d2i8g85a2s8zdj4dbbacanxz8xdktgv_986.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/d2i8g85a2s8zdj4dbbacanxz8xdktgv_986/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2414 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.w26rfcwenk2j568atytdc7g5pza_25.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/w26rfcwenk2j568atytdc7g5pza_25/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_4904 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.q4fvkl5jlfpgp4v8t_522.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/q4fvkl5jlfpgp4v8t_522/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1665 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.ub65okipkiesmj95bqaqtg_1785.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/ub65okipkiesmj95bqaqtg_1785/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2162 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.ygubwigw7cpymzybgwq_235.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/ygubwigw7cpymzybgwq_235/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1729 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
[SW] CAM_Init() - start
|
|||
|
|
[SW] CAM_Init() - done
|
|||
|
|
[SW] CAM_EnableDevice() - start
|
|||
|
|
SV_write_control()- start
|
|||
|
|
SV_write_control()- done
|
|||
|
|
SV_read_control()- start
|
|||
|
|
SV_read_control()- done
|
|||
|
|
SV_write_control()- start
|
|||
|
|
SV_write_control()- done
|
|||
|
|
[SW] CAM_EnableDevice() - done
|
|||
|
|
[SW] CAM_Init() - start
|
|||
|
|
SV_write_control()- start
|
|||
|
|
[SW] CAM_Init() - done
|
|||
|
|
[SW] CAM_EnableDevice() - start
|
|||
|
|
SV_write_control()- done
|
|||
|
|
SV_read_control()- start
|
|||
|
|
SV_read_control()- done
|
|||
|
|
SV_write_control()- start
|
|||
|
|
SV_write_control()- done
|
|||
|
|
[SW] CAM_EnableDevice() - done
|
|||
|
|
[2520658] INFO: finished packet stimulus file
|
|||
|
|
[3115420] ERROR: tuple mismatch for packet 1
|
|||
|
|
expected < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
|
|||
|
|
actual < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000004010000 >
|
|||
|
|
$finish called at time : 3115420 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" Line 120
|
|||
|
|
exit
|
|||
|
|
INFO: [Common 17-206] Exiting xsim at Sun Jul 28 12:20:56 2019...
|
|||
|
|
+ grep ^expected /home/nico/master-thesis/netpfga/log/compile-2019-07-28-121947-6.8-egress-only
|
|||
|
|
+ sed -e s/.*= <// -e s/.*= (//
|
|||
|
|
+ expected_line= 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
|
|||
|
|
+ grep ^actual /home/nico/master-thesis/netpfga/log/compile-2019-07-28-121947-6.8-egress-only
|
|||
|
|
+ sed -e s/.*= <// -e s/.*= (//
|
|||
|
|
+ actual_line= 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000004010000 >
|
|||
|
|
+ [ 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 > != 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000004010000 > ]
|
|||
|
|
+ echo packet mismatch
|
|||
|
|
packet mismatch
|
|||
|
|
+ exit 1
|