20963 lines
3 MiB
Text
20963 lines
3 MiB
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+ date
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Son Jul 28 16:58:15 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
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actions_egress.p4(51): warning: Table v6_networks is not used; removing
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table v6_networks {
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^^^^^^^^^^^
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actions_nat64_generic.p4(159): warning: Table nat64 is not used; removing
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table nat64 {
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^^^^^
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actions_nat64_generic.p4(178): warning: Table nat46 is not used; removing
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table nat46 {
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^^^^^
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minip4_solution.p4(19): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates
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out metadata meta,
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^^^^
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minip4_solution.p4(16)
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parser RealParser(
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^^^^^^^^^^
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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./gen_testdata.py
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Applying pkt on nf0 at 1:
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Applying pkt on nf1 at 2:
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Applying pkt on nf2 at 3:
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Applying pkt on nf3 at 4:
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nf0_applied times: [1]
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nf1_applied times: [2]
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nf2_applied times: [3]
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nf3_applied times: [4]
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
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Xilinx SDNet Compiler version 2018.2, build 2342300
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Compilation successful
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_externs.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ ./testdata/ ./sw/ --base_address 0x44020000
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_API.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_CLI.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
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cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
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cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
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cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
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# The following command only applies if running P4_SWITCH Questa Simulation with Ubuntu
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sed -i 's/vsim/vsim \-ldflags \"\-B\/usr\/lib\/x86\_64\-linux-gnu\"/g' nf_sume_sdnet_ip/SimpleSumeSwitch/questa.bash
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# modify the P4_SWITCH_tb so that it writes the table configuration writes to a file
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/modify_P4_SWITCH_tb.py nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv
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# Fix introduced for SDNet 2017.4
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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# Fix introduced for SDNet 2018.2
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sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp testdata/*.axi nf_sume_sdnet_ip/SimpleSumeSwitch/
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+ date
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Son Jul 28 16:58:19 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch
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+ ./vivado_sim.bash
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+ find -name '*.v' -o -name '*.vp' -o -name '*.sv'
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+ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv %
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_v4_networks_0_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_v4_networks_0_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_v4_networks_0_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_0_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_0_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_NoAction_0_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_user_metadata_task
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_user_metadata_ingress_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_user_metadata_table_id
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_user_metadata_task
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_user_metadata_ingress_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_debug_table_id_sec_compute_control_increment_offset
|
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|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_sec
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_sec_compute_user_metadata_task
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_sec_compute_user_metadata_ingress_port
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_sec_compute_sume_metadata_dst_port
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_sec_compute_control_nextSection
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_controller_reply_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_and_mac_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_and_mac_sec_compute_p_ethernet_dst_addr
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_and_mac_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_and_mac_sec_compute_control_nextSection
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_and_mac_sec_compute_control_increment_offset
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_sec
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_sec_compute_sume_metadata_dst_port
|
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|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_sec_compute_control_nextSection
|
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|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_realmain_set_egress_port_sec_compute_control_increment_offset
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_nextSection
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_increment_offset
|
|||
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
|
|||
|
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
|
|||
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work
|
|||
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
|
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser
|
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|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_fifo_base
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_counter_updn
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_fifo_async
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
|
|||
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_base
|
|||
|
|
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work
|
|||
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INFO: [VRFC 10-311] analyzing module glbl
|
|||
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
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|||
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv" into library work
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_base
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|||
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INFO: [VRFC 10-311] analyzing module asym_bwe_bb
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv" into library work
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
|
|||
|
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INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|||
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INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|||
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v" into library work
|
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.v" into library work
|
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INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.vp" into library work
|
|||
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library work
|
|||
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine
|
|||
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_realmain_v4_networks_0_req_lookup_request_key
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection
|
|||
|
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library work
|
|||
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp" into library work
|
|||
|
|
ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library work
|
|||
|
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INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v" into library work
|
|||
|
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INFO: [VRFC 10-311] analyzing module TB_System_Stim
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module Check
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch_tb
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_ethertype
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopDeparser_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_base
|
|||
|
|
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_cdc.sv" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/realmain_v4_networks_0_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Wrap
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_IntTop
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Lookup
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Hash_Lookup
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_RamR1RW1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Cam
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Update
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Hash_Update
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod4_Rnd
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod5
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_Randmod5_Rnd
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t_csr
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/realmain_v4_networks_0_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module realmain_v4_networks_0_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_RESETTER_line
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_RESETTER_control
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_Engine
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv4_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ipv6_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_tcp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_udp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_cpu_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_na_ns_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_arp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dma_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf3_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf2_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf1_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_nf0_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_send_dig_to_cpu
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_drop
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_standard_metadata_pkt_len
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_hdr_1_ethernet_ethertype
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_fl_digest_data_1_unused
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ethernet_ethertype
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_version
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ihl
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_diff_serv
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ecn
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_totalLen
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_identification
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_flags
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_fragOffset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_ttl
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_protocol
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv4_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_version
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_traffic_class
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_flow_label
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_payload_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_next_header
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_hop_limit
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_src_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_ipv6_dst_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_seqNo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ackNo
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_data_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_res
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_cwr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ece
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_urg
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_ack
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_psh
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_rst
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_syn
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_fin
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_window
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_tcp_urgentPtr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_payload_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_udp_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_code
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_task
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_ingress_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_ethertype
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_cpu_table_id
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_code
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_checksum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_router
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_solicitated
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_override
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_reserved
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_na_ns_target_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_ll_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_icmp6_option_link_layer_addr_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_isValid
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_hw_type
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_protocol
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_hw_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_protocol_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_opcode
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_src_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_src_ipv4_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_dst_mac_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_p_arp_dst_ipv4_addr
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_ingress_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_task
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_switch_task
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp6_na_ns
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_icmp
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_ipv4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_udp_v4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_udp_v6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_tcp_v4
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_chk_tcp_v6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_length_without_ip_header
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_cast_length
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_v4sum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_v6sum
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_headerdiff
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_table_id
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_digest_data_unused
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_dma_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf3_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf2_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf1_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_nf0_q_size
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_send_dig_to_cpu
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_drop
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_dst_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_src_port
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_sume_metadata_pkt_len
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_reject
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_accept
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module TopParser_t
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp" into library work
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp" into library work
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library work
|
|||
|
|
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch
|
|||
|
|
+ true
|
|||
|
|
+ mkdir -p xsim.dir/xsc
|
|||
|
|
+ find -name '*.c'
|
|||
|
|
+ xargs /opt/Xilinx/Vivado/2018.2/bin/xsc -mt off -v 1
|
|||
|
|
Turned off multi-threading.
|
|||
|
|
Running compilation flow
|
|||
|
|
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR
|
|||
|
|
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/user.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -DXILINX_SIMULATOR
|
|||
|
|
./Testbench/user.c: In function ‘register_write_control’:
|
|||
|
|
./Testbench/user.c:37:5: warning: implicit declaration of function ‘SV_write_control’ [-Wimplicit-function-declaration]
|
|||
|
|
SV_write_control(&sv_addr, &sv_data);
|
|||
|
|
^~~~~~~~~~~~~~~~
|
|||
|
|
./Testbench/user.c: In function ‘register_read_control’:
|
|||
|
|
./Testbench/user.c:51:5: warning: implicit declaration of function ‘SV_read_control’ [-Wimplicit-function-declaration]
|
|||
|
|
SV_read_control(&sv_addr, &sv_data);
|
|||
|
|
^~~~~~~~~~~~~~~
|
|||
|
|
./Testbench/user.c: In function ‘CAM_Init’:
|
|||
|
|
./Testbench/user.c:88:76: warning: passing argument 9 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
|
|||
|
|
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
|
|||
|
|
^~~~~~~~~~~~~~
|
|||
|
|
In file included from ./Testbench/user.c:7:0:
|
|||
|
|
./Testbench/CAM.h:169:5: note: expected ‘void (*)(addr_t, uint32_t) {aka void (*)(long long unsigned int, unsigned int)}’ but argument is of type ‘void (*)(uint32_t, uint32_t) {aka void (*)(unsigned int, unsigned int)}’
|
|||
|
|
int CAM_Init_ValidateContext(
|
|||
|
|
^~~~~~~~~~~~~~~~~~~~~~~~
|
|||
|
|
./Testbench/user.c:88:92: warning: passing argument 10 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
|
|||
|
|
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
|
|||
|
|
^~~~~~~~~~~~~
|
|||
|
|
In file included from ./Testbench/user.c:7:0:
|
|||
|
|
./Testbench/CAM.h:169:5: note: expected ‘uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)}’ but argument is of type ‘uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}’
|
|||
|
|
int CAM_Init_ValidateContext(
|
|||
|
|
^~~~~~~~~~~~~~~~~~~~~~~~
|
|||
|
|
Done compilation
|
|||
|
|
Linking with command:
|
|||
|
|
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/
|
|||
|
|
|
|||
|
|
Running command : /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/
|
|||
|
|
Done linking: "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so"
|
|||
|
|
+ /opt/Xilinx/Vivado/2018.2/bin/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
|
|||
|
|
Vivado Simulator 2018.2
|
|||
|
|
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
|
|||
|
|
Multi-threading is on. Using 6 slave threads.
|
|||
|
|
Starting static elaboration
|
|||
|
|
Completed static elaboration
|
|||
|
|
Starting simulation data flow analysis
|
|||
|
|
Completed simulation data flow analysis
|
|||
|
|
Time Resolution for simulation is 1ps
|
|||
|
|
Compiling module work.S_RESETTER_line
|
|||
|
|
Compiling module work.S_RESETTER_lookup
|
|||
|
|
Compiling module work.S_RESETTER_control
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_0_ErrorC...
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_0_Extrac...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
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|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
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Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
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Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
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|
|||
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|
|||
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|
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|
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|
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|
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|
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|
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Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
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Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
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|
|||
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Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
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Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
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Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
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|
|||
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Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
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Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
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Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_TopPar...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ethe...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ethe...
|
|||
|
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|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ethe...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
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|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv4...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_ipv6...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
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|
|||
|
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Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
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Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_tcp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_udp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_udp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_udp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_udp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_udp_...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_start_compute_p_icmp...
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
Compiling module work.TopParser_t_start_compute_user_m...
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_start
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_reject
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_0_TupleF...
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopParser_t_accept
|
|||
|
|
Compiling module work.TopParser_t_EngineStage_1
|
|||
|
|
Compiling module work.TopParser_t_Engine
|
|||
|
|
Compiling module work.TopParser_t
|
|||
|
|
Compiling module work.TopPipe_lvl_t_setup_compute_real...
|
|||
|
|
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|
|||
|
|
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
|
|||
|
|
Compiling module work.TopPipe_lvl_t_setup
|
|||
|
|
Compiling module work.TopPipe_lvl_t_EngineStage_0
|
|||
|
|
Compiling module work.TopPipe_lvl_t_Engine
|
|||
|
|
Compiling module work.TopPipe_lvl_t
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Hash_Lo...
|
|||
|
|
Compiling module work.xpm_memory_base(MEMORY_SIZE=2160...
|
|||
|
|
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=21...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_RamR1RW...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Cam
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Lookup
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Hash_Up...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Randmod...
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Update
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_IntTop
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_Wrap
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t_csr
|
|||
|
|
Compiling module work.realmain_v4_networks_0_t
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_v4_netw...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_v4_netw...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_v4_netw...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_EngineStage_0
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_NoAction_0_sec_c...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_NoAction_0_sec_c...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_NoAction_0_sec
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
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|
|||
|
|
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|
|||
|
|
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|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
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|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
|
Compiling module work.TopPipe_lvl_0_t_realmain_control...
|
|||
|
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Compiling module work.TopPipe_lvl_0_t_realmain_control...
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|
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Compiling module work.xpm_cdc_sync_rst(DEST_SYNC_FF=2,...
|
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|
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|
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|
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|
|||
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|
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|
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|
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|
|||
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|
|||
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|
|||
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|
|||
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|
|||
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|
|||
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|||
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|
|||
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|
|||
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|
|||
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|
|||
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|
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|||
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|
|||
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|
|||
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|
|||
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|
|||
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|
|||
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|
|||
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|
|||
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|
|||
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|
|||
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|
|||
|
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|
|||
|
|
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|
|||
|
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|
|||
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|
|||
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Compiling module work.glbl
|
|||
|
|
Built simulation snapshot work.SimpleSumeSwitch_tb#work.glbl
|
|||
|
|
|
|||
|
|
****** Webtalk v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/xsim_webtalk.tcl -notrace
|
|||
|
|
INFO: [Common 17-186] '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Sun Jul 28 16:59:05 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html.
|
|||
|
|
INFO: [Common 17-206] Exiting Webtalk at Sun Jul 28 16:59:05 2019...
|
|||
|
|
+ /opt/Xilinx/Vivado/2018.2/bin/xsim --runall SimpleSumeSwitch_tb#work.glbl
|
|||
|
|
|
|||
|
|
****** xsim v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsim_script.tcl
|
|||
|
|
# xsim {work.SimpleSumeSwitch_tb#work.glbl} -autoloadwcfg -runall
|
|||
|
|
Vivado Simulator 2018.2
|
|||
|
|
Time resolution is 1 ps
|
|||
|
|
run -all
|
|||
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_370 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_370 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_370 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_370 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.realmain_v4_networks_0.realmain_v4_networks_0_t_Wrap_inst.realmain_v4_networks_0_t_IntTop_inst.realmain_v4_networks_0_t_Lookup_inst.realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_370 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1078 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.lf3x44qdk2z74a1s0gndyt27sldl_779.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1171 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.q7gvskyh9rdb9henjto295zvigo9_974.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1201 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1265 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.blb6zofu4m1iwfz7b9fn78j_619.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1349 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.xnn8oc66i3dtvlfhp0bahskooll2x2_2380.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1171 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.xw49r6188i46a9wjd0nkk1oksp_526.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1201 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.nqj3a7on863ee2q57ufzkn6sb2_2042.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1530 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.f2xqwifp1sq1wjip1qs5_1422.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1614 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.vgsz2hwji6xt2tcnqha3_994.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1698 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.jwu7vwv11bfiar50ae_2490.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1265 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.m150wixgtma9i0g8y0g7_645.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1349 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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|||
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.y06wki9vylrmylq2v_2571.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1950 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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|||
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.avehixb9cn0lazkk9ssg_157.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1171 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.u34kvw4geng8wp39esl2j727nx7c0_647.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1201 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
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|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.gbqfimspskm6hnlgzqqao1mt5w_1310.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1698 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.xvxcv5ctaicypzrsuzoa92bpsxv_1486.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2219 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.itav5rgzqhzrf7n00dmq9hj_2570.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1530 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
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|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.rqlk2vb5gdzd29aq4s0qdonhh2_1914.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
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|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1265 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.wboy95wr5obljm9n9nzzz5j30dc2v6h_2139.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1614 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.xan657w55lznzq3hcpp22k9a_2275.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2555 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.uswzetjhoap7d9wrf4i9dhm9lwzf_2235.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1349 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.xe63wyalaxqi3pjbu72rro2_1653.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1950 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.jkyzocxmm0s4149oa1_1899.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1171 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.izzp83m68hsu2ozh14472qcg_421.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1201 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.pvmmu0cz9e244pe3fiu49stpb6kwfc_144.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1530 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.r0sf3f4b9u0hx8wiyii96zm26iev_2414.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1614 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.ht1zdw1pp2sdohld_2567.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1698 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.itbaw93kgsedybjcawtjyy1ivrr3ksj_977.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1265 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.bg3rgtuwucqmjzmclir9q2k5ps_794.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1349 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.xdgk72zc6lz2v1f6_638.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1950 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.gp7dlwqm2bugfp4a69nq18to_18.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3409 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.wfqws46340wyslrwid2yow_1831.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1201 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.ffbkdipo4aqln89eo1a_180.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1698 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.t3nvy4hx7fbwz0fzqej0kwod6wj_790.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1265 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/xpm_memory.sv
|
|||
|
|
[SW] CAM_Init() - start
|
|||
|
|
[SW] CAM_Init() - done
|
|||
|
|
[SW] CAM_EnableDevice() - start
|
|||
|
|
SV_write_control()- start
|
|||
|
|
SV_write_control()- done
|
|||
|
|
SV_read_control()- start
|
|||
|
|
SV_read_control()- done
|
|||
|
|
SV_write_control()- start
|
|||
|
|
SV_write_control()- done
|
|||
|
|
[SW] CAM_EnableDevice() - done
|
|||
|
|
[2280754] INFO: finished packet stimulus file
|
|||
|
|
[2735572] ERROR: tuple mismatch for packet 1
|
|||
|
|
expected < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
|
|||
|
|
actual < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000004010000 >
|
|||
|
|
$finish called at time : 2735572 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" Line 120
|
|||
|
|
exit
|
|||
|
|
INFO: [Common 17-206] Exiting xsim at Sun Jul 28 16:59:15 2019...
|
|||
|
|
+ grep ^expected /home/nico/master-thesis/netpfga/log/compile-2019-07-28-165815
|
|||
|
|
+ sed -e s/.*= <// -e s/.*= (//
|
|||
|
|
+ expected_line= 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
|
|||
|
|
+ grep ^actual /home/nico/master-thesis/netpfga/log/compile-2019-07-28-165815
|
|||
|
|
+ sed -e s/.*= <// -e s/.*= (//
|
|||
|
|
+ actual_line= 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000004010000 >
|
|||
|
|
+ date
|
|||
|
|
Son Jul 28 16:59:15 CEST 2019
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|||
|
|
+ make config_writes
|
|||
|
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata
|
|||
|
|
orig dic: OrderedDict([(0, ('00000020', '00000001')), (1, ('00000020', '00000000'))])
|
|||
|
|
new dic: OrderedDict()
|
|||
|
|
+ date
|
|||
|
|
Son Jul 28 16:59:15 CEST 2019
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|||
|
|
+ make uninstall_sdnet
|
|||
|
|
rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip
|
|||
|
|
+ make install_sdnet
|
|||
|
|
rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip
|
|||
|
|
cp -r nf_sume_sdnet_ip /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/
|
|||
|
|
mkdir /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/hdl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper/
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/tcl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/Makefile /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
|
|||
|
|
make -C /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
|
|||
|
|
rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip
|
|||
|
|
vivado -mode batch -source nf_sume_sdnet.tcl
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source nf_sume_sdnet.tcl
|
|||
|
|
# set design nf_sume_sdnet
|
|||
|
|
# set top nf_sume_sdnet
|
|||
|
|
# set device xc7vx690t-3-ffg1761
|
|||
|
|
# set proj_dir ./ip_proj
|
|||
|
|
# set ip_version 1.00
|
|||
|
|
# set lib_name NetFPGA
|
|||
|
|
# create_project -name ${design} -force -dir "./${proj_dir}" -part ${device}
|
|||
|
|
# set_property source_mgmt_mode All [current_project]
|
|||
|
|
# set_property top ${top} [current_fileset]
|
|||
|
|
# set_property ip_repo_paths $::env(SUME_FOLDER)/lib/hw/ [current_fileset]
|
|||
|
|
# update_ip_catalog
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
|
|||
|
|
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
|
|||
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
|||
|
|
# puts "nf_sume_sdnet"
|
|||
|
|
nf_sume_sdnet
|
|||
|
|
# read_verilog "./wrapper/sume_to_sdnet.v"
|
|||
|
|
# read_verilog "./wrapper/nf_sume_sdnet.v"
|
|||
|
|
# read_verilog "./wrapper/changeEndian.v"
|
|||
|
|
# add_files -scan_for_includes ./SimpleSumeSwitch/
|
|||
|
|
# import_files -force
|
|||
|
|
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
|
|||
|
|
# update_compile_order -fileset sources_1
|
|||
|
|
# update_compile_order -fileset sim_1
|
|||
|
|
# ipx::package_project
|
|||
|
|
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/wrapper/changeEndian.v'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.h'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/dpi.h'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM.h'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM_INST0.h'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.vp'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv'.
|
|||
|
|
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv'.
|
|||
|
|
INFO: [IP_Flow 19-5169] Module 'nf_sume_sdnet' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'axis_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'S_AXI'.
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'.
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'S_AXI_ARESETN'.
|
|||
|
|
INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'axis_resetn'.
|
|||
|
|
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
|||
|
|
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
|||
|
|
ipx::package_project: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1291.492 ; gain = 12.000 ; free physical = 13770 ; free virtual = 16072
|
|||
|
|
# set_property name ${design} [ipx::current_core]
|
|||
|
|
# set_property library ${lib_name} [ipx::current_core]
|
|||
|
|
# set_property vendor_display_name {NetFPGA} [ipx::current_core]
|
|||
|
|
# set_property company_url {http://www.netfpga.org} [ipx::current_core]
|
|||
|
|
# set_property vendor {NetFPGA} [ipx::current_core]
|
|||
|
|
# set_property supported_families {{virtex7} {Production}} [ipx::current_core]
|
|||
|
|
# set_property taxonomy {{/NetFPGA/Generic}} [ipx::current_core]
|
|||
|
|
# set_property version ${ip_version} [ipx::current_core]
|
|||
|
|
# set_property display_name ${design} [ipx::current_core]
|
|||
|
|
# set_property description ${design} [ipx::current_core]
|
|||
|
|
# ipx::add_user_parameter {C_M_AXIS_DATA_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_M_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {256} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {C_S_AXIS_DATA_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_S_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {256} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {C_M_AXIS_TUSER_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_M_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {128} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {C_S_AXIS_TUSER_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_S_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {128} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {C_S_AXI_DATA_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_S_AXI_DATA_WIDTH} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {32} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {C_S_AXI_ADDR_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {C_S_AXI_ADDR_WIDTH} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {12} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_user_parameter {SDNET_ADDR_WIDTH} [ipx::current_core]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_resolve_type {user} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property display_name {SDNET_ADDR_WIDTH} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value {11} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|||
|
|
# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|||
|
|
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]]
|
|||
|
|
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]]
|
|||
|
|
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]]
|
|||
|
|
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]]
|
|||
|
|
# update_ip_catalog -rebuild
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
|
|||
|
|
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
|
|||
|
|
# ipx::infer_user_parameters [ipx::current_core]
|
|||
|
|
# ipx::check_integrity [ipx::current_core]
|
|||
|
|
INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
|
|||
|
|
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
|||
|
|
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
|||
|
|
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
|
|||
|
|
# ipx::save_core [ipx::current_core]
|
|||
|
|
# update_ip_catalog
|
|||
|
|
# close_project
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 28 16:59:38 2019...
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
|
|||
|
|
+ date
|
|||
|
|
Son Jul 28 16:59:38 CEST 2019
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default
|
|||
|
|
+ make
|
|||
|
|
rm -f config_writes.py*
|
|||
|
|
rm -f *.pyc
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./
|
|||
|
|
+ date
|
|||
|
|
Son Jul 28 16:59:38 CEST 2019
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA
|
|||
|
|
+ ./tools/scripts/nf_test.py sim --major switch --minor default
|
|||
|
|
make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
|
|||
|
|
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_defines.tcl
|
|||
|
|
# set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
# set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
# set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
# set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
# set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
# set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
# set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
# set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
# set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
# set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
# set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
# set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
# set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
# set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
# set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
# set M00_BASEADDR 0x44000000
|
|||
|
|
# set M00_HIGHADDR 0x44000FFF
|
|||
|
|
# set M00_SIZEADDR 0x1000
|
|||
|
|
# set M01_BASEADDR 0x44010000
|
|||
|
|
# set M01_HIGHADDR 0x44010FFF
|
|||
|
|
# set M01_SIZEADDR 0x1000
|
|||
|
|
# set M02_BASEADDR 0x44020000
|
|||
|
|
# set M02_HIGHADDR 0x44020FFF
|
|||
|
|
# set M02_SIZEADDR 0x1000
|
|||
|
|
# set M03_BASEADDR 0x44030000
|
|||
|
|
# set M03_HIGHADDR 0x44030FFF
|
|||
|
|
# set M03_SIZEADDR 0x1000
|
|||
|
|
# set M04_BASEADDR 0x44040000
|
|||
|
|
# set M04_HIGHADDR 0x44040FFF
|
|||
|
|
# set M04_SIZEADDR 0x1000
|
|||
|
|
# set M05_BASEADDR 0x44050000
|
|||
|
|
# set M05_HIGHADDR 0x44050FFF
|
|||
|
|
# set M05_SIZEADDR 0x1000
|
|||
|
|
# set M06_BASEADDR 0x44060000
|
|||
|
|
# set M06_HIGHADDR 0x44060FFF
|
|||
|
|
# set M06_SIZEADDR 0x1000
|
|||
|
|
# set M07_BASEADDR 0x44070000
|
|||
|
|
# set M07_HIGHADDR 0x44070FFF
|
|||
|
|
# set M07_SIZEADDR 0x1000
|
|||
|
|
# set M08_BASEADDR 0x44080000
|
|||
|
|
# set M08_HIGHADDR 0x44080FFF
|
|||
|
|
# set M08_SIZEADDR 0x1000
|
|||
|
|
# set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
# set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
# set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
# set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
# set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
# set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
# set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
# set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
# set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
# set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
# set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
# set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
# set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
# set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
# set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
# set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
# set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
# set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
# set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
# set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
# set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
# set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
# set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
# set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
# set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
# set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
# set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 28 16:59:44 2019...
|
|||
|
|
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/export_registers.tcl
|
|||
|
|
# set DEF_LIST {
|
|||
|
|
# {MICROBLAZE_AXI_IIC 0 0 ""} \
|
|||
|
|
# {MICROBLAZE_UARTLITE 0 0 ""} \
|
|||
|
|
# {MICROBLAZE_DLMB_BRAM 0 0 ""} \
|
|||
|
|
# {MICROBLAZE_ILMB_BRAM 0 0 ""} \
|
|||
|
|
# {MICROBLAZE_AXI_INTC 0 0 ""} \
|
|||
|
|
# {INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \
|
|||
|
|
# {OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \
|
|||
|
|
# {OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \
|
|||
|
|
# {NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \
|
|||
|
|
# {NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
# {NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
# {NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
# {NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \
|
|||
|
|
#
|
|||
|
|
#
|
|||
|
|
# }
|
|||
|
|
# set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/
|
|||
|
|
# set target_file $target_path/sume_register_defines.h
|
|||
|
|
# proc write_header { target_file } {
|
|||
|
|
#
|
|||
|
|
# # creat a blank header file
|
|||
|
|
# # do a fresh rewrite in case the file already exits
|
|||
|
|
# file delete -force $target_file
|
|||
|
|
# open $target_file "w"
|
|||
|
|
# set h_file [open $target_file "w"]
|
|||
|
|
#
|
|||
|
|
#
|
|||
|
|
# puts $h_file "//-"
|
|||
|
|
# puts $h_file "// Copyright (c) 2015 University of Cambridge"
|
|||
|
|
# puts $h_file "// All rights reserved."
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory "
|
|||
|
|
# puts $h_file "// under National Science Foundation under Grant No. CNS-0855268,"
|
|||
|
|
# puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and"
|
|||
|
|
# puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), "
|
|||
|
|
# puts $h_file "// as part of the DARPA MRC research programme."
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// @NETFPGA_LICENSE_HEADER_START@"
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor"
|
|||
|
|
# puts $h_file "// license agreements. See the NOTICE file distributed with this work for"
|
|||
|
|
# puts $h_file "// additional information regarding copyright ownership. NetFPGA licenses this"
|
|||
|
|
# puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the"
|
|||
|
|
# puts $h_file "// \"License\"); you may not use this file except in compliance with the"
|
|||
|
|
# puts $h_file "// License. You may obtain a copy of the License at:"
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// http://www.netfpga-cic.org"
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed"
|
|||
|
|
# puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR"
|
|||
|
|
# puts $h_file "// CONDITIONS OF ANY KIND, either express or implied. See the License for the"
|
|||
|
|
# puts $h_file "// specific language governing permissions and limitations under the License."
|
|||
|
|
# puts $h_file "//"
|
|||
|
|
# puts $h_file "// @NETFPGA_LICENSE_HEADER_END@"
|
|||
|
|
# puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
|
|||
|
|
# puts $h_file "// This is an automatically generated header definitions file"
|
|||
|
|
# puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
|
|||
|
|
# puts $h_file ""
|
|||
|
|
#
|
|||
|
|
# close $h_file
|
|||
|
|
#
|
|||
|
|
# };
|
|||
|
|
# proc write_core {target_file prefix id has_registers lib_name} {
|
|||
|
|
#
|
|||
|
|
#
|
|||
|
|
# set h_file [open $target_file "a"]
|
|||
|
|
#
|
|||
|
|
# #First, read the memory map information from the reference_project defines file
|
|||
|
|
# source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
|
|||
|
|
#
|
|||
|
|
#
|
|||
|
|
# set baseaddr [set $prefix\_BASEADDR]
|
|||
|
|
# set highaddr [set $prefix\_HIGHADDR]
|
|||
|
|
# set sizeaddr [set $prefix\_SIZEADDR]
|
|||
|
|
#
|
|||
|
|
# puts $h_file "//######################################################"
|
|||
|
|
# puts $h_file "//# Definitions for $prefix"
|
|||
|
|
# puts $h_file "//######################################################"
|
|||
|
|
#
|
|||
|
|
# puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr"
|
|||
|
|
# puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr"
|
|||
|
|
# puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr"
|
|||
|
|
# puts $h_file ""
|
|||
|
|
#
|
|||
|
|
# #Second, read the registers information from the library defines file
|
|||
|
|
# if $has_registers {
|
|||
|
|
# set lib_path "$public_repo_dir/std/cores/$lib_name"
|
|||
|
|
# set regs_h_define_file $lib_path
|
|||
|
|
# set regs_h_define_file_read [open $regs_h_define_file r]
|
|||
|
|
# set regs_h_define_file_data [read $regs_h_define_file_read]
|
|||
|
|
# close $regs_h_define_file_read
|
|||
|
|
# set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"]
|
|||
|
|
#
|
|||
|
|
# foreach read_line $regs_h_define_file_data_line {
|
|||
|
|
# if {[regexp "#define" $read_line]} {
|
|||
|
|
# puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]"
|
|||
|
|
# }
|
|||
|
|
# }
|
|||
|
|
# }
|
|||
|
|
# puts $h_file ""
|
|||
|
|
# close $h_file
|
|||
|
|
# };
|
|||
|
|
# write_header $target_file
|
|||
|
|
# foreach lib_item $DEF_LIST {
|
|||
|
|
# write_core $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3]
|
|||
|
|
# }
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 28 16:59:50 2019...
|
|||
|
|
cd ../sw/embedded/src && cp /home/nico/projects/P4-NetFPGA/tools/scripts/xparam2regdefines.py . && python xparam2regdefines.py
|
|||
|
|
cd ../sw/embedded/src && rm -f xparam2regdefines.py && mv reg_defines.h ../
|
|||
|
|
cd ../sw/embedded && cp /home/nico/projects/P4-NetFPGA/tools/scripts/python_parser.py . && python python_parser.py
|
|||
|
|
cd ../sw/embedded && rm -f python_parser.py && mv reg_defines.py ../../test/reg_defines_simple_sume_switch.py
|
|||
|
|
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
|
|||
|
|
make: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
|
|||
|
|
rm -rf proj_* vivado*.* *.*~ .Xil* /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/
|
|||
|
|
rm -rf *[0-9]_{stim,expected,log}.axi
|
|||
|
|
rm -f *.axi
|
|||
|
|
rm -f portconfig.sim
|
|||
|
|
rm -f seed
|
|||
|
|
rm -f *.log
|
|||
|
|
rm -f ../test/Makefile
|
|||
|
|
rm -rf ../test/*.log
|
|||
|
|
rm -rf ../test/*.axi
|
|||
|
|
rm -rf ../test/seed
|
|||
|
|
rm -rf ../test/*.sim
|
|||
|
|
rm -rf ../test/proj_*
|
|||
|
|
rm -rf ../test/ip_repo
|
|||
|
|
rm -f ../test/vivado*.*
|
|||
|
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.py
|
|||
|
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.pyc
|
|||
|
|
rm -f ../hw/create_ip/id_rom16x32.coe
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
|
|||
|
|
echo 16028002 >> rom_data.txt
|
|||
|
|
echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt
|
|||
|
|
grep: ../../../RELEASE_NOTES: No such file or directory
|
|||
|
|
echo 00000204 >> rom_data.txt
|
|||
|
|
echo 0000FFFF >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py
|
|||
|
|
16
|
|||
|
|
|
|||
|
|
mv -f id_rom16x32.coe ../hw/create_ip/
|
|||
|
|
mv -f rom_data.txt ../hw/create_ip/
|
|||
|
|
cp -f /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_defines_simple_sume_switch.py /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/reg_defines_simple_sume_switch.py
|
|||
|
|
vivado -mode batch -source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl -tclargs sim_switch_default
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl
|
|||
|
|
# set design $::env(NF_PROJECT_NAME)
|
|||
|
|
# set top top_sim
|
|||
|
|
# set sim_top top_tb
|
|||
|
|
# set device xc7vx690t-3-ffg1761
|
|||
|
|
# set proj_dir ./project
|
|||
|
|
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
|
|||
|
|
# set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/
|
|||
|
|
# set repo_dir ./ip_repo
|
|||
|
|
# set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc
|
|||
|
|
# set project_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_general.xdc
|
|||
|
|
# set nf_10g_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_10g.xdc
|
|||
|
|
# set test_name [lindex $argv 0]
|
|||
|
|
# source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
# create_project -name ${design} -force -dir "$::env(NF_DESIGN_DIR)/hw/${proj_dir}" -part ${device}
|
|||
|
|
# set_property source_mgmt_mode DisplayOnly [current_project]
|
|||
|
|
# set_property top ${top} [current_fileset]
|
|||
|
|
# puts "Creating User Datapath reference project"
|
|||
|
|
Creating User Datapath reference project
|
|||
|
|
# create_fileset -constrset -quiet constraints
|
|||
|
|
# file copy ${public_repo_dir}/ ${repo_dir}
|
|||
|
|
# set_property ip_repo_paths ${repo_dir} [current_fileset]
|
|||
|
|
# add_files -fileset constraints -norecurse ${bit_settings}
|
|||
|
|
# add_files -fileset constraints -norecurse ${project_constraints}
|
|||
|
|
# add_files -fileset constraints -norecurse ${nf_10g_constraints}
|
|||
|
|
# set_property is_enabled true [get_files ${project_constraints}]
|
|||
|
|
# set_property is_enabled true [get_files ${bit_settings}]
|
|||
|
|
# set_property is_enabled true [get_files ${project_constraints}]
|
|||
|
|
# update_ip_catalog
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/ip_repo'.
|
|||
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
|||
|
|
# create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci]
|
|||
|
|
# reset_target all [get_ips nf_sume_sdnet_ip]
|
|||
|
|
# generate_target all [get_ips nf_sume_sdnet_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
# create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip
|
|||
|
|
# set_property -dict [list CONFIG.C_BASEADDR $INPUT_ARBITER_BASEADDR] [get_ips input_arbiter_ip]
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci]
|
|||
|
|
# reset_target all [get_ips input_arbiter_ip]
|
|||
|
|
# generate_target all [get_ips input_arbiter_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'input_arbiter_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'input_arbiter_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'input_arbiter_ip'...
|
|||
|
|
# create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip
|
|||
|
|
# set_property -dict [list CONFIG.C_BASEADDR $OUTPUT_QUEUES_BASEADDR] [get_ips sss_output_queues_ip]
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci]
|
|||
|
|
# reset_target all [get_ips sss_output_queues_ip]
|
|||
|
|
# generate_target all [get_ips sss_output_queues_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'sss_output_queues_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'sss_output_queues_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'sss_output_queues_ip'...
|
|||
|
|
# create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip
|
|||
|
|
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
|
|||
|
|
create_ip: Time (s): cpu = 00:00:22 ; elapsed = 00:00:58 . Memory (MB): peak = 1690.242 ; gain = 390.395 ; free physical = 13239 ; free virtual = 15725
|
|||
|
|
# set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {1024} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip]
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files identifier_ip.xci]
|
|||
|
|
# reset_target all [get_ips identifier_ip]
|
|||
|
|
# generate_target all [get_ips identifier_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'identifier_ip'...
|
|||
|
|
# create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip
|
|||
|
|
# set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip]
|
|||
|
|
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '5.000' to '5.0' has been ignored for IP 'clk_wiz_ip'
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci]
|
|||
|
|
# reset_target all [get_ips clk_wiz_ip]
|
|||
|
|
# generate_target all [get_ips clk_wiz_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_ip'...
|
|||
|
|
# create_ip -name barrier -vendor NetFPGA -library NetFPGA -module_name barrier_ip
|
|||
|
|
# reset_target all [get_ips barrier_ip]
|
|||
|
|
# generate_target all [get_ips barrier_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'barrier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'barrier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'barrier_ip'...
|
|||
|
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip0
|
|||
|
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_0_log.axi] [get_ips axis_sim_record_ip0]
|
|||
|
|
# reset_target all [get_ips axis_sim_record_ip0]
|
|||
|
|
# generate_target all [get_ips axis_sim_record_ip0]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip0'...
|
|||
|
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip1
|
|||
|
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_1_log.axi] [get_ips axis_sim_record_ip1]
|
|||
|
|
# reset_target all [get_ips axis_sim_record_ip1]
|
|||
|
|
# generate_target all [get_ips axis_sim_record_ip1]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip1'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip1'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip1'...
|
|||
|
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip2
|
|||
|
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_2_log.axi] [get_ips axis_sim_record_ip2]
|
|||
|
|
# reset_target all [get_ips axis_sim_record_ip2]
|
|||
|
|
# generate_target all [get_ips axis_sim_record_ip2]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip2'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip2'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip2'...
|
|||
|
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip3
|
|||
|
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_3_log.axi] [get_ips axis_sim_record_ip3]
|
|||
|
|
# reset_target all [get_ips axis_sim_record_ip3]
|
|||
|
|
# generate_target all [get_ips axis_sim_record_ip3]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip3'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip3'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip3'...
|
|||
|
|
# create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip4
|
|||
|
|
# set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/dma_0_log.axi] [get_ips axis_sim_record_ip4]
|
|||
|
|
# reset_target all [get_ips axis_sim_record_ip4]
|
|||
|
|
# generate_target all [get_ips axis_sim_record_ip4]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_record_ip4'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_record_ip4'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_record_ip4'...
|
|||
|
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip0
|
|||
|
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_0_stim.axi] [get_ips axis_sim_stim_ip0]
|
|||
|
|
# generate_target all [get_ips axis_sim_stim_ip0]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip0'...
|
|||
|
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip1
|
|||
|
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_1_stim.axi] [get_ips axis_sim_stim_ip1]
|
|||
|
|
# generate_target all [get_ips axis_sim_stim_ip1]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip1'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip1'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip1'...
|
|||
|
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip2
|
|||
|
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_2_stim.axi] [get_ips axis_sim_stim_ip2]
|
|||
|
|
# generate_target all [get_ips axis_sim_stim_ip2]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip2'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip2'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip2'...
|
|||
|
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip3
|
|||
|
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_3_stim.axi] [get_ips axis_sim_stim_ip3]
|
|||
|
|
# generate_target all [get_ips axis_sim_stim_ip3]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip3'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip3'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip3'...
|
|||
|
|
# create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip4
|
|||
|
|
# set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/dma_0_stim.axi] [get_ips axis_sim_stim_ip4]
|
|||
|
|
# generate_target all [get_ips axis_sim_stim_ip4]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_sim_stim_ip4'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_sim_stim_ip4'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_sim_stim_ip4'...
|
|||
|
|
# create_ip -name axi_sim_transactor -vendor NetFPGA -library NetFPGA -module_name axi_sim_transactor_ip
|
|||
|
|
# set_property -dict [list CONFIG.STIM_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.axi CONFIG.EXPECT_FILE $::env(NF_DESIGN_DIR)/test/reg_expect.axi CONFIG.LOG_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.log] [get_ips axi_sim_transactor_ip]
|
|||
|
|
# reset_target all [get_ips axi_sim_transactor_ip]
|
|||
|
|
# generate_target all [get_ips axi_sim_transactor_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_sim_transactor_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_sim_transactor_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_sim_transactor_ip'...
|
|||
|
|
# update_ip_catalog
|
|||
|
|
# source $::env(NF_DESIGN_DIR)/hw/tcl/control_sub_sim.tcl
|
|||
|
|
## set scripts_vivado_version 2018.2
|
|||
|
|
## set current_vivado_version [version -short]
|
|||
|
|
## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
|||
|
|
## puts ""
|
|||
|
|
## puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
|
|||
|
|
##
|
|||
|
|
## return 1
|
|||
|
|
## }
|
|||
|
|
## set design_name control_sub
|
|||
|
|
## if { [get_projects -quiet] eq "" } {
|
|||
|
|
## puts "ERROR: Please open or create a project!"
|
|||
|
|
## return 1
|
|||
|
|
## }
|
|||
|
|
## set errMsg ""
|
|||
|
|
## set nRet 0
|
|||
|
|
## set cur_design [current_bd_design -quiet]
|
|||
|
|
## set list_cells [get_bd_cells -quiet]
|
|||
|
|
## if { ${design_name} eq "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 1) Design_name not set
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
|
|||
|
|
## set nRet 1
|
|||
|
|
##
|
|||
|
|
## } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 2): Current design opened AND is empty AND names same.
|
|||
|
|
## # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
|||
|
|
## # 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
|||
|
|
##
|
|||
|
|
## if { $cur_design ne $design_name } {
|
|||
|
|
## puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
|||
|
|
## set design_name [get_property NAME $cur_design]
|
|||
|
|
## }
|
|||
|
|
## puts "INFO: Constructing design in IPI design <$cur_design>..."
|
|||
|
|
##
|
|||
|
|
## } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 5) Current design opened AND has components AND same names.
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
|||
|
|
## set nRet 1
|
|||
|
|
## } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 6) Current opened design, has components, but diff names, design_name exists in project.
|
|||
|
|
## # 7) No opened design, design_name exists in project.
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
|||
|
|
## set nRet 2
|
|||
|
|
##
|
|||
|
|
## } else {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 8) No opened design, design_name not in project.
|
|||
|
|
## # 9) Current opened design, has components, but diff names, design_name not in project.
|
|||
|
|
##
|
|||
|
|
## puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
|
|||
|
|
##
|
|||
|
|
## create_bd_design $design_name
|
|||
|
|
##
|
|||
|
|
## puts "INFO: Making design <$design_name> as current_bd_design."
|
|||
|
|
## current_bd_design $design_name
|
|||
|
|
##
|
|||
|
|
## }
|
|||
|
|
INFO: Currently there is no design <control_sub> in project, so creating one...
|
|||
|
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
|||
|
|
INFO: Making design <control_sub> as current_bd_design.
|
|||
|
|
## puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
|
|||
|
|
INFO: Currently the variable <design_name> is equal to "control_sub".
|
|||
|
|
## if { $nRet != 0 } {
|
|||
|
|
## puts $errMsg
|
|||
|
|
## return $nRet
|
|||
|
|
## }
|
|||
|
|
## proc create_root_design { parentCell } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" } {
|
|||
|
|
## set parentCell [get_bd_cells /]
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create interface ports
|
|||
|
|
## set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI
|
|||
|
|
## set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M01_AXI
|
|||
|
|
## set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M02_AXI
|
|||
|
|
## set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M03_AXI
|
|||
|
|
## set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M04_AXI
|
|||
|
|
## set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M05_AXI
|
|||
|
|
## set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M06_AXI
|
|||
|
|
## set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M07_AXI
|
|||
|
|
## set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.CLK_DOMAIN {} CONFIG.DATA_WIDTH {32} CONFIG.FREQ_HZ {100000000} CONFIG.ID_WIDTH {0} CONFIG.MAX_BURST_LENGTH {256} CONFIG.NUM_READ_OUTSTANDING {2} CONFIG.NUM_WRITE_OUTSTANDING {2} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0} ] $S00_AXI
|
|||
|
|
##
|
|||
|
|
## # Create ports
|
|||
|
|
## set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ]
|
|||
|
|
## set axi_lite_areset [ create_bd_port -dir I -type rst axi_lite_areset ]
|
|||
|
|
## set core_clk [ create_bd_port -dir I -type clk core_clk ]
|
|||
|
|
## set_property -dict [ list CONFIG.FREQ_HZ {200000000} ] $core_clk
|
|||
|
|
## set core_resetn [ create_bd_port -dir I -type rst core_resetn ]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create instance: axi_interconnect_0, and set properties
|
|||
|
|
## set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
|
|||
|
|
## set_property -dict [ list CONFIG.NUM_MI {8} CONFIG.TRANSLATION_MODE {0} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Add AXI clock converter
|
|||
|
|
## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0
|
|||
|
|
## connect_bd_intf_net [get_bd_intf_ports S00_AXI] [get_bd_intf_pins axi_clock_converter_0/S_AXI]
|
|||
|
|
## connect_bd_intf_net [get_bd_intf_pins axi_clock_converter_0/M_AXI] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI]
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI]
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk] [get_bd_pins axi_clock_converter_0/s_axi_aclk]
|
|||
|
|
## connect_bd_net -net core_clk_1 [get_bd_ports core_clk] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK]
|
|||
|
|
## connect_bd_net -net axi_lite_areset_1 [get_bd_ports axi_lite_areset] [get_bd_pins axi_clock_converter_0/s_axi_aresetn]
|
|||
|
|
## connect_bd_net -net core_resetn_1 [get_bd_ports core_resetn] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN]
|
|||
|
|
##
|
|||
|
|
## # Create address segments
|
|||
|
|
## source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
## assign_bd_address [get_bd_addr_segs {M00_AXI/Reg }]
|
|||
|
|
## set_property offset $M00_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}]
|
|||
|
|
## set_property range $M00_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}]
|
|||
|
|
##
|
|||
|
|
## assign_bd_address [get_bd_addr_segs {M01_AXI/Reg }]
|
|||
|
|
## set_property offset $M01_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}]
|
|||
|
|
## set_property range $M01_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## assign_bd_address [get_bd_addr_segs {M02_AXI/Reg }]
|
|||
|
|
## set_property offset $M02_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}]
|
|||
|
|
## set_property range $M02_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}]
|
|||
|
|
##
|
|||
|
|
## assign_bd_address [get_bd_addr_segs {M03_AXI/Reg }]
|
|||
|
|
## set_property offset $M03_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}]
|
|||
|
|
## set_property range $M03_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
##
|
|||
|
|
## save_bd_design
|
|||
|
|
## }
|
|||
|
|
## create_root_design ""
|
|||
|
|
CRITICAL WARNING: [BD 41-737] Cannot set the parameter TRANSLATION_MODE on /axi_interconnect_0. It is read-only.
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
</M00_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
|
|||
|
|
</M01_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
|
|||
|
|
</M02_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
|
|||
|
|
</M03_AXI/Reg> is being mapped into </S00_AXI> at <0x44A00000 [ 64K ]>
|
|||
|
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
|||
|
|
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/axi_clocking.v"
|
|||
|
|
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/nf_datapath.v"
|
|||
|
|
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_sim.v"
|
|||
|
|
# read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_tb.v"
|
|||
|
|
# update_compile_order -fileset sources_1
|
|||
|
|
# update_compile_order -fileset sim_1
|
|||
|
|
# set_property top ${sim_top} [get_filesets sim_1]
|
|||
|
|
# set_property include_dirs ${proj_dir} [get_filesets sim_1]
|
|||
|
|
# set_property simulator_language Mixed [current_project]
|
|||
|
|
# set_property verilog_define { {SIMULATION=1} } [get_filesets sim_1]
|
|||
|
|
# set_property -name xsim.more_options -value {-testplusarg TESTNAME=basic_test} -objects [get_filesets sim_1]
|
|||
|
|
# set_property runtime {} [get_filesets sim_1]
|
|||
|
|
# set_property target_simulator xsim [current_project]
|
|||
|
|
# set_property compxlib.xsim_compiled_library_dir {} [current_project]
|
|||
|
|
# set_property top_lib xil_defaultlib [get_filesets sim_1]
|
|||
|
|
# update_compile_order -fileset sim_1
|
|||
|
|
update_compile_order: Time (s): cpu = 00:00:20 ; elapsed = 00:00:08 . Memory (MB): peak = 2029.395 ; gain = 8.008 ; free physical = 13086 ; free virtual = 15613
|
|||
|
|
loading libsume..
|
|||
|
|
Traceback (most recent call last):
|
|||
|
|
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py", line 42, in <module>
|
|||
|
|
import config_writes
|
|||
|
|
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py", line 7
|
|||
|
|
|
|||
|
|
^
|
|||
|
|
IndentationError: expected an indented block
|
|||
|
|
while executing
|
|||
|
|
"exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py"
|
|||
|
|
invoked from within
|
|||
|
|
"set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]"
|
|||
|
|
(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 177)
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 28 17:01:18 2019...
|
|||
|
|
Makefile:120: recipe for target 'sim' failed
|
|||
|
|
make: *** [sim] Error 1
|
|||
|
|
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_stim.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_expected.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_stim.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_expected.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_stim.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_expected.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_stim.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_expected.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_expected.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.log': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_expect.axi': No such file or directory
|
|||
|
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.axi': No such file or directory
|
|||
|
|
NetFPGA environment:
|
|||
|
|
Root dir: /home/nico/projects/P4-NetFPGA
|
|||
|
|
Project name: simple_sume_switch
|
|||
|
|
Project dir: /tmp/nico/test/simple_sume_switch
|
|||
|
|
Work dir: /tmp/nico
|
|||
|
|
512
|
|||
|
|
=== Work directory is /tmp/nico/test/simple_sume_switch
|
|||
|
|
=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
|
|||
|
|
=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
|
|||
|
|
+ date
|
|||
|
|
Son Jul 28 17:01:18 CEST 2019
|
|||
|
|
+ [ = no ]
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch
|
|||
|
|
+ make
|
|||
|
|
make -C hw distclean
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
rm -rf proj_* vivado*.* *.*~ .Xil* /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/
|
|||
|
|
rm -rf *[0-9]_{stim,expected,log}.axi
|
|||
|
|
rm -f *.axi
|
|||
|
|
rm -f portconfig.sim
|
|||
|
|
rm -f seed
|
|||
|
|
rm -f *.log
|
|||
|
|
rm -f ../test/Makefile
|
|||
|
|
rm -rf ../test/*.log
|
|||
|
|
rm -rf ../test/*.axi
|
|||
|
|
rm -rf ../test/seed
|
|||
|
|
rm -rf ../test/*.sim
|
|||
|
|
rm -rf ../test/proj_*
|
|||
|
|
rm -rf ../test/ip_repo
|
|||
|
|
rm -f ../test/vivado*.*
|
|||
|
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.py
|
|||
|
|
rm -f ../test/*_*_*/reg_defines_simple_sume_switch.pyc
|
|||
|
|
rm -rfv project;\
|
|||
|
|
rm -rfv ../sw/embedded/project;\
|
|||
|
|
rm -rfv vivado*;\
|
|||
|
|
rm -rfv *.log;\
|
|||
|
|
rm -rfv .Xil;\
|
|||
|
|
rm -rfv ..rej;\
|
|||
|
|
rm -rfv .srcs;\
|
|||
|
|
rm -rfv webtalk*;\
|
|||
|
|
rm -rfv *.*~;\
|
|||
|
|
rm -rfv ip_repo;\
|
|||
|
|
rm -rfv ip_proj;\
|
|||
|
|
rm -rfv std;\
|
|||
|
|
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
make -C sw/embedded/ distclean
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
|
|||
|
|
rm -rf `find . -name "SDK_Workspace"`
|
|||
|
|
rm -rf `find . -name "*.log"`
|
|||
|
|
rm -rf `find . -name "*.jou"`
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
|
|||
|
|
rm -rfv vivado*;\
|
|||
|
|
|
|||
|
|
make -C hw project
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
rm -f ../hw/create_ip/id_rom16x32.coe
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
|
|||
|
|
echo 16028002 >> rom_data.txt
|
|||
|
|
echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt
|
|||
|
|
grep: ../../../RELEASE_NOTES: No such file or directory
|
|||
|
|
echo 00000204 >> rom_data.txt
|
|||
|
|
echo 0000FFFF >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py
|
|||
|
|
16
|
|||
|
|
|
|||
|
|
mv -f id_rom16x32.coe ../hw/create_ip/
|
|||
|
|
mv -f rom_data.txt ../hw/create_ip/
|
|||
|
|
echo "Create reference project under folder /project";\
|
|||
|
|
if test -d project/; then\
|
|||
|
|
echo "Project already exists"; \
|
|||
|
|
else \
|
|||
|
|
vivado -mode batch -source tcl/simple_sume_switch.tcl;\
|
|||
|
|
if [ -f patch/simple_sume_switch.patch ]; then\
|
|||
|
|
patch -p1 < patch/simple_sume_switch.patch;\
|
|||
|
|
fi;\
|
|||
|
|
fi;\
|
|||
|
|
|
|||
|
|
Create reference project under folder /project
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source tcl/simple_sume_switch.tcl
|
|||
|
|
# set design $::env(NF_PROJECT_NAME)
|
|||
|
|
# set top top
|
|||
|
|
# set device xc7vx690t-3-ffg1761
|
|||
|
|
# set proj_dir ./project
|
|||
|
|
# set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
|
|||
|
|
# set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/
|
|||
|
|
# set repo_dir ./ip_repo
|
|||
|
|
# set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc
|
|||
|
|
# set project_constraints ./constraints/nf_sume_general.xdc
|
|||
|
|
# set nf_10g_constraints ./constraints/nf_sume_10g.xdc
|
|||
|
|
# source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
## set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
## set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
## set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
## set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
## set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
## set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
## set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
## set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
## set M00_BASEADDR 0x44000000
|
|||
|
|
## set M00_HIGHADDR 0x44000FFF
|
|||
|
|
## set M00_SIZEADDR 0x1000
|
|||
|
|
## set M01_BASEADDR 0x44010000
|
|||
|
|
## set M01_HIGHADDR 0x44010FFF
|
|||
|
|
## set M01_SIZEADDR 0x1000
|
|||
|
|
## set M02_BASEADDR 0x44020000
|
|||
|
|
## set M02_HIGHADDR 0x44020FFF
|
|||
|
|
## set M02_SIZEADDR 0x1000
|
|||
|
|
## set M03_BASEADDR 0x44030000
|
|||
|
|
## set M03_HIGHADDR 0x44030FFF
|
|||
|
|
## set M03_SIZEADDR 0x1000
|
|||
|
|
## set M04_BASEADDR 0x44040000
|
|||
|
|
## set M04_HIGHADDR 0x44040FFF
|
|||
|
|
## set M04_SIZEADDR 0x1000
|
|||
|
|
## set M05_BASEADDR 0x44050000
|
|||
|
|
## set M05_HIGHADDR 0x44050FFF
|
|||
|
|
## set M05_SIZEADDR 0x1000
|
|||
|
|
## set M06_BASEADDR 0x44060000
|
|||
|
|
## set M06_HIGHADDR 0x44060FFF
|
|||
|
|
## set M06_SIZEADDR 0x1000
|
|||
|
|
## set M07_BASEADDR 0x44070000
|
|||
|
|
## set M07_HIGHADDR 0x44070FFF
|
|||
|
|
## set M07_SIZEADDR 0x1000
|
|||
|
|
## set M08_BASEADDR 0x44080000
|
|||
|
|
## set M08_HIGHADDR 0x44080FFF
|
|||
|
|
## set M08_SIZEADDR 0x1000
|
|||
|
|
## set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
## set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
## set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
## set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
## set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
## set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
## set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
## set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
## set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
## set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
## set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
## set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
## set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
## set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
## set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
# source ./tcl/export_registers.tcl
|
|||
|
|
## set DEF_LIST {
|
|||
|
|
## {MICROBLAZE_AXI_IIC 0 0 ""} \
|
|||
|
|
## {MICROBLAZE_UARTLITE 0 0 ""} \
|
|||
|
|
## {MICROBLAZE_DLMB_BRAM 0 0 ""} \
|
|||
|
|
## {MICROBLAZE_ILMB_BRAM 0 0 ""} \
|
|||
|
|
## {MICROBLAZE_AXI_INTC 0 0 ""} \
|
|||
|
|
## {INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \
|
|||
|
|
## {OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \
|
|||
|
|
## {OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \
|
|||
|
|
## {NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \
|
|||
|
|
## {NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
## {NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
## {NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
|
|||
|
|
## {NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## }
|
|||
|
|
## set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/
|
|||
|
|
## set target_file $target_path/sume_register_defines.h
|
|||
|
|
## proc write_header { target_file } {
|
|||
|
|
##
|
|||
|
|
## # creat a blank header file
|
|||
|
|
## # do a fresh rewrite in case the file already exits
|
|||
|
|
## file delete -force $target_file
|
|||
|
|
## open $target_file "w"
|
|||
|
|
## set h_file [open $target_file "w"]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## puts $h_file "//-"
|
|||
|
|
## puts $h_file "// Copyright (c) 2015 University of Cambridge"
|
|||
|
|
## puts $h_file "// All rights reserved."
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory "
|
|||
|
|
## puts $h_file "// under National Science Foundation under Grant No. CNS-0855268,"
|
|||
|
|
## puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and"
|
|||
|
|
## puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), "
|
|||
|
|
## puts $h_file "// as part of the DARPA MRC research programme."
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// @NETFPGA_LICENSE_HEADER_START@"
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor"
|
|||
|
|
## puts $h_file "// license agreements. See the NOTICE file distributed with this work for"
|
|||
|
|
## puts $h_file "// additional information regarding copyright ownership. NetFPGA licenses this"
|
|||
|
|
## puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the"
|
|||
|
|
## puts $h_file "// \"License\"); you may not use this file except in compliance with the"
|
|||
|
|
## puts $h_file "// License. You may obtain a copy of the License at:"
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// http://www.netfpga-cic.org"
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed"
|
|||
|
|
## puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR"
|
|||
|
|
## puts $h_file "// CONDITIONS OF ANY KIND, either express or implied. See the License for the"
|
|||
|
|
## puts $h_file "// specific language governing permissions and limitations under the License."
|
|||
|
|
## puts $h_file "//"
|
|||
|
|
## puts $h_file "// @NETFPGA_LICENSE_HEADER_END@"
|
|||
|
|
## puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
|
|||
|
|
## puts $h_file "// This is an automatically generated header definitions file"
|
|||
|
|
## puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
|
|||
|
|
## puts $h_file ""
|
|||
|
|
##
|
|||
|
|
## close $h_file
|
|||
|
|
##
|
|||
|
|
## };
|
|||
|
|
## proc write_core {target_file prefix id has_registers lib_name} {
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## set h_file [open $target_file "a"]
|
|||
|
|
##
|
|||
|
|
## #First, read the memory map information from the reference_project defines file
|
|||
|
|
## source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
## set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## set baseaddr [set $prefix\_BASEADDR]
|
|||
|
|
## set highaddr [set $prefix\_HIGHADDR]
|
|||
|
|
## set sizeaddr [set $prefix\_SIZEADDR]
|
|||
|
|
##
|
|||
|
|
## puts $h_file "//######################################################"
|
|||
|
|
## puts $h_file "//# Definitions for $prefix"
|
|||
|
|
## puts $h_file "//######################################################"
|
|||
|
|
##
|
|||
|
|
## puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr"
|
|||
|
|
## puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr"
|
|||
|
|
## puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr"
|
|||
|
|
## puts $h_file ""
|
|||
|
|
##
|
|||
|
|
## #Second, read the registers information from the library defines file
|
|||
|
|
## if $has_registers {
|
|||
|
|
## set lib_path "$public_repo_dir/std/cores/$lib_name"
|
|||
|
|
## set regs_h_define_file $lib_path
|
|||
|
|
## set regs_h_define_file_read [open $regs_h_define_file r]
|
|||
|
|
## set regs_h_define_file_data [read $regs_h_define_file_read]
|
|||
|
|
## close $regs_h_define_file_read
|
|||
|
|
## set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"]
|
|||
|
|
##
|
|||
|
|
## foreach read_line $regs_h_define_file_data_line {
|
|||
|
|
## if {[regexp "#define" $read_line]} {
|
|||
|
|
## puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]"
|
|||
|
|
## }
|
|||
|
|
## }
|
|||
|
|
## }
|
|||
|
|
## puts $h_file ""
|
|||
|
|
## close $h_file
|
|||
|
|
## };
|
|||
|
|
## write_header $target_file
|
|||
|
|
## foreach lib_item $DEF_LIST {
|
|||
|
|
## write_core $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3]
|
|||
|
|
## }
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
# create_project -name ${design} -force -dir "./${proj_dir}" -part ${device}
|
|||
|
|
# set_property source_mgmt_mode DisplayOnly [current_project]
|
|||
|
|
# set_property top ${top} [current_fileset]
|
|||
|
|
# puts "Creating User Datapath reference project"
|
|||
|
|
Creating User Datapath reference project
|
|||
|
|
# create_fileset -constrset -quiet constraints
|
|||
|
|
# file copy ${public_repo_dir}/ ${repo_dir}
|
|||
|
|
# set_property ip_repo_paths ${repo_dir} [current_fileset]
|
|||
|
|
# add_files -fileset constraints -norecurse ${bit_settings}
|
|||
|
|
# add_files -fileset constraints -norecurse ${project_constraints}
|
|||
|
|
# add_files -fileset constraints -norecurse ${nf_10g_constraints}
|
|||
|
|
# set_property is_enabled true [get_files ${project_constraints}]
|
|||
|
|
# set_property is_enabled true [get_files ${bit_settings}]
|
|||
|
|
# set_property is_enabled true [get_files ${nf_10g_constraints}]
|
|||
|
|
# set_property constrset constraints [get_runs synth_1]
|
|||
|
|
# set_property constrset constraints [get_runs impl_1]
|
|||
|
|
# update_ip_catalog
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
|
|||
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
|||
|
|
# create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci]
|
|||
|
|
# reset_target all [get_ips input_arbiter_ip]
|
|||
|
|
# generate_target all [get_ips input_arbiter_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'input_arbiter_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'input_arbiter_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'input_arbiter_ip'...
|
|||
|
|
# create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci]
|
|||
|
|
# reset_target all [get_ips sss_output_queues_ip]
|
|||
|
|
# generate_target all [get_ips sss_output_queues_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'sss_output_queues_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'sss_output_queues_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'sss_output_queues_ip'...
|
|||
|
|
# source ./tcl/control_sub.tcl
|
|||
|
|
## set scripts_vivado_version 2018.2
|
|||
|
|
## set current_vivado_version [version -short]
|
|||
|
|
## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
|||
|
|
## puts ""
|
|||
|
|
## puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
|
|||
|
|
##
|
|||
|
|
## return 1
|
|||
|
|
## }
|
|||
|
|
## set design_name control_sub
|
|||
|
|
## if { [get_projects -quiet] eq "" } {
|
|||
|
|
## puts "ERROR: Please open or create a project!"
|
|||
|
|
## return 1
|
|||
|
|
## }
|
|||
|
|
## set errMsg ""
|
|||
|
|
## set nRet 0
|
|||
|
|
## set cur_design [current_bd_design -quiet]
|
|||
|
|
## set list_cells [get_bd_cells -quiet]
|
|||
|
|
## if { ${design_name} eq "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 1) Design_name not set
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
|
|||
|
|
## set nRet 1
|
|||
|
|
##
|
|||
|
|
## } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 2): Current design opened AND is empty AND names same.
|
|||
|
|
## # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
|||
|
|
## # 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
|||
|
|
##
|
|||
|
|
## if { $cur_design ne $design_name } {
|
|||
|
|
## puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
|||
|
|
## set design_name [get_property NAME $cur_design]
|
|||
|
|
## }
|
|||
|
|
## puts "INFO: Constructing design in IPI design <$cur_design>..."
|
|||
|
|
##
|
|||
|
|
## } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 5) Current design opened AND has components AND same names.
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
|||
|
|
## set nRet 1
|
|||
|
|
## } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 6) Current opened design, has components, but diff names, design_name exists in project.
|
|||
|
|
## # 7) No opened design, design_name exists in project.
|
|||
|
|
##
|
|||
|
|
## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
|||
|
|
## set nRet 2
|
|||
|
|
##
|
|||
|
|
## } else {
|
|||
|
|
## # USE CASES:
|
|||
|
|
## # 8) No opened design, design_name not in project.
|
|||
|
|
## # 9) Current opened design, has components, but diff names, design_name not in project.
|
|||
|
|
##
|
|||
|
|
## puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
|
|||
|
|
##
|
|||
|
|
## create_bd_design $design_name
|
|||
|
|
##
|
|||
|
|
## puts "INFO: Making design <$design_name> as current_bd_design."
|
|||
|
|
## current_bd_design $design_name
|
|||
|
|
##
|
|||
|
|
## }
|
|||
|
|
INFO: Currently there is no design <control_sub> in project, so creating one...
|
|||
|
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
|||
|
|
INFO: Making design <control_sub> as current_bd_design.
|
|||
|
|
## puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
|
|||
|
|
INFO: Currently the variable <design_name> is equal to "control_sub".
|
|||
|
|
## if { $nRet != 0 } {
|
|||
|
|
## puts $errMsg
|
|||
|
|
## return $nRet
|
|||
|
|
## }
|
|||
|
|
## proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" || $nameHier eq "" } {
|
|||
|
|
## puts "ERROR: create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
## # Create cell and set as current instance
|
|||
|
|
## set hier_obj [create_bd_cell -type hier $nameHier]
|
|||
|
|
## current_bd_instance $hier_obj
|
|||
|
|
##
|
|||
|
|
## # Create interface pins
|
|||
|
|
## create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB
|
|||
|
|
## create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB
|
|||
|
|
##
|
|||
|
|
## # Create pins
|
|||
|
|
## create_bd_pin -dir I -type clk LMB_Clk
|
|||
|
|
## create_bd_pin -dir I -from 0 -to 0 -type rst LMB_Rst
|
|||
|
|
##
|
|||
|
|
## # Create instance: dlmb_bram_if_cntlr, and set properties
|
|||
|
|
## set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_ECC {0} ] $dlmb_bram_if_cntlr
|
|||
|
|
##
|
|||
|
|
## # Create instance: dlmb_v10, and set properties
|
|||
|
|
## set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: ilmb_bram_if_cntlr, and set properties
|
|||
|
|
## set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_ECC {0} ] $ilmb_bram_if_cntlr
|
|||
|
|
##
|
|||
|
|
## # Create instance: ilmb_v10, and set properties
|
|||
|
|
## set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: lmb_bram, and set properties
|
|||
|
|
## set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ]
|
|||
|
|
## set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller} ] $lmb_bram
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk]
|
|||
|
|
## connect_bd_net -net microblaze_0_LMB_Rst [get_bd_pins LMB_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst]
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
## }
|
|||
|
|
## proc create_hier_cell_mbsys { parentCell nameHier } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" || $nameHier eq "" } {
|
|||
|
|
## puts "ERROR: create_hier_cell_mbsys() - Empty argument(s)!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
## # Create cell and set as current instance
|
|||
|
|
## set hier_obj [create_bd_cell -type hier $nameHier]
|
|||
|
|
## current_bd_instance $hier_obj
|
|||
|
|
##
|
|||
|
|
## # Create interface pins
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI
|
|||
|
|
##
|
|||
|
|
## # Create pins
|
|||
|
|
## create_bd_pin -dir I -type clk Clk
|
|||
|
|
## create_bd_pin -dir I -from 0 -to 0 In0
|
|||
|
|
## create_bd_pin -dir I -from 0 -to 0 In1
|
|||
|
|
## create_bd_pin -dir I dcm_locked
|
|||
|
|
## create_bd_pin -dir I -type rst ext_reset_in
|
|||
|
|
## create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn
|
|||
|
|
##
|
|||
|
|
## # Create instance: mdm_1, and set properties
|
|||
|
|
## set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: microblaze_0, and set properties
|
|||
|
|
## set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:10.0 microblaze_0 ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_DEBUG_ENABLED {1} CONFIG.C_D_AXI {1} CONFIG.C_D_LMB {1} CONFIG.C_I_LMB {1} ] $microblaze_0
|
|||
|
|
##
|
|||
|
|
## # Create instance: microblaze_0_axi_intc, and set properties
|
|||
|
|
## set microblaze_0_axi_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 microblaze_0_axi_intc ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_HAS_FAST {1} ] $microblaze_0_axi_intc
|
|||
|
|
##
|
|||
|
|
## # Create instance: microblaze_0_axi_periph, and set properties
|
|||
|
|
## set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]
|
|||
|
|
## set_property -dict [ list CONFIG.NUM_MI {3} ] $microblaze_0_axi_periph
|
|||
|
|
##
|
|||
|
|
## # Create instance: microblaze_0_local_memory
|
|||
|
|
## create_hier_cell_microblaze_0_local_memory $hier_obj microblaze_0_local_memory
|
|||
|
|
##
|
|||
|
|
## # Create instance: microblaze_0_xlconcat, and set properties
|
|||
|
|
## set microblaze_0_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 microblaze_0_xlconcat ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: rst_clk_wiz_1_100M, and set properties
|
|||
|
|
## set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ]
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins M01_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins M02_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_intc_axi [get_bd_intf_pins microblaze_0_axi_intc/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins microblaze_0/INTERRUPT] [get_bd_intf_pins microblaze_0_axi_intc/interrupt]
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net In0_1 [get_bd_pins In0] [get_bd_pins microblaze_0_xlconcat/In0]
|
|||
|
|
## connect_bd_net -net In1_1 [get_bd_pins In1] [get_bd_pins microblaze_0_xlconcat/In1]
|
|||
|
|
## connect_bd_net -net clk_wiz_1_locked [get_bd_pins dcm_locked] [get_bd_pins rst_clk_wiz_1_100M/dcm_locked]
|
|||
|
|
## connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst]
|
|||
|
|
## connect_bd_net -net microblaze_0_Clk [get_bd_pins Clk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_intc/processor_clk] [get_bd_pins microblaze_0_axi_intc/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk]
|
|||
|
|
## connect_bd_net -net microblaze_0_intr [get_bd_pins microblaze_0_axi_intc/intr] [get_bd_pins microblaze_0_xlconcat/dout]
|
|||
|
|
## connect_bd_net -net reset_1 [get_bd_pins ext_reset_in] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]
|
|||
|
|
## connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/LMB_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset]
|
|||
|
|
## connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn]
|
|||
|
|
## connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins microblaze_0_axi_intc/processor_rst] [get_bd_pins rst_clk_wiz_1_100M/mb_reset]
|
|||
|
|
## connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins peripheral_aresetn] [get_bd_pins microblaze_0_axi_intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn]
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
## }
|
|||
|
|
## proc create_hier_cell_nf_mbsys { parentCell nameHier } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" || $nameHier eq "" } {
|
|||
|
|
## puts "ERROR: create_hier_cell_nf_mbsys() - Empty argument(s)!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
## # Create cell and set as current instance
|
|||
|
|
## set hier_obj [create_bd_cell -type hier $nameHier]
|
|||
|
|
## current_bd_instance $hier_obj
|
|||
|
|
##
|
|||
|
|
## # Create interface pins
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart
|
|||
|
|
##
|
|||
|
|
## # Create pins
|
|||
|
|
## create_bd_pin -dir O -from 1 -to 0 iic_reset
|
|||
|
|
## create_bd_pin -dir I -type rst reset
|
|||
|
|
## create_bd_pin -dir I -type clk sysclk
|
|||
|
|
##
|
|||
|
|
## # Create instance: axi_iic_0, and set properties
|
|||
|
|
## set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_GPO_WIDTH {2} CONFIG.C_SCL_INERTIAL_DELAY {5} CONFIG.C_SDA_INERTIAL_DELAY {5} ] $axi_iic_0
|
|||
|
|
##
|
|||
|
|
## # Create instance: axi_uartlite_0, and set properties
|
|||
|
|
## set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
|
|||
|
|
## set_property -dict [ list CONFIG.C_BAUDRATE {115200} ] $axi_uartlite_0
|
|||
|
|
##
|
|||
|
|
## # Create instance: clk_wiz_1, and set properties
|
|||
|
|
## set clk_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_1 ]
|
|||
|
|
## # set_property -dict [ list CONFIG.PRIM_IN_FREQ {200.000} CONFIG.PRIM_SOURCE {No_buffer} ] $clk_wiz_1
|
|||
|
|
##
|
|||
|
|
## # config 100MHz input clk
|
|||
|
|
## set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} CONFIG.PRIM_SOURCE {No_buffer} \
|
|||
|
|
## CONFIG.CLKIN1_JITTER_PS {100.0} CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \
|
|||
|
|
## CONFIG.MMCM_CLKIN1_PERIOD {10.0} CONFIG.CLKOUT1_JITTER {130.958} \
|
|||
|
|
## CONFIG.CLKOUT1_PHASE_ERROR {98.575}] $clk_wiz_1
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create instance: mbsys
|
|||
|
|
## create_hier_cell_mbsys $hier_obj mbsys
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_pins iic_fpga] [get_bd_intf_pins axi_iic_0/IIC]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_pins uart] [get_bd_intf_pins axi_uartlite_0/UART]
|
|||
|
|
## connect_bd_intf_net -intf_net mbsys_M01_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins mbsys/M01_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net mbsys_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins mbsys/M02_AXI]
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net axi_iic_0_gpo [get_bd_pins iic_reset] [get_bd_pins axi_iic_0/gpo]
|
|||
|
|
## connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins mbsys/In0]
|
|||
|
|
## connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins mbsys/In1]
|
|||
|
|
## connect_bd_net -net clk_wiz_1_locked [get_bd_pins clk_wiz_1/locked] [get_bd_pins mbsys/dcm_locked]
|
|||
|
|
## connect_bd_net -net mbsys_peripheral_aresetn [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins mbsys/peripheral_aresetn]
|
|||
|
|
## connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins clk_wiz_1/clk_out1] [get_bd_pins mbsys/Clk]
|
|||
|
|
## connect_bd_net -net reset_1 [get_bd_pins reset] [get_bd_pins clk_wiz_1/reset] [get_bd_pins mbsys/ext_reset_in]
|
|||
|
|
## connect_bd_net -net sysclk_1 [get_bd_pins sysclk] [get_bd_pins clk_wiz_1/clk_in1]
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
## }
|
|||
|
|
## proc create_hier_cell_dma_sub { parentCell nameHier } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" || $nameHier eq "" } {
|
|||
|
|
## puts "ERROR: create_hier_cell_dma_sub() - Empty argument(s)!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
## # Create cell and set as current instance
|
|||
|
|
## set hier_obj [create_bd_cell -type hier $nameHier]
|
|||
|
|
## current_bd_instance $hier_obj
|
|||
|
|
##
|
|||
|
|
## # Create interface pins
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma_tx
|
|||
|
|
## create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_7x_mgt
|
|||
|
|
## create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma_rx
|
|||
|
|
##
|
|||
|
|
## # Create pins
|
|||
|
|
## create_bd_pin -dir I -type clk axi_lite_aclk
|
|||
|
|
## create_bd_pin -dir I -type rst axi_lite_aresetn
|
|||
|
|
## create_bd_pin -dir I -type clk axis_datapath_aclk
|
|||
|
|
## create_bd_pin -dir I -type rst axis_datapath_aresetn
|
|||
|
|
## create_bd_pin -dir I -type clk sys_clk
|
|||
|
|
## create_bd_pin -dir I -type rst sys_reset
|
|||
|
|
##
|
|||
|
|
## create_bd_pin -dir I -type clk M00_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M00_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M01_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M01_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M02_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M02_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M03_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M03_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M04_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M04_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M05_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M05_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M06_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M06_ARESETN
|
|||
|
|
## create_bd_pin -dir I -type clk M07_ACLK
|
|||
|
|
## create_bd_pin -dir I -type rst M07_ARESETN
|
|||
|
|
##
|
|||
|
|
## # Create instance: axi_interconnect_0, and set properties
|
|||
|
|
## set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
|
|||
|
|
## set_property -dict [ list CONFIG.NUM_MI {9} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.M08_HAS_REGSLICE {3} CONFIG.M08_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
## set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
|
|||
|
|
##
|
|||
|
|
## # AXIS: clock domain crossing FIFO, TX (PCIe->FPGA) user_fifo_reset (user_clk)
|
|||
|
|
## set pcie_reset_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic pcie_reset_inv]
|
|||
|
|
## set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {not}] [get_bd_cells pcie_reset_inv]
|
|||
|
|
##
|
|||
|
|
## # Create instance: axis_dwidth_converter
|
|||
|
|
## set axis_dwidth_dma_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_dma_tx]
|
|||
|
|
## set_property -dict [list CONFIG.HAS_TKEEP.VALUE_SRC USER CONFIG.HAS_TLAST.VALUE_SRC USER \
|
|||
|
|
## CONFIG.HAS_TSTRB.VALUE_SRC USER CONFIG.S_TDATA_NUM_BYTES.VALUE_SRC USER \
|
|||
|
|
## CONFIG.TUSER_BITS_PER_BYTE.VALUE_SRC USER] $axis_dwidth_dma_tx
|
|||
|
|
##
|
|||
|
|
## set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {16} CONFIG.M_TDATA_NUM_BYTES {32} \
|
|||
|
|
## CONFIG.TUSER_BITS_PER_BYTE {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TSTRB {0} \
|
|||
|
|
## CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1}] $axis_dwidth_dma_tx
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## set axis_dwidth_dma_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_dma_rx]
|
|||
|
|
##
|
|||
|
|
## set_property -dict [list CONFIG.HAS_TKEEP.VALUE_SRC USER CONFIG.HAS_TLAST.VALUE_SRC USER \
|
|||
|
|
## CONFIG.HAS_TSTRB.VALUE_SRC USER CONFIG.S_TDATA_NUM_BYTES.VALUE_SRC USER \
|
|||
|
|
## CONFIG.TUSER_BITS_PER_BYTE.VALUE_SRC USER] $axis_dwidth_dma_rx
|
|||
|
|
##
|
|||
|
|
## set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {32} CONFIG.M_TDATA_NUM_BYTES {16} \
|
|||
|
|
## CONFIG.TUSER_BITS_PER_BYTE {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TSTRB {0} \
|
|||
|
|
## CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1}] $axis_dwidth_dma_rx
|
|||
|
|
##
|
|||
|
|
## # Create instance: axis_fifo_10g_rx, and set properties
|
|||
|
|
## set axis_fifo_10g_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_fifo_10g_rx]
|
|||
|
|
## set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.TUSER_WIDTH {128} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32}] $axis_fifo_10g_rx
|
|||
|
|
##
|
|||
|
|
## # Create instance: axis_fifo_10g_tx, and set properties
|
|||
|
|
## set axis_fifo_10g_tx [create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_fifo_10g_tx]
|
|||
|
|
## set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.TUSER_WIDTH {128} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32}] $axis_fifo_10g_tx
|
|||
|
|
##
|
|||
|
|
## # Create instance: nf_riffa_dma_1, and set properties
|
|||
|
|
## set nf_riffa_dma_1 [ create_bd_cell -type ip -vlnv NetFPGA:NetFPGA:nf_riffa_dma:1.0 nf_riffa_dma_1 ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: axi_clock_converter_0, and set properties
|
|||
|
|
## set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
|
|||
|
|
##
|
|||
|
|
## # Create instance: pcie3_7x_1, and set properties
|
|||
|
|
## set pcie3_7x_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:pcie3_7x:4.3 pcie3_7x_1 ]
|
|||
|
|
## set_property -dict [ list CONFIG.PF0_DEVICE_ID {7028} \
|
|||
|
|
## CONFIG.PF0_INTERRUPT_PIN {NONE} CONFIG.PF1_DEVICE_ID {7011} \
|
|||
|
|
## CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {5.0_GT/s} CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
|
|||
|
|
## CONFIG.axisten_freq {250} CONFIG.axisten_if_enable_client_tag {false} \
|
|||
|
|
## CONFIG.axisten_if_width {128_bit} CONFIG.cfg_ctl_if {false} \
|
|||
|
|
## CONFIG.cfg_ext_if {false} CONFIG.cfg_mgmt_if {false} \
|
|||
|
|
## CONFIG.cfg_tx_msg_if {false} CONFIG.en_ext_clk {false} \
|
|||
|
|
## CONFIG.extended_tag_field {true} CONFIG.gen_x0y0 {false} \
|
|||
|
|
## CONFIG.mode_selection {Advanced} CONFIG.pcie_blk_locn {X0Y1} \
|
|||
|
|
## CONFIG.per_func_status_if {false} CONFIG.pf0_bar0_size {1} \
|
|||
|
|
## CONFIG.pf0_dev_cap_max_payload {128_bytes} CONFIG.rcv_msg_if {false} \
|
|||
|
|
## CONFIG.tx_fc_if {false} CONFIG.xlnx_ref_board {None} \
|
|||
|
|
## ] $pcie3_7x_1
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI]
|
|||
|
|
##
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_dma_rx [get_bd_intf_pins s_axis_dma_rx] [get_bd_intf_pins axis_dwidth_dma_rx/S_AXIS]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_fifo_dwidth_rx [get_bd_intf_pins axis_fifo_10g_rx/S_AXIS] [get_bd_intf_pins axis_dwidth_dma_rx/M_AXIS]
|
|||
|
|
## connect_bd_intf_net -intf_net axis_fifo_10g_rx_M_AXIS [get_bd_intf_pins axis_fifo_10g_rx/M_AXIS] [get_bd_intf_pins nf_riffa_dma_1/s_axis_xge_rx]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_m_axis_dma_tx [get_bd_intf_pins m_axis_dma_tx] [get_bd_intf_pins axis_dwidth_dma_tx/M_AXIS]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_fifo_dwidth_tx [get_bd_intf_pins axis_fifo_10g_tx/M_AXIS] [get_bd_intf_pins axis_dwidth_dma_tx/S_AXIS]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_dwidth_conv_tx [get_bd_intf_pins axis_fifo_10g_tx/S_AXIS] [get_bd_intf_pins nf_riffa_dma_1/m_axis_xge_tx]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_interrupt [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_interrupt]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_msi [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt_msi] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_msi]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_status [get_bd_intf_pins nf_riffa_dma_1/cfg] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_status]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie_cfg_fc [get_bd_intf_pins nf_riffa_dma_1/cfg_fc] [get_bd_intf_pins pcie3_7x_1/pcie_cfg_fc]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_cc [get_bd_intf_pins nf_riffa_dma_1/s_axis_cc] [get_bd_intf_pins pcie3_7x_1/s_axis_cc]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_rq [get_bd_intf_pins nf_riffa_dma_1/s_axis_rq] [get_bd_intf_pins pcie3_7x_1/s_axis_rq]
|
|||
|
|
## connect_bd_intf_net -intf_net pcie3_7x_1_m_axis_cq [get_bd_intf_pins nf_riffa_dma_1/m_axis_cq] [get_bd_intf_pins pcie3_7x_1/m_axis_cq]
|
|||
|
|
## connect_bd_intf_net -intf_net pcie3_7x_1_m_axis_rc [get_bd_intf_pins nf_riffa_dma_1/m_axis_rc] [get_bd_intf_pins pcie3_7x_1/m_axis_rc]
|
|||
|
|
## connect_bd_intf_net -intf_net pcie3_7x_1_pcie_7x_mgt [get_bd_intf_pins pcie_7x_mgt] [get_bd_intf_pins pcie3_7x_1/pcie_7x_mgt]
|
|||
|
|
## connect_bd_intf_net -intf_net s00_axi_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins nf_riffa_dma_1/m_axi_lite]
|
|||
|
|
##
|
|||
|
|
## #Clock converter connections
|
|||
|
|
## connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins nf_riffa_dma_1/s_axi_lite]
|
|||
|
|
## connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M08_AXI]
|
|||
|
|
## set_property -dict [ list CONFIG.FREQ_HZ {250000000} ] [get_bd_intf_pins nf_riffa_dma_1/s_axi_lite]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net axi_lite_clk_1 [get_bd_pins axi_lite_aclk] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins nf_riffa_dma_1/m_axi_lite_aclk]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net M00_ACLK_i [get_bd_pins M00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK]
|
|||
|
|
## connect_bd_net -net M01_ACLK_i [get_bd_pins M01_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK]
|
|||
|
|
## connect_bd_net -net M02_ACLK_i [get_bd_pins M02_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK]
|
|||
|
|
## connect_bd_net -net M03_ACLK_i [get_bd_pins M03_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK]
|
|||
|
|
## connect_bd_net -net M04_ACLK_i [get_bd_pins M04_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK]
|
|||
|
|
## connect_bd_net -net M05_ACLK_i [get_bd_pins M05_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK]
|
|||
|
|
## connect_bd_net -net M06_ACLK_i [get_bd_pins M06_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK]
|
|||
|
|
## connect_bd_net -net M07_ACLK_i [get_bd_pins M07_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net axi_lite_rstn_1 [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_lite_aresetn] [get_bd_pins nf_riffa_dma_1/m_axi_lite_aresetn]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net M00_ARESETN_i [get_bd_pins M00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN]
|
|||
|
|
## connect_bd_net -net M01_ARESETN_i [get_bd_pins M01_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN]
|
|||
|
|
## connect_bd_net -net M02_ARESETN_i [get_bd_pins M02_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN]
|
|||
|
|
## connect_bd_net -net M03_ARESETN_i [get_bd_pins M03_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN]
|
|||
|
|
## connect_bd_net -net M04_ARESETN_i [get_bd_pins M04_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN]
|
|||
|
|
## connect_bd_net -net M05_ARESETN_i [get_bd_pins M05_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN]
|
|||
|
|
## connect_bd_net -net M06_ARESETN_i [get_bd_pins M06_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN]
|
|||
|
|
## connect_bd_net -net M07_ARESETN_i [get_bd_pins M07_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net axis_10g_clk_1 [get_bd_pins axis_datapath_aclk] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axis_dwidth_dma_rx/aclk] [get_bd_pins axis_dwidth_dma_tx/aclk] [get_bd_pins axis_fifo_10g_rx/s_axis_aclk] [get_bd_pins axis_fifo_10g_tx/m_axis_aclk]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net axis_rx_sys_reset_0_peripheral_aresetn [get_bd_pins axis_datapath_aresetn] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axis_dwidth_dma_rx/aresetn] [get_bd_pins axis_dwidth_dma_tx/aresetn] [get_bd_pins axis_fifo_10g_rx/s_axis_aresetn] [get_bd_pins axis_fifo_10g_tx/m_axis_aresetn]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net axis_tx_sys_reset_0_peripheral_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axis_fifo_10g_rx/m_axis_aresetn] [get_bd_pins axis_fifo_10g_tx/s_axis_aresetn] [get_bd_pins pcie_reset_inv/Res]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net pcie3_7x_1_user_clk [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axis_fifo_10g_rx/m_axis_aclk] [get_bd_pins axis_fifo_10g_tx/s_axis_aclk] [get_bd_pins nf_riffa_dma_1/user_clk] [get_bd_pins pcie3_7x_1/user_clk]
|
|||
|
|
##
|
|||
|
|
## connect_bd_net -net pcie3_7x_1_user_lnk_up [get_bd_pins nf_riffa_dma_1/user_lnk_up] [get_bd_pins pcie3_7x_1/user_lnk_up]
|
|||
|
|
## connect_bd_net -net pcie3_7x_1_user_reset [get_bd_pins pcie_reset_inv/Op1] [get_bd_pins nf_riffa_dma_1/user_reset] [get_bd_pins pcie3_7x_1/user_reset]
|
|||
|
|
## connect_bd_net -net sys_clk_1 [get_bd_pins sys_clk] [get_bd_pins pcie3_7x_1/sys_clk]
|
|||
|
|
## connect_bd_net -net sys_reset_1 [get_bd_pins sys_reset] [get_bd_pins pcie3_7x_1/sys_reset]
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
## }
|
|||
|
|
## proc create_root_design { parentCell } {
|
|||
|
|
##
|
|||
|
|
## if { $parentCell eq "" } {
|
|||
|
|
## set parentCell [get_bd_cells /]
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Get object for parentCell
|
|||
|
|
## set parentObj [get_bd_cells $parentCell]
|
|||
|
|
## if { $parentObj == "" } {
|
|||
|
|
## puts "ERROR: Unable to find parent cell <$parentCell>!"
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Make sure parentObj is hier blk
|
|||
|
|
## set parentType [get_property TYPE $parentObj]
|
|||
|
|
## if { $parentType ne "hier" } {
|
|||
|
|
## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
|||
|
|
## return
|
|||
|
|
## }
|
|||
|
|
##
|
|||
|
|
## # Save current instance; Restore later
|
|||
|
|
## set oldCurInst [current_bd_instance .]
|
|||
|
|
##
|
|||
|
|
## # Set parent object as current
|
|||
|
|
## current_bd_instance $parentObj
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create interface ports
|
|||
|
|
## set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI
|
|||
|
|
## set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M01_AXI
|
|||
|
|
## set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M02_AXI
|
|||
|
|
## set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M03_AXI
|
|||
|
|
## set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M04_AXI
|
|||
|
|
## set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M05_AXI
|
|||
|
|
## set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M06_AXI
|
|||
|
|
## set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ]
|
|||
|
|
## set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M07_AXI
|
|||
|
|
## set iic_fpga [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga ]
|
|||
|
|
## set m_axis_dma_tx [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma_tx ]
|
|||
|
|
## set pcie_7x_mgt [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_7x_mgt ]
|
|||
|
|
## set s_axis_dma_rx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma_rx ]
|
|||
|
|
## set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} CONFIG.HAS_TREADY {1} CONFIG.HAS_TSTRB {0} CONFIG.LAYERED_METADATA {undef} CONFIG.PHASE {0.000} CONFIG.TDATA_NUM_BYTES {32} CONFIG.TDEST_WIDTH {0} CONFIG.TID_WIDTH {0} CONFIG.TUSER_WIDTH {128} ] $s_axis_dma_rx
|
|||
|
|
## set uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart ]
|
|||
|
|
##
|
|||
|
|
## # Create ports
|
|||
|
|
## set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ]
|
|||
|
|
## set axi_lite_aresetn [ create_bd_port -dir I -type rst axi_lite_aresetn ]
|
|||
|
|
## set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}] $axi_lite_aresetn
|
|||
|
|
## set axis_datapath_aclk [ create_bd_port -dir I -type clk axis_datapath_aclk ]
|
|||
|
|
## set axis_datapath_aresetn [ create_bd_port -dir I -type rst axis_datapath_aresetn ]
|
|||
|
|
## set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $axis_datapath_aresetn
|
|||
|
|
## set iic_reset [ create_bd_port -dir O -from 1 -to 0 iic_reset ]
|
|||
|
|
## set sys_clk [ create_bd_port -dir I -type clk sys_clk ]
|
|||
|
|
## set_property -dict [ list CONFIG.FREQ_HZ {100000000} ] $sys_clk
|
|||
|
|
## set sys_reset [ create_bd_port -dir I -type rst sys_reset ]
|
|||
|
|
## set_property -dict [ list CONFIG.POLARITY {ACTIVE_HIGH} ] $sys_reset
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create instance: dma_sub
|
|||
|
|
## create_hier_cell_dma_sub [current_bd_instance .] dma_sub
|
|||
|
|
##
|
|||
|
|
## # Create instance: nf_mbsys
|
|||
|
|
## create_hier_cell_nf_mbsys [current_bd_instance .] nf_mbsys
|
|||
|
|
##
|
|||
|
|
## # Create interface connections
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins dma_sub/M00_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins dma_sub/M01_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins dma_sub/M02_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins dma_sub/M03_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins dma_sub/M04_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins dma_sub/M05_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins dma_sub/M06_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins dma_sub/M07_AXI]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_m_axis_dma_tx [get_bd_intf_ports m_axis_dma_tx] [get_bd_intf_pins dma_sub/m_axis_dma_tx]
|
|||
|
|
## connect_bd_intf_net -intf_net dma_sub_pcie_7x_mgt [get_bd_intf_ports pcie_7x_mgt] [get_bd_intf_pins dma_sub/pcie_7x_mgt]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_mbsys_iic_fpga [get_bd_intf_ports iic_fpga] [get_bd_intf_pins nf_mbsys/iic_fpga]
|
|||
|
|
## connect_bd_intf_net -intf_net nf_mbsys_uart [get_bd_intf_ports uart] [get_bd_intf_pins nf_mbsys/uart]
|
|||
|
|
## connect_bd_intf_net -intf_net s_axis_dma_rx_1 [get_bd_intf_ports s_axis_dma_rx] [get_bd_intf_pins dma_sub/s_axis_dma_rx]
|
|||
|
|
##
|
|||
|
|
## # Create port connections
|
|||
|
|
## connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk] [get_bd_pins dma_sub/axi_lite_aclk]
|
|||
|
|
## connect_bd_net -net axi_lite_aresetn_1 [get_bd_ports axi_lite_aresetn] [get_bd_pins dma_sub/axi_lite_aresetn]
|
|||
|
|
## connect_bd_net -net axis_datapath_aclk_1 [get_bd_ports axis_datapath_aclk] [get_bd_pins dma_sub/axis_datapath_aclk] [get_bd_pins dma_sub/M00_ACLK] [get_bd_pins dma_sub/M01_ACLK] [get_bd_pins dma_sub/M02_ACLK] [get_bd_pins dma_sub/M03_ACLK] [get_bd_pins dma_sub/M04_ACLK] [get_bd_pins dma_sub/M05_ACLK] [get_bd_pins dma_sub/M06_ACLK] [get_bd_pins dma_sub/M07_ACLK]
|
|||
|
|
## connect_bd_net -net axis_datapath_aresetn_1 [get_bd_ports axis_datapath_aresetn] [get_bd_pins dma_sub/axis_datapath_aresetn] [get_bd_pins dma_sub/M00_ARESETN] [get_bd_pins dma_sub/M01_ARESETN] [get_bd_pins dma_sub/M02_ARESETN] [get_bd_pins dma_sub/M03_ARESETN] [get_bd_pins dma_sub/M04_ARESETN] [get_bd_pins dma_sub/M05_ARESETN] [get_bd_pins dma_sub/M06_ARESETN] [get_bd_pins dma_sub/M07_ARESETN]
|
|||
|
|
## connect_bd_net -net nf_mbsys_iic_reset [get_bd_ports iic_reset] [get_bd_pins nf_mbsys/iic_reset]
|
|||
|
|
## connect_bd_net -net sys_clk_1 [get_bd_ports sys_clk] [get_bd_pins dma_sub/sys_clk] [get_bd_pins nf_mbsys/sysclk]
|
|||
|
|
## connect_bd_net -net sys_reset_1 [get_bd_ports sys_reset] [get_bd_pins dma_sub/sys_reset] [get_bd_pins nf_mbsys/reset]
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Create address segments
|
|||
|
|
## source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl
|
|||
|
|
## create_bd_addr_seg -range $M00_SIZEADDR -offset $M00_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M01_SIZEADDR -offset $M01_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M01_AXI/Reg] SEG_M01_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M02_SIZEADDR -offset $M02_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M02_AXI/Reg] SEG_M02_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M03_SIZEADDR -offset $M03_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M03_AXI/Reg] SEG_M03_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M04_SIZEADDR -offset $M04_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M04_AXI/Reg] SEG_M04_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M05_SIZEADDR -offset $M05_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M05_AXI/Reg] SEG_M05_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M06_SIZEADDR -offset $M06_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M06_AXI/Reg] SEG_M06_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M07_SIZEADDR -offset $M07_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M07_AXI/Reg] SEG_M07_AXI_Reg
|
|||
|
|
## create_bd_addr_seg -range $M08_SIZEADDR -offset $M08_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs dma_sub/nf_riffa_dma_1/s_axi_lite/reg0] SEG_nf_riffa_dma_1_reg0
|
|||
|
|
##
|
|||
|
|
## create_bd_addr_seg -range $MICROBLAZE_AXI_IIC_SIZEADDR -offset $MICROBLAZE_AXI_IIC_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg
|
|||
|
|
## create_bd_addr_seg -range $MICROBLAZE_UARTLITE_SIZEADDR -offset $MICROBLAZE_UARTLITE_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
|
|||
|
|
## create_bd_addr_seg -range $MICROBLAZE_DLMB_BRAM_SIZEADDR -offset $MICROBLAZE_DLMB_BRAM_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem
|
|||
|
|
## create_bd_addr_seg -range $MICROBLAZE_ILMB_BRAM_SIZEADDR -offset $MICROBLAZE_ILMB_BRAM_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Instruction] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem
|
|||
|
|
## create_bd_addr_seg -range $MICROBLAZE_AXI_INTC_SIZEADDR -offset $MICROBLAZE_AXI_INTC_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_axi_intc/s_axi/Reg] SEG_microblaze_0_axi_intc_Reg
|
|||
|
|
##
|
|||
|
|
##
|
|||
|
|
## # Restore current instance
|
|||
|
|
## current_bd_instance $oldCurInst
|
|||
|
|
##
|
|||
|
|
## save_bd_design
|
|||
|
|
## }
|
|||
|
|
## create_root_design ""
|
|||
|
|
CRITICAL WARNING: [BD 41-737] Cannot set the parameter FREQ_HZ on /dma_sub/nf_riffa_dma_1/s_axi_lite. It is read-only.
|
|||
|
|
create_bd_cell: Time (s): cpu = 00:00:22 ; elapsed = 00:00:57 . Memory (MB): peak = 1703.027 ; gain = 287.730 ; free physical = 13196 ; free virtual = 15685
|
|||
|
|
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '10.000' to '10.0' has been ignored for IP 'nf_mbsys/clk_wiz_1'
|
|||
|
|
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
|
|||
|
|
### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
|
|||
|
|
### set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
|
|||
|
|
### set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
|
|||
|
|
### set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
|
|||
|
|
### set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
|
|||
|
|
### set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
|
|||
|
|
### set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
|
|||
|
|
### set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
|
|||
|
|
### set M00_BASEADDR 0x44000000
|
|||
|
|
### set M00_HIGHADDR 0x44000FFF
|
|||
|
|
### set M00_SIZEADDR 0x1000
|
|||
|
|
### set M01_BASEADDR 0x44010000
|
|||
|
|
### set M01_HIGHADDR 0x44010FFF
|
|||
|
|
### set M01_SIZEADDR 0x1000
|
|||
|
|
### set M02_BASEADDR 0x44020000
|
|||
|
|
### set M02_HIGHADDR 0x44020FFF
|
|||
|
|
### set M02_SIZEADDR 0x1000
|
|||
|
|
### set M03_BASEADDR 0x44030000
|
|||
|
|
### set M03_HIGHADDR 0x44030FFF
|
|||
|
|
### set M03_SIZEADDR 0x1000
|
|||
|
|
### set M04_BASEADDR 0x44040000
|
|||
|
|
### set M04_HIGHADDR 0x44040FFF
|
|||
|
|
### set M04_SIZEADDR 0x1000
|
|||
|
|
### set M05_BASEADDR 0x44050000
|
|||
|
|
### set M05_HIGHADDR 0x44050FFF
|
|||
|
|
### set M05_SIZEADDR 0x1000
|
|||
|
|
### set M06_BASEADDR 0x44060000
|
|||
|
|
### set M06_HIGHADDR 0x44060FFF
|
|||
|
|
### set M06_SIZEADDR 0x1000
|
|||
|
|
### set M07_BASEADDR 0x44070000
|
|||
|
|
### set M07_HIGHADDR 0x44070FFF
|
|||
|
|
### set M07_SIZEADDR 0x1000
|
|||
|
|
### set M08_BASEADDR 0x44080000
|
|||
|
|
### set M08_HIGHADDR 0x44080FFF
|
|||
|
|
### set M08_SIZEADDR 0x1000
|
|||
|
|
### set IDENTIFIER_BASEADDR $M00_BASEADDR
|
|||
|
|
### set IDENTIFIER_HIGHADDR $M00_HIGHADDR
|
|||
|
|
### set IDENTIFIER_SIZEADDR $M00_SIZEADDR
|
|||
|
|
### set INPUT_ARBITER_BASEADDR $M01_BASEADDR
|
|||
|
|
### set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
|
|||
|
|
### set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
|
|||
|
|
### set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
|
|||
|
|
### set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
|
|||
|
|
### set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
|
|||
|
|
### set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
|||
|
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
|||
|
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
|||
|
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
|||
|
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
|||
|
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
|||
|
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
|||
|
|
# create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci]
|
|||
|
|
# reset_target all [get_ips nf_sume_sdnet_ip]
|
|||
|
|
# generate_target all [get_ips nf_sume_sdnet_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_sume_sdnet_ip'...
|
|||
|
|
# source ./create_ip/nf_10ge_interface.tcl
|
|||
|
|
## set sharedLogic "FALSE"
|
|||
|
|
## set tdataWidth 256
|
|||
|
|
## set convWidth [expr $tdataWidth/8]
|
|||
|
|
## if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } {
|
|||
|
|
## set supportLevel 1
|
|||
|
|
## } else {
|
|||
|
|
## set supportLevel 0
|
|||
|
|
## }
|
|||
|
|
## create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_nonshared
|
|||
|
|
WARNING: [IP_Flow 19-4832] The IP name 'axi_10g_ethernet_nonshared' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues.
|
|||
|
|
## set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
|
|||
|
|
## set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
|
|||
|
|
## set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
## set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
## set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
## set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
## set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_nonshared.xci]
|
|||
|
|
## reset_target all [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
## generate_target all [get_ips axi_10g_ethernet_nonshared]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_10g_ethernet_nonshared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_10g_ethernet_nonshared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_10g_ethernet_nonshared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_10g_ethernet_nonshared'...
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/hw_handoff/axi_10g_ethernet_nonshared.hwh
|
|||
|
|
Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/hw_handoff/axi_10g_ethernet_nonshared_bd.tcl
|
|||
|
|
Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/synth/axi_10g_ethernet_nonshared.hwdef
|
|||
|
|
generate_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1942.422 ; gain = 43.977 ; free physical = 12923 ; free virtual = 15466
|
|||
|
|
## create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_status
|
|||
|
|
## set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Performance_Options {First_Word_Fall_Through}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Input_Data_Width {458} CONFIG.Input_Depth {16}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Reset_Pin {false}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Output_Data_Width {458} CONFIG.Output_Depth {16}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Full_Flags_Reset_Value {0}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Use_Dout_Reset {false}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Data_Count_Width {4}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Write_Data_Count_Width {4}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Read_Data_Count_Width {4}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Full_Threshold_Assert_Value {15}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Full_Threshold_Negate_Value {14}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Empty_Threshold_Assert_Value {4}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property -dict [list CONFIG.Empty_Threshold_Negate_Value {5}] [get_ips fifo_generator_status]
|
|||
|
|
## set_property generate_synth_checkpoint false [get_files fifo_generator_status.xci]
|
|||
|
|
## reset_target all [get_ips fifo_generator_status]
|
|||
|
|
## generate_target all [get_ips fifo_generator_status]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fifo_generator_status'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_generator_status'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fifo_generator_status'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fifo_generator_status'...
|
|||
|
|
## create_ip -name util_vector_logic -vendor xilinx.com -library ip -version 2.0 -module_name inverter_0
|
|||
|
|
WARNING: [Coretcl 2-1618] The 'xilinx.com:ip:util_vector_logic:2.0' IP is intended for use in IPI only.
|
|||
|
|
## set_property -dict [list CONFIG.C_SIZE {1}] [get_ips inverter_0]
|
|||
|
|
## set_property -dict [list CONFIG.C_OPERATION {not}] [get_ips inverter_0]
|
|||
|
|
## set_property generate_synth_checkpoint false [get_files inverter_0.xci]
|
|||
|
|
## reset_target all [get_ips inverter_0]
|
|||
|
|
## generate_target all [get_ips inverter_0]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'inverter_0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'inverter_0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'inverter_0'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'inverter_0'...
|
|||
|
|
## create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_1_9
|
|||
|
|
## set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM} CONFIG.Performance_Options {First_Word_Fall_Through} CONFIG.Input_Data_Width {1} CONFIG.Input_Depth {16} CONFIG.Output_Data_Width {1} CONFIG.Output_Depth {16} CONFIG.Data_Count_Width {4} CONFIG.Write_Data_Count_Width {4} CONFIG.Read_Data_Count_Width {4} CONFIG.Full_Threshold_Assert_Value {13} CONFIG.Full_Threshold_Negate_Value {12}] [get_ips fifo_generator_1_9]
|
|||
|
|
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Assert_Value' from '15' to '13' has been ignored for IP 'fifo_generator_1_9'
|
|||
|
|
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Negate_Value' from '14' to '12' has been ignored for IP 'fifo_generator_1_9'
|
|||
|
|
## set_property generate_synth_checkpoint false [get_files fifo_generator_1_9.xci]
|
|||
|
|
## reset_target all [get_ips fifo_generator_1_9]
|
|||
|
|
## generate_target all [get_ips fifo_generator_1_9]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fifo_generator_1_9'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_generator_1_9'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fifo_generator_1_9'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fifo_generator_1_9'...
|
|||
|
|
# create_ip -name nf_10ge_interface -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_ip
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files nf_10g_interface_ip.xci]
|
|||
|
|
# reset_target all [get_ips nf_10g_interface_ip]
|
|||
|
|
# generate_target all [get_ips nf_10g_interface_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_10g_interface_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_10g_interface_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_10g_interface_ip'...
|
|||
|
|
generate_target: Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1987.246 ; gain = 38.785 ; free physical = 12835 ; free virtual = 15457
|
|||
|
|
# source ./create_ip/nf_10ge_interface_shared.tcl
|
|||
|
|
## set sharedLogic "TRUE"
|
|||
|
|
## set tdataWidth 256
|
|||
|
|
## set convWidth [expr $tdataWidth/8]
|
|||
|
|
## if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } {
|
|||
|
|
## set supportLevel 1
|
|||
|
|
## } else {
|
|||
|
|
## set supportLevel 0
|
|||
|
|
## }
|
|||
|
|
## create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_shared
|
|||
|
|
## set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
|
|||
|
|
## set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
|
|||
|
|
## set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
WARNING: [BD 41-1306] The connection to interface pin /xpcs/refclk_p is being overridden by the user. This pin will not be connected as a part of interface connection refclk_diff_port
|
|||
|
|
WARNING: [BD 41-1306] The connection to interface pin /xpcs/refclk_n is being overridden by the user. This pin will not be connected as a part of interface connection refclk_diff_port
|
|||
|
|
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {Mode=="Slave" && VLNV=="xilinx.com:interface:aximm_rtl:1.0"}'
|
|||
|
|
## set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
## set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
## set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_shared]
|
|||
|
|
## set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_shared.xci]
|
|||
|
|
## reset_target all [get_ips axi_10g_ethernet_shared]
|
|||
|
|
## generate_target all [get_ips axi_10g_ethernet_shared]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_10g_ethernet_shared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_10g_ethernet_shared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_10g_ethernet_shared'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_10g_ethernet_shared'...
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
|
|||
|
|
Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/hw_handoff/axi_10g_ethernet_shared.hwh
|
|||
|
|
Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/hw_handoff/axi_10g_ethernet_shared_bd.tcl
|
|||
|
|
Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/synth/axi_10g_ethernet_shared.hwdef
|
|||
|
|
generate_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2002.578 ; gain = 15.328 ; free physical = 12776 ; free virtual = 15404
|
|||
|
|
# create_ip -name nf_10ge_interface_shared -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_shared_ip
|
|||
|
|
WARNING: [IP_Flow 19-4832] The IP name 'nf_10g_interface_shared_ip' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues.
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files nf_10g_interface_shared_ip.xci]
|
|||
|
|
# reset_target all [get_ips nf_10g_interface_shared_ip]
|
|||
|
|
# generate_target all [get_ips nf_10g_interface_shared_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'nf_10g_interface_shared_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'nf_10g_interface_shared_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'nf_10g_interface_shared_ip'...
|
|||
|
|
generate_target: Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 2040.105 ; gain = 37.527 ; free physical = 12755 ; free virtual = 15402
|
|||
|
|
# create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip
|
|||
|
|
# set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip]
|
|||
|
|
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '5.000' to '5.0' has been ignored for IP 'clk_wiz_ip'
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci]
|
|||
|
|
# reset_target all [get_ips clk_wiz_ip]
|
|||
|
|
# generate_target all [get_ips clk_wiz_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_ip'...
|
|||
|
|
# create_ip -name proc_sys_reset -vendor xilinx.com -library ip -version 5.0 -module_name proc_sys_reset_ip
|
|||
|
|
# set_property -dict [list CONFIG.C_EXT_RESET_HIGH {0} CONFIG.C_AUX_RESET_HIGH {0}] [get_ips proc_sys_reset_ip]
|
|||
|
|
# set_property -dict [list CONFIG.C_NUM_PERP_RST {1} CONFIG.C_NUM_PERP_ARESETN {1}] [get_ips proc_sys_reset_ip]
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files proc_sys_reset_ip.xci]
|
|||
|
|
# reset_target all [get_ips proc_sys_reset_ip]
|
|||
|
|
# generate_target all [get_ips proc_sys_reset_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'proc_sys_reset_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'proc_sys_reset_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'proc_sys_reset_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'proc_sys_reset_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'proc_sys_reset_ip'...
|
|||
|
|
# create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip
|
|||
|
|
# set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {4096} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip]
|
|||
|
|
# set_property generate_synth_checkpoint false [get_files identifier_ip.xci]
|
|||
|
|
# reset_target all [get_ips identifier_ip]
|
|||
|
|
# generate_target all [get_ips identifier_ip]
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'identifier_ip'...
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'identifier_ip'...
|
|||
|
|
# read_verilog "./hdl/axi_clocking.v"
|
|||
|
|
# read_verilog "./hdl/nf_datapath.v"
|
|||
|
|
# read_verilog "./hdl/top.v"
|
|||
|
|
# create_run -flow {Vivado Synthesis 2018} synth
|
|||
|
|
Run is defaulting to srcset: sources_1
|
|||
|
|
Run is defaulting to constrset: constraints
|
|||
|
|
Run is defaulting to part: xc7vx690tffg1761-3
|
|||
|
|
# create_run impl -parent_run synth -flow {Vivado Implementation 2018}
|
|||
|
|
Run is defaulting to parent run srcset: sources_1
|
|||
|
|
Run is defaulting to parent run constrset: constraints
|
|||
|
|
Run is defaulting to parent run part: xc7vx690tffg1761-3
|
|||
|
|
# set_property steps.phys_opt_design.is_enabled true [get_runs impl_1]
|
|||
|
|
# set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE ExploreWithHoldFix [get_runs impl_1]
|
|||
|
|
# set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
|
|||
|
|
# set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.is_enabled true [get_runs impl_1]
|
|||
|
|
# set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
|||
|
|
# set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
|
|||
|
|
# launch_runs synth
|
|||
|
|
INFO: [xilinx.com:ip:axi_intc:4.1-1] /nf_mbsys/mbsys/microblaze_0_axi_intc: The AXI INTC core has been configured to operate with synchronous clocks.
|
|||
|
|
INFO: [xilinx.com:ip:axi_intc:4.1-1] /nf_mbsys/mbsys/microblaze_0_axi_intc: The AXI INTC core has been configured to operate with synchronous clocks.
|
|||
|
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
|||
|
|
VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v
|
|||
|
|
VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/sim/control_sub.v
|
|||
|
|
VHDL Output written to : /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hdl/control_sub_wrapper.v
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/axi_iic_0 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/axi_uartlite_0 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/clk_wiz_1 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/mdm_1 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_axi_intc .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_xlconcat .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/rst_clk_wiz_1_100M .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block nf_mbsys/mbsys/microblaze_0_axi_periph/xbar .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/pcie_reset_inv .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_dwidth_dma_tx .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_dwidth_dma_rx .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_fifo_10g_rx .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axis_fifo_10g_tx .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/nf_riffa_dma_1 .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_ooc.xdc'
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_clock_converter_0 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/pcie3_7x_1 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/xbar .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0_ooc.xdc'
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0_ooc.xdc'
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0_ooc.xdc'
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0_ooc.xdc'
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0_ooc.xdc'
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0_ooc.xdc'
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0_ooc.xdc'
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0_ooc.xdc'
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0_ooc.xdc'
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0_ooc.xdc'
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo .
|
|||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_ooc.xdc'
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INFO: [BD 41-1029] Generation completed for the IP Integrator block dma_sub/axi_interconnect_0/s00_couplers/auto_cc .
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Exporting to file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hw_handoff/control_sub.hwh
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Generated Block Design Tcl file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/hw_handoff/control_sub_bd.tcl
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Generated Hardware Definition File /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.hwdef
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[Sun Jul 28 17:03:49 2019] Launched control_sub_m07_data_fifo_0_synth_1, control_sub_mdm_1_0_synth_1, control_sub_clk_wiz_1_0_synth_1, control_sub_axi_uartlite_0_0_synth_1, control_sub_axi_iic_0_0_synth_1, control_sub_ilmb_v10_0_synth_1, control_sub_lmb_bram_0_synth_1, control_sub_xbar_1_synth_1, control_sub_pcie_reset_inv_0_synth_1, control_sub_axis_dwidth_dma_tx_0_synth_1, control_sub_axis_dwidth_dma_rx_0_synth_1, control_sub_axis_fifo_10g_rx_0_synth_1, control_sub_axis_fifo_10g_tx_0_synth_1, control_sub_nf_riffa_dma_1_0_synth_1, control_sub_axi_clock_converter_0_0_synth_1, control_sub_pcie3_7x_1_0_synth_1, control_sub_xbar_0_synth_1, control_sub_microblaze_0_0_synth_1, control_sub_microblaze_0_axi_intc_0_synth_1, control_sub_microblaze_0_xlconcat_0_synth_1, control_sub_rst_clk_wiz_1_100M_0_synth_1, control_sub_dlmb_bram_if_cntlr_0_synth_1, control_sub_dlmb_v10_0_synth_1, control_sub_ilmb_bram_if_cntlr_0_synth_1, control_sub_m08_data_fifo_0_synth_1, control_sub_m06_data_fifo_0_synth_1, control_sub_m05_data_fifo_0_synth_1, control_sub_m04_data_fifo_0_synth_1, control_sub_m03_data_fifo_0_synth_1, control_sub_m02_data_fifo_0_synth_1, control_sub_m01_data_fifo_0_synth_1, control_sub_m00_data_fifo_0_synth_1, control_sub_s00_data_fifo_0_synth_1, control_sub_auto_cc_0_synth_1...
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Run output will be captured here:
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control_sub_m07_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m07_data_fifo_0_synth_1/runme.log
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control_sub_mdm_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_mdm_1_0_synth_1/runme.log
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control_sub_clk_wiz_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_clk_wiz_1_0_synth_1/runme.log
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control_sub_axi_uartlite_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_uartlite_0_0_synth_1/runme.log
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control_sub_axi_iic_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_iic_0_0_synth_1/runme.log
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control_sub_ilmb_v10_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_v10_0_synth_1/runme.log
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control_sub_lmb_bram_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_lmb_bram_0_synth_1/runme.log
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control_sub_xbar_1_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_1_synth_1/runme.log
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control_sub_pcie_reset_inv_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie_reset_inv_0_synth_1/runme.log
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control_sub_axis_dwidth_dma_tx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_tx_0_synth_1/runme.log
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control_sub_axis_dwidth_dma_rx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_rx_0_synth_1/runme.log
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control_sub_axis_fifo_10g_rx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_rx_0_synth_1/runme.log
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|||
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control_sub_axis_fifo_10g_tx_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_tx_0_synth_1/runme.log
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|||
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control_sub_nf_riffa_dma_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_nf_riffa_dma_1_0_synth_1/runme.log
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|||
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control_sub_axi_clock_converter_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_clock_converter_0_0_synth_1/runme.log
|
|||
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control_sub_pcie3_7x_1_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie3_7x_1_0_synth_1/runme.log
|
|||
|
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control_sub_xbar_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_0_synth_1/runme.log
|
|||
|
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control_sub_microblaze_0_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_0_synth_1/runme.log
|
|||
|
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control_sub_microblaze_0_axi_intc_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_axi_intc_0_synth_1/runme.log
|
|||
|
|
control_sub_microblaze_0_xlconcat_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_xlconcat_0_synth_1/runme.log
|
|||
|
|
control_sub_rst_clk_wiz_1_100M_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_rst_clk_wiz_1_100M_0_synth_1/runme.log
|
|||
|
|
control_sub_dlmb_bram_if_cntlr_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_bram_if_cntlr_0_synth_1/runme.log
|
|||
|
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control_sub_dlmb_v10_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_v10_0_synth_1/runme.log
|
|||
|
|
control_sub_ilmb_bram_if_cntlr_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_bram_if_cntlr_0_synth_1/runme.log
|
|||
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control_sub_m08_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m08_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_m06_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m06_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_m05_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m05_data_fifo_0_synth_1/runme.log
|
|||
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control_sub_m04_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m04_data_fifo_0_synth_1/runme.log
|
|||
|
|
control_sub_m03_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m03_data_fifo_0_synth_1/runme.log
|
|||
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|
control_sub_m02_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log
|
|||
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control_sub_m01_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m01_data_fifo_0_synth_1/runme.log
|
|||
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|
control_sub_m00_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m00_data_fifo_0_synth_1/runme.log
|
|||
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control_sub_s00_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_s00_data_fifo_0_synth_1/runme.log
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control_sub_auto_cc_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_auto_cc_0_synth_1/runme.log
|
|||
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[Sun Jul 28 17:03:49 2019] Launched synth...
|
|||
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Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log
|
|||
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launch_runs: Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2872.812 ; gain = 832.703 ; free physical = 12515 ; free virtual = 15254
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# wait_on_run synth
|
|||
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|
[Sun Jul 28 17:03:49 2019] Waiting for synth to finish...
|
|||
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|
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*** Running vivado
|
|||
|
|
with args -log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl
|
|||
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|
|||
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|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
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|
|||
|
|
source top.tcl -notrace
|
|||
|
|
Command: synth_design -top top -part xc7vx690tffg1761-3
|
|||
|
|
Starting synth_design
|
|||
|
|
WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
|
|||
|
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/identifier_ip.xci
|
|||
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|
|||
|
|
Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx690t'
|
|||
|
|
INFO: Launching helper process for spawning children vivado processes
|
|||
|
|
INFO: Helper process launched with PID 9968
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_single [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153]
|
|||
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|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_gray [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_handshake [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:469]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_pulse [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:715]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_array_single [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_sync_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_cdc_async_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1171]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_base [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_rst [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_counter_updn [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_reg_vec [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_reg_bit [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_reg_pipe_bit [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1774]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_sync [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_async [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_fifo_axis [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2076]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_base [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module asym_bwe_bb [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6541]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_dpdistram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6600]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_dprom [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6734]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_sdpram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:6888]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_spram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7043]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_sprom [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7189]
|
|||
|
|
WARNING: [Synth 8-2490] overwriting previous definition of module xpm_memory_tdpram [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325]
|
|||
|
|
WARNING: [Synth 8-2507] parameter declaration becomes local in small_fifo with formal parameter declaration list [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:67]
|
|||
|
|
WARNING: [Synth 8-2507] parameter declaration becomes local in sss_small_fifo with formal parameter declaration list [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_small_fifo.v:69]
|
|||
|
|
WARNING: [Synth 8-2306] macro REG_ID_DEFAULT redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues_cpu_regs_defines.v:44]
|
|||
|
|
WARNING: [Synth 8-2306] macro REG_ID_DEFAULT redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:44]
|
|||
|
|
WARNING: [Synth 8-2306] macro REG_PKTIN_ADDR redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:75]
|
|||
|
|
WARNING: [Synth 8-2306] macro REG_PKTOUT_ADDR redefined [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs_defines.v:80]
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Starting RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:23 . Memory (MB): peak = 1453.863 ; gain = 129.371 ; free physical = 11890 ; free virtual = 14791
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'top' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:43]
|
|||
|
|
Parameter C_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter IF_SFP0 bound to: 8'b00000001
|
|||
|
|
Parameter IF_SFP1 bound to: 8'b00000100
|
|||
|
|
Parameter IF_SFP2 bound to: 8'b00010000
|
|||
|
|
Parameter IF_SFP3 bound to: 8'b01000000
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:152]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:153]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:154]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:155]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:156]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:157]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:166]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:167]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:168]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:169]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:170]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:171]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:180]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:181]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:182]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:183]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:184]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:185]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:194]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:195]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:196]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:197]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:198]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:199]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:259]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:260]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:261]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:262]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:263]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:264]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:265]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:266]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:267]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:268]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:269]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:270]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:271]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:272]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:273]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:274]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:275]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:276]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:277]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:431]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'OBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:27275]
|
|||
|
|
Parameter CAPACITANCE bound to: DONT_CARE - type: string
|
|||
|
|
Parameter DRIVE bound to: 12 - type: integer
|
|||
|
|
Parameter IOSTANDARD bound to: DEFAULT - type: string
|
|||
|
|
Parameter SLEW bound to: SLOW - type: string
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'OBUF' (1#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:27275]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19473]
|
|||
|
|
Parameter CAPACITANCE bound to: DONT_CARE - type: string
|
|||
|
|
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
|
|||
|
|
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
|
|||
|
|
Parameter IOSTANDARD bound to: DEFAULT - type: string
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19473]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'IBUFDS_GTE2' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19625]
|
|||
|
|
Parameter CLKCM_CFG bound to: TRUE - type: string
|
|||
|
|
Parameter CLKRCV_TRST bound to: TRUE - type: string
|
|||
|
|
Parameter CLKSWING_CFG bound to: 2'b11
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'IBUFDS_GTE2' (3#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19625]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:22660]
|
|||
|
|
Parameter DRIVE bound to: 12 - type: integer
|
|||
|
|
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
|
|||
|
|
Parameter IOSTANDARD bound to: DEFAULT - type: string
|
|||
|
|
Parameter SLEW bound to: SLOW - type: string
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (4#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:22660]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'axi_clocking' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/axi_clocking.v:44]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488]
|
|||
|
|
Parameter CAPACITANCE bound to: DONT_CARE - type: string
|
|||
|
|
Parameter DIFF_TERM bound to: FALSE - type: string
|
|||
|
|
Parameter DQS_BIAS bound to: FALSE - type: string
|
|||
|
|
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
|
|||
|
|
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
|
|||
|
|
Parameter IOSTANDARD bound to: DEFAULT - type: string
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (5#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'clk_wiz_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.v:70]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'clk_wiz_ip_clk_wiz' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:68]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:126]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:126]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762]
|
|||
|
|
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
|
|||
|
|
Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: float
|
|||
|
|
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float
|
|||
|
|
Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT0_DIVIDE_F bound to: 5.000000 - type: float
|
|||
|
|
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float
|
|||
|
|
Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float
|
|||
|
|
Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string
|
|||
|
|
Parameter COMPENSATION bound to: ZHOLD - type: string
|
|||
|
|
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
|
|||
|
|
Parameter IS_CLKINSEL_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_PSEN_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_PSINCDEC_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_PWRDWN_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_RST_INVERTED bound to: 1'b0
|
|||
|
|
Parameter REF_JITTER1 bound to: 0.010000 - type: float
|
|||
|
|
Parameter REF_JITTER2 bound to: 0.010000 - type: float
|
|||
|
|
Parameter SS_EN bound to: FALSE - type: string
|
|||
|
|
Parameter SS_MODE bound to: CENTER_HIGH - type: string
|
|||
|
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Parameter SS_MOD_PERIOD bound to: 10000 - type: integer
|
|||
|
|
Parameter STARTUP_WAIT bound to: FALSE - type: string
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (6#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762]
|
|||
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|
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (7#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'BUFGCE' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:619]
|
|||
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|
Parameter CE_TYPE bound to: SYNC - type: string
|
|||
|
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Parameter IS_CE_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_I_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'BUFGCE' (8#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:619]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'BUFH' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:808]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'BUFH' (9#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:808]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_ip_clk_wiz' (10#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_clk_wiz.v:68]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_ip' (11#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.v:70]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'axi_clocking' (12#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/axi_clocking.v:44]
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:74]
|
|||
|
|
Parameter C_FAMILY bound to: virtex7 - type: string
|
|||
|
|
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_EXT_RESET_HIGH bound to: 1'b0
|
|||
|
|
Parameter C_AUX_RESET_HIGH bound to: 1'b0
|
|||
|
|
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
|
|||
|
|
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:129]
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
|
|||
|
|
Parameter C_FAMILY bound to: virtex7 - type: string
|
|||
|
|
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_EXT_RESET_HIGH bound to: 1'b0
|
|||
|
|
Parameter C_AUX_RESET_HIGH bound to: 1'b0
|
|||
|
|
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
|
|||
|
|
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
|
|||
|
|
Parameter INIT bound to: 1'b1
|
|||
|
|
Parameter IS_C_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_D_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_R_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1392]
|
|||
|
|
Parameter INIT bound to: 1'b1
|
|||
|
|
Parameter IS_C_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_D_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_R_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1408]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
Parameter IS_C_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_D_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_R_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1434]
|
|||
|
|
Parameter INIT bound to: 1'b1
|
|||
|
|
Parameter IS_C_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_D_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_R_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1457]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
Parameter IS_C_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_D_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_R_INVERTED bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1481]
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'lpf' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
|
|||
|
|
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_EXT_RESET_HIGH bound to: 1'b0
|
|||
|
|
Parameter C_AUX_RESET_HIGH bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-3491] module 'SRL16' declared at '/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:868]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'SRL16' [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695]
|
|||
|
|
Parameter INIT bound to: 16'b0000000000000000
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (13#1) [/opt/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:50695]
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:106]
|
|||
|
|
Parameter C_CDC_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter C_RESET_STATE bound to: 0 - type: integer
|
|||
|
|
Parameter C_SINGLE_BIT bound to: 1 - type: integer
|
|||
|
|
Parameter C_FLOP_INPUT bound to: 0 - type: integer
|
|||
|
|
Parameter C_VECTOR_WIDTH bound to: 2 - type: integer
|
|||
|
|
Parameter C_MTBF_STAGES bound to: 4 - type: integer
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:514]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:545]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:554]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:564]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:574]
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:584]
|
|||
|
|
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (14#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/lib_cdc_v1_0_rfs.vhd:106]
|
|||
|
|
INFO: [Synth 8-256] done synthesizing module 'lpf' (15#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
|
|||
|
|
Parameter C_SIZE bound to: 6 - type: integer
|
|||
|
|
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (16#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
|
|||
|
|
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (17#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
|
|||
|
|
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (18#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
|
|||
|
|
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset_ip' (19#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/synth/proc_sys_reset_ip.vhd:74]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'nf_datapath' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:44]
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
Parameter C_BASEADDR bound to: 0 - type: integer
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter NUM_QUEUES bound to: 5 - type: integer
|
|||
|
|
Parameter DIGEST_WIDTH bound to: 80 - type: integer
|
|||
|
|
Parameter C_AXIS_TUSER_DIGEST_WIDTH bound to: 304 - type: integer
|
|||
|
|
Parameter Q_SIZE_WIDTH bound to: 16 - type: integer
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:194]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:195]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:196]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:197]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:198]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:199]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:201]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:202]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:203]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:204]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:205]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:206]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:209]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:210]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:211]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:212]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:213]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:321]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:322]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'input_arbiter_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/synth/input_arbiter_ip.v:57]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'input_arbiter' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:55]
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter NUM_QUEUES bound to: 5 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
Parameter C_BASEADDR bound to: 0 - type: integer
|
|||
|
|
Parameter NUM_QUEUES_WIDTH bound to: 3 - type: integer
|
|||
|
|
Parameter NUM_STATES bound to: 1 - type: integer
|
|||
|
|
Parameter IDLE bound to: 0 - type: integer
|
|||
|
|
Parameter WR_PKT bound to: 1 - type: integer
|
|||
|
|
Parameter MAX_PKT_SIZE bound to: 2000 - type: integer
|
|||
|
|
Parameter IN_FIFO_DEPTH_BIT bound to: 6 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'fallthrough_small_fifo' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/fallthrough_small_fifo.v:46]
|
|||
|
|
Parameter WIDTH bound to: 417 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 6 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'small_fifo' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:44]
|
|||
|
|
Parameter WIDTH bound to: 417 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 6 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 64 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'small_fifo' (20#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:44]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'fallthrough_small_fifo' (21#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/fallthrough_small_fifo.v:46]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'input_arbiter_cpu_regs' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:42]
|
|||
|
|
Parameter C_BASE_ADDRESS bound to: 0 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:305]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'input_arbiter_cpu_regs' (22#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter_cpu_regs.v:42]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'input_arbiter' (23#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:55]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'input_arbiter_ip' (24#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/synth/input_arbiter_ip.v:57]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'nf_sume_sdnet_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/synth/nf_sume_sdnet_ip.v:57]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'nf_sume_sdnet' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:44]
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 304 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
Parameter SDNET_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
Parameter DIGEST_WIDTH bound to: 256 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'sume_to_sdnet' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:41]
|
|||
|
|
Parameter FIRST bound to: 0 - type: integer
|
|||
|
|
Parameter WAIT bound to: 1 - type: integer
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:72]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'sume_to_sdnet' (25#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/sume_to_sdnet.v:41]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_line' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v:40]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_line' (26#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_lookup' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v:40]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_lookup' (27#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_RESETTER_control' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v:40]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_RESETTER_control' (28#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'TopParser_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v:282]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'TopParser_t' (182#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v:282]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'TopPipe_lvl_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v:172]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'TopPipe_lvl_t' (189#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v:172]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'realmain_v4_networks_0_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/realmain_v4_networks_0_t.v:36]
|
|||
|
|
Parameter K bound to: 32 - type: integer
|
|||
|
|
Parameter V bound to: 99 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_tdpram' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:467]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (191#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_tdpram' (192#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:7325]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
|
|||
|
|
Warning: Trying to implement RAM in registers. Block RAM or DRAM implementation is not possible for one or more of the following reasons :
|
|||
|
|
1: Invalid write to RAM.
|
|||
|
|
2: Unable to determine number of words or word size in RAM.
|
|||
|
|
3: No valid read/write found for RAM.
|
|||
|
|
RAM dissolved into registers
|
|||
|
|
WARNING: [Synth 8-4767] Trying to implement RAM 'CamPtrBck_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
|
|||
|
|
Reason is one or more of the following :
|
|||
|
|
1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
|
|||
|
|
2: Unable to determine number of words or word size in RAM.
|
|||
|
|
3: No valid read/write found for RAM.
|
|||
|
|
RAM "CamPtrBck_reg" dissolved into registers
|
|||
|
|
WARNING: [Synth 8-4767] Trying to implement RAM 'CamPtrFwd_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
|
|||
|
|
Reason is one or more of the following :
|
|||
|
|
1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
|
|||
|
|
2: Unable to determine number of words or word size in RAM.
|
|||
|
|
3: No valid read/write found for RAM.
|
|||
|
|
RAM "CamPtrFwd_reg" dissolved into registers
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_b.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'realmain_v4_networks_0_t' (205#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/realmain_v4_networks_0_t.HDL/realmain_v4_networks_0_t.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'TopPipe_lvl_0_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v:178]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'TopPipe_lvl_0_t' (247#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v:178]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'TopDeparser_t' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v:169]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'TopDeparser_t' (318#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v:169]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1651663213 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 128 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: std - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 3 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 48 - type: integer
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 128 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 3 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 48 - type: integer
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 8192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 128 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 8192 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 48 - type: integer
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized0' (318#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
|
|
Parameter DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter INIT_SYNC_FF bound to: 1 - type: integer
|
|||
|
|
Parameter REG_OUTPUT bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 8 - type: integer
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (319#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
Parameter REG_WIDTH bound to: 8 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (320#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
|
|
Parameter DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter INIT_SYNC_FF bound to: 1 - type: integer
|
|||
|
|
Parameter REG_OUTPUT bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 9 - type: integer
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (320#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
Parameter REG_WIDTH bound to: 9 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (320#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1638]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1663]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055]
|
|||
|
|
Parameter DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter INIT bound to: 32'sb00000000000000000000000000000000
|
|||
|
|
Parameter INIT_SYNC_FF bound to: 1 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter DEF_VAL bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1107]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (321#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1055]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (322#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755]
|
|||
|
|
Parameter RST_VALUE bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (323#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1755]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (324#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 1 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (324#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (324#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (325#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async' (326#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request' (327#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_PROTOCOL_ADAPTER_INGRESS' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:36]
|
|||
|
|
Parameter IDLE bound to: 1 - type: integer
|
|||
|
|
Parameter RX_SOF bound to: 2 - type: integer
|
|||
|
|
Parameter RX_SOF_EOF bound to: 3 - type: integer
|
|||
|
|
Parameter RX_PKT bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-4471] merging register 'tuple_out_control_VALID_reg' into 'packet_out_SOF_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:182]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element tuple_out_control_VALID_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:182]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_PROTOCOL_ADAPTER_INGRESS' (328#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_PROTOCOL_ADAPTER_EGRESS' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v:36]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_PROTOCOL_ADAPTER_EGRESS' (329#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v:36]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_TopParser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:124]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
WARNING: [Synth 8-6104] Input port 'value' has an internal driver [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:126]
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-6104' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 136192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 129 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 129 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 136192 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 266 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 266 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 266 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 266 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 266 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 266 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 266 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 266 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 266 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 266 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 266 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 266 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 266 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized1' (329#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst__parameterized0' (329#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1478]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 10 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (329#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 1 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (329#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized4' (329#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-5772' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized0' (329#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync' (330#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: FWFT - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 129 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 512 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 127 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 127 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 2 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 512 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 1 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 1 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 1 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 1 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 1 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 1 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: yes - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 5 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 1 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element gen_rd_b.gen_doutb_pipe.enb_pipe_reg[0] was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:2588]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized2' (330#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 2 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized5' (330#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1707]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized1' (330#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized0' (330#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized0' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 32768 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 66 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 66 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 32768 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 128 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 128 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 128 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 128 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 128 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 128 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 128 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 128 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 128 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 128 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 128 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 128 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 128 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized3' (330#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized2' (330#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized0' (330#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 5120 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 5120 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 20 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 20 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 20 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 20 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 20 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 20 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 20 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 20 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 20 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 20 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 20 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 20 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: yes - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 20 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized4' (330#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized3' (330#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized1' (330#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element hbrzn5sm3y1iqh2rr6a6_110_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:353]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element fy9v76xz77oxlpo98qmexs9fki_560_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:341]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element zb217fqpsc5ng5d6exwfpawf5kico2_573_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:355]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element c003l2eygw8vznjuw61krj9ms5_803_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:292]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_SYNCER_for_TopParser' (331#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 136192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 135 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 135 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized4' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized1' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: FWFT - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 512 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 133 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 133 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 2 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized5' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized2' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized2' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 359168 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 359168 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 1403 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 1403 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 1403 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 1403 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 1403 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 1403 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 1403 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 1403 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 1403 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 1403 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 1403 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 1403 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 1403 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized5' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized6' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized2' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 40960 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 40960 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 160 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 160 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 160 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 160 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 160 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 160 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 160 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 160 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 160 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 160 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 160 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 160 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 160 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized6' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized7' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized3' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized8' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 65536 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 65536 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 256 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 256 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 256 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 256 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 256 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 256 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 256 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 256 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 256 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 256 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 256 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 256 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized7' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized8' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized4' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized5' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized9' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 32768 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized9' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized5' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized6' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized10' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 65 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 8192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 65 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized8' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 8192 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: yes - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized8' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized10' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized6' (331#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element ij20kj3hmkl9fwqztizrj17e5h9lc8w_18_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:557]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element ijzi4y78n8e9s8grwvac_302_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:545]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element o4i1clvo1fm1752hi7i56kh_593_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:559]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element vndj4bflbin6rr0rxdpiw5g6vp_365_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:452]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser' (332#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'S_SYNCER_for_S_SYNCER_for_TopDeparser' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:40]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized3' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized11' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 136192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 167 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 167 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized11' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized3' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized4' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: FWFT - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized12' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 167 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 512 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 165 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 165 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 2 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized12' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_sync__parameterized4' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1800]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized7' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized13' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 65536 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized13' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized7' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized8' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized14' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 4096 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized9' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 4096 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 16 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 16 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 16 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 16 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 16 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 16 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 8 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 16 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 16 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 16 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 16 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 16 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 16 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: yes - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 16 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized9' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized14' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized8' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized9' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized15' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1403 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 359168 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized15' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized9' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized10' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 32768 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized16' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized10' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 160 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 81 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 40960 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 81 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized17' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized11' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1937]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 100 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 33 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 100 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 33 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 100 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 33 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 100 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 33 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 128 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 12800 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 33 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 33 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 125 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 125 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 8 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 8 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 12800 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 100 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 100 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 100 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 7 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 100 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 100 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 100 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 7 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 100 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 100 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 100 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 100 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 128 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 100 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 100 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 7 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 7 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 7 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 7 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 100 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized10' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
|
|||
|
|
Parameter DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter INIT_SYNC_FF bound to: 1 - type: integer
|
|||
|
|
Parameter REG_OUTPUT bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 7 - type: integer
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized1' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
|||
|
|
Parameter REG_WIDTH bound to: 7 - type: integer
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized1' (332#1) [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1733]
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 1 - type: integer
|
|||
|
|
Parameter COUNTER_WIDTH bound to: 7 - type: integer
|
|||
|
|
Parameter RESET_VALUE bound to: 2 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 5120 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 84 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 84 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 84 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 8192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 84 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 84 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element cvd3vxmp9vcajtody811p7waekpy7r_542_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:659]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element okhj43wkyvm6aw7rvumt7b0s8xnh_292_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:647]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element mw4b21v57gn0qdn1mb6so0qr9_616_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:661]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element tjv7pi7a44sf4pj702efupr_850_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:532]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 266 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 136192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 143 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 143 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: FWFT - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 143 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 1 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 512 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 141 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 141 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 507 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 2 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1161]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1207]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1218]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1266]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 20 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 5120 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 72 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 72 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: lutram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 72 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 8192 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 72 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 72 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element eq6rttbutlprd1jmkj2tlf45vx_145_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:557]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element cq3uo963m0o6deu1rmzsg4vwpkk_19_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:545]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element nov4rvx2zxkydmnn6zu_454_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:559]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element vl1gxnef3p66f47bkq2ykt41x155_761_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:452]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 290 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 290 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 1 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 290 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 290 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 135 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 512 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 148480 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 9 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 135 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 135 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 509 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
Parameter MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_SIZE bound to: 148480 - type: integer
|
|||
|
|
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
|
|||
|
|
Parameter CLOCKING_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter MEMORY_INIT_FILE bound to: none - type: string
|
|||
|
|
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
|
|||
|
|
Parameter USE_MEM_INIT bound to: 1 - type: integer
|
|||
|
|
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_A bound to: 290 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_A bound to: 290 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_A bound to: 290 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_A bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_MODE_A bound to: 2 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH_B bound to: 290 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH_B bound to: 290 - type: integer
|
|||
|
|
Parameter BYTE_WRITE_WIDTH_B bound to: 290 - type: integer
|
|||
|
|
Parameter ADDR_WIDTH_B bound to: 9 - type: integer
|
|||
|
|
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
|
|||
|
|
Parameter READ_LATENCY_B bound to: 1 - type: integer
|
|||
|
|
Parameter WRITE_MODE_B bound to: 2 - type: integer
|
|||
|
|
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_A bound to: 290 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_B bound to: 290 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA bound to: 290 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_ECC bound to: 290 - type: integer
|
|||
|
|
Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter P_MEMORY_OPT bound to: yes - type: string
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_A bound to: 290 - type: integer
|
|||
|
|
Parameter P_WIDTH_COL_WRITE_B bound to: 290 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
|
|||
|
|
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
|
|||
|
|
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
|
|||
|
|
Parameter P_SDP_WRITE_MODE bound to: no - type: string
|
|||
|
|
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 290 - type: integer
|
|||
|
|
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
|
|||
|
|
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:469]
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: bram - type: string
|
|||
|
|
Parameter ECC_MODE bound to: no_ecc - type: string
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: STD - type: string
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter P_ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
|
|||
|
|
Parameter COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter RELATED_CLOCKS bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter ECC_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter WRITE_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter USE_ADV_FEATURES bound to: 0707 - type: string
|
|||
|
|
Parameter READ_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter READ_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_EMPTY_THRESH bound to: 66 - type: integer
|
|||
|
|
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
|
|||
|
|
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
|
|||
|
|
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
|
|||
|
|
Parameter WAKEUP_TIME bound to: 0 - type: integer
|
|||
|
|
Parameter VERSION bound to: 0 - type: integer
|
|||
|
|
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter RD_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter ENABLE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter FIFO_READ_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter FIFO_SIZE bound to: 65536 - type: integer
|
|||
|
|
Parameter WR_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter RD_PNTR_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter FULL_RST_VAL bound to: 1'b0
|
|||
|
|
Parameter WR_RD_RATIO bound to: 0 - type: integer
|
|||
|
|
Parameter PF_THRESH_ADJ bound to: 66 - type: integer
|
|||
|
|
Parameter PE_THRESH_ADJ bound to: 66 - type: integer
|
|||
|
|
Parameter PF_THRESH_MIN bound to: 5 - type: integer
|
|||
|
|
Parameter PF_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter PE_THRESH_MIN bound to: 3 - type: integer
|
|||
|
|
Parameter PE_THRESH_MAX bound to: 253 - type: integer
|
|||
|
|
Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer
|
|||
|
|
Parameter RD_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111
|
|||
|
|
Parameter EN_OF bound to: 1'b1
|
|||
|
|
Parameter EN_PF bound to: 1'b1
|
|||
|
|
Parameter EN_WDC bound to: 1'b1
|
|||
|
|
Parameter EN_AF bound to: 1'b0
|
|||
|
|
Parameter EN_WACK bound to: 1'b0
|
|||
|
|
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
|
|||
|
|
Parameter EN_UF bound to: 1'b1
|
|||
|
|
Parameter EN_PE bound to: 1'b1
|
|||
|
|
Parameter EN_RDC bound to: 1'b1
|
|||
|
|
Parameter EN_AE bound to: 1'b0
|
|||
|
|
Parameter EN_DVLD bound to: 1'b0
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element zhmxuvbb52aen2zs_473_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:302]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element cevb6eny3o0w29i1ttq4_609_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:300]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element tlw7t8bbuiwhyjzbd_249_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:337]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'control_S_AXI_AWADDR' does not match port width (8) of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:189]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'control_S_AXI_ARADDR' does not match port width (8) of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:199]
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 304 - type: integer
|
|||
|
|
Parameter NUM_QUEUES bound to: 5 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
Parameter C_BASEADDR bound to: 0 - type: integer
|
|||
|
|
Parameter QUEUE_DEPTH_BITS bound to: 16 - type: integer
|
|||
|
|
Parameter NUM_QUEUES_WIDTH bound to: 3 - type: integer
|
|||
|
|
Parameter DMA_QUEUE bound to: 4 - type: integer
|
|||
|
|
Parameter BUFFER_SIZE bound to: 131072 - type: integer
|
|||
|
|
Parameter BUFFER_SIZE_WIDTH bound to: 12 - type: integer
|
|||
|
|
Parameter MAX_PACKET_SIZE bound to: 1600 - type: integer
|
|||
|
|
Parameter BUFFER_THRESHOLD bound to: 4046 - type: integer
|
|||
|
|
Parameter NUM_STATES bound to: 3 - type: integer
|
|||
|
|
Parameter IDLE bound to: 0 - type: integer
|
|||
|
|
Parameter WR_PKT bound to: 1 - type: integer
|
|||
|
|
Parameter DROP bound to: 2 - type: integer
|
|||
|
|
Parameter NUM_METADATA_STATES bound to: 2 - type: integer
|
|||
|
|
Parameter WAIT_HEADER bound to: 0 - type: integer
|
|||
|
|
Parameter WAIT_EOP bound to: 1 - type: integer
|
|||
|
|
Parameter MIN_PACKET_SIZE bound to: 64 - type: integer
|
|||
|
|
Parameter META_BUFFER_WIDTH bound to: 11 - type: integer
|
|||
|
|
Parameter DIGEST_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter DST_POS bound to: 24 - type: integer
|
|||
|
|
Parameter SEND_DIG_POS bound to: 40 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 289 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 12 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 4046 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 289 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 12 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 4046 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 4096 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 11 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 2047 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 11 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 2047 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 2048 - type: integer
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420]
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420]
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420]
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420]
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:420]
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:489]
|
|||
|
|
Parameter C_BASE_ADDRESS bound to: 0 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues_cpu_regs.v:414]
|
|||
|
|
WARNING: [Synth 8-689] width (16) of port connection 'nf0_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:372]
|
|||
|
|
WARNING: [Synth 8-689] width (16) of port connection 'nf1_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:373]
|
|||
|
|
WARNING: [Synth 8-689] width (16) of port connection 'nf2_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:374]
|
|||
|
|
WARNING: [Synth 8-689] width (16) of port connection 'nf3_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:375]
|
|||
|
|
WARNING: [Synth 8-689] width (16) of port connection 'dma_q_size' does not match port width (17) of module 'sss_output_queues_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:376]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_sume_sdnet_wrapper_1'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:282]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'bram_output_queues_1'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:332]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_arbiter_v1_0'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:217]
|
|||
|
|
WARNING: [Synth 8-350] instance 'axi_clock_converter_0' of module 'control_sub_axi_clock_converter_0_0' requires 42 connections, but only 40 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:3986]
|
|||
|
|
WARNING: [Synth 8-350] instance 'axis_fifo_10g_rx' of module 'control_sub_axis_fifo_10g_rx_0' requires 19 connections, but only 16 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4270]
|
|||
|
|
WARNING: [Synth 8-350] instance 'axis_fifo_10g_tx' of module 'control_sub_axis_fifo_10g_tx_0' requires 19 connections, but only 16 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4287]
|
|||
|
|
WARNING: [Synth 8-350] instance 'nf_riffa_dma_1' of module 'control_sub_nf_riffa_dma_1_0' requires 133 connections, but only 132 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4304]
|
|||
|
|
WARNING: [Synth 8-350] instance 'pcie3_7x_1' of module 'control_sub_pcie3_7x_1_0' requires 90 connections, but only 88 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:4437]
|
|||
|
|
WARNING: [Synth 8-350] instance 'xbar' of module 'control_sub_xbar_1' requires 40 connections, but only 38 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:3020]
|
|||
|
|
WARNING: [Synth 8-350] instance 'dlmb_v10' of module 'control_sub_dlmb_v10_0' requires 25 connections, but only 24 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7409]
|
|||
|
|
WARNING: [Synth 8-350] instance 'ilmb_v10' of module 'control_sub_ilmb_v10_0' requires 25 connections, but only 24 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7455]
|
|||
|
|
WARNING: [Synth 8-350] instance 'lmb_bram' of module 'control_sub_lmb_bram_0' requires 16 connections, but only 14 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7480]
|
|||
|
|
WARNING: [Synth 8-350] instance 'rst_clk_wiz_1_100M' of module 'control_sub_rst_clk_wiz_1_100M_0' requires 10 connections, but only 9 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/synth/control_sub.v:7251]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M00_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:698]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M00_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:702]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M01_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:718]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M01_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:722]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M02_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:738]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M02_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:742]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M03_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:758]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M03_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:762]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M04_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:778]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M04_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:782]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M05_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:798]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M05_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:802]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M06_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:818]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M06_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:822]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M07_AXI_araddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:838]
|
|||
|
|
WARNING: [Synth 8-689] width (12) of port connection 'M07_AXI_awaddr' does not match port width (31) of module 'control_sub' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:842]
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_BASE_ADDRESS bound to: 0 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
Parameter tuser_bits_per_byte bound to: 16 - type: integer
|
|||
|
|
Parameter interface_byte_width bound to: 32 - type: integer
|
|||
|
|
Parameter tuser_width_intern bound to: 512 - type: integer
|
|||
|
|
Parameter tuser_width_remain bound to: 384 - type: integer
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_AXIS_DATA_INTERNAL_WIDTH bound to: 64 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:102]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:103]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:104]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:105]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:106]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:107]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:109]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:110]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:111]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:112]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:113]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:116]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:117]
|
|||
|
|
Parameter CONST_VAL bound to: 1 - type: integer
|
|||
|
|
Parameter CONST_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter CONST_VAL bound to: 5 - type: integer
|
|||
|
|
Parameter CONST_WIDTH bound to: 3 - type: integer
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:70]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:72]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:74]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:76]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:79]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:81]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:88]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:90]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:92]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:94]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* KEEP = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0_block.v:96]
|
|||
|
|
Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string
|
|||
|
|
Parameter QPLL_FBDIV_TOP bound to: 66 - type: integer
|
|||
|
|
Parameter QPLL_FBDIV_IN bound to: 10'b0101000000
|
|||
|
|
Parameter QPLL_FBDIV_RATIO bound to: 1'b0
|
|||
|
|
Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000
|
|||
|
|
Parameter COMMON_CFG bound to: 92 - type: integer
|
|||
|
|
Parameter IS_DRPCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter QPLL_CFG bound to: 27'b000010010000000000111000111
|
|||
|
|
Parameter QPLL_CLKOUT_CFG bound to: 4'b1111
|
|||
|
|
Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000
|
|||
|
|
Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0
|
|||
|
|
Parameter QPLL_CP bound to: 10'b0000011111
|
|||
|
|
Parameter QPLL_CP_MONITOR_EN bound to: 1'b0
|
|||
|
|
Parameter QPLL_DMONITOR_SEL bound to: 1'b0
|
|||
|
|
Parameter QPLL_FBDIV bound to: 10'b0101000000
|
|||
|
|
Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0
|
|||
|
|
Parameter QPLL_FBDIV_RATIO bound to: 1'b0
|
|||
|
|
Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110
|
|||
|
|
Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000
|
|||
|
|
Parameter QPLL_LPF bound to: 4'b1111
|
|||
|
|
Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer
|
|||
|
|
Parameter QPLL_RP_COMP bound to: 1'b0
|
|||
|
|
Parameter QPLL_VTRL_RESET bound to: 2'b00
|
|||
|
|
Parameter RCAL_CFG bound to: 2'b00
|
|||
|
|
Parameter RSVD_ATTR0 bound to: 16'b0000000000000000
|
|||
|
|
Parameter RSVD_ATTR1 bound to: 16'b0000000000000000
|
|||
|
|
Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001
|
|||
|
|
Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string
|
|||
|
|
Parameter SIM_VERSION bound to: 2.0 - type: string
|
|||
|
|
Parameter CAPACITANCE bound to: DONT_CARE - type: string
|
|||
|
|
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
|
|||
|
|
Parameter IBUF_LOW_PWR bound to: FALSE - type: string
|
|||
|
|
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
|
|||
|
|
Parameter IOSTANDARD bound to: DEFAULT - type: string
|
|||
|
|
Parameter CLKCM_CFG bound to: TRUE - type: string
|
|||
|
|
Parameter CLKRCV_TRST bound to: TRUE - type: string
|
|||
|
|
Parameter CLKSWING_CFG bound to: 2'b11
|
|||
|
|
Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer
|
|||
|
|
Parameter C_RVAL bound to: 1'b1
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer_rst.v:72]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer_rst.v:72]
|
|||
|
|
Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer
|
|||
|
|
Parameter C_RVAL bound to: 1'b0
|
|||
|
|
Parameter MASTER_WATCHDOG_TIMER_RESET bound to: 29'b00110111111000010010110100000
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "yes" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_block.v:202]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "yes" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_block.v:204]
|
|||
|
|
Parameter RXRESETTIME_NOM bound to: 24'b000000000000011000011011
|
|||
|
|
Parameter RXRESETTIME_MAX bound to: 24'b000100011010010010100110
|
|||
|
|
Parameter SYNTH_VALUE bound to: 24'b000100011010010010100110
|
|||
|
|
Parameter SIM_VALUE bound to: 24'b000000000000011000011011
|
|||
|
|
Parameter INIT bound to: 2'b10
|
|||
|
|
Parameter INIT bound to: 1'b0
|
|||
|
|
Parameter IS_CLR_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_G_INVERTED bound to: 1'b0
|
|||
|
|
Parameter C_NUM_SYNC_REGS bound to: 7 - type: integer
|
|||
|
|
Parameter C_RVAL bound to: 1'b1
|
|||
|
|
Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer.v:68]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_ff_synchronizer.v:68]
|
|||
|
|
Parameter CABLE_PULL_WATCHDOG_RESET bound to: 20'b00100000000000000000
|
|||
|
|
Parameter CABLE_UNPULL_WATCHDOG_RESET bound to: 20'b00100000000000000000
|
|||
|
|
Parameter GEARBOXSLIP_IGNORE_COUNT bound to: 4'b1111
|
|||
|
|
Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer
|
|||
|
|
Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string
|
|||
|
|
Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string
|
|||
|
|
Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer
|
|||
|
|
Parameter TXSYNC_OVRD_IN bound to: 1'b0
|
|||
|
|
Parameter TXSYNC_MULTILANE_IN bound to: 1'b0
|
|||
|
|
Parameter ACJTAG_DEBUG_MODE bound to: 1'b0
|
|||
|
|
Parameter ACJTAG_MODE bound to: 1'b0
|
|||
|
|
Parameter ACJTAG_RESET bound to: 1'b0
|
|||
|
|
Parameter ADAPT_CFG0 bound to: 20'b00000000110000010000
|
|||
|
|
Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string
|
|||
|
|
Parameter ALIGN_COMMA_ENABLE bound to: 10'b0001111111
|
|||
|
|
Parameter ALIGN_COMMA_WORD bound to: 1 - type: integer
|
|||
|
|
Parameter ALIGN_MCOMMA_DET bound to: FALSE - type: string
|
|||
|
|
Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011
|
|||
|
|
Parameter ALIGN_PCOMMA_DET bound to: FALSE - type: string
|
|||
|
|
Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100
|
|||
|
|
Parameter A_RXOSCALRESET bound to: 1'b0
|
|||
|
|
Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string
|
|||
|
|
Parameter CFOK_CFG bound to: 42'b100100100000000000000001000000111010000000
|
|||
|
|
Parameter CFOK_CFG2 bound to: 6'b100000
|
|||
|
|
Parameter CFOK_CFG3 bound to: 6'b100000
|
|||
|
|
Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string
|
|||
|
|
Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer
|
|||
|
|
Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000
|
|||
|
|
Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000
|
|||
|
|
Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000
|
|||
|
|
Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000
|
|||
|
|
Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111
|
|||
|
|
Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000
|
|||
|
|
Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000
|
|||
|
|
Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000
|
|||
|
|
Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000
|
|||
|
|
Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111
|
|||
|
|
Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string
|
|||
|
|
Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer
|
|||
|
|
Parameter CLK_CORRECT_USE bound to: FALSE - type: string
|
|||
|
|
Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string
|
|||
|
|
Parameter CLK_COR_MAX_LAT bound to: 19 - type: integer
|
|||
|
|
Parameter CLK_COR_MIN_LAT bound to: 15 - type: integer
|
|||
|
|
Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string
|
|||
|
|
Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer
|
|||
|
|
Parameter CLK_COR_SEQ_1_1 bound to: 10'b0000000000
|
|||
|
|
Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000
|
|||
|
|
Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000
|
|||
|
|
Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000
|
|||
|
|
Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111
|
|||
|
|
Parameter CLK_COR_SEQ_2_1 bound to: 10'b0000000000
|
|||
|
|
Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000
|
|||
|
|
Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000
|
|||
|
|
Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000
|
|||
|
|
Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111
|
|||
|
|
Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string
|
|||
|
|
Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer
|
|||
|
|
Parameter CPLL_CFG bound to: 29'b00000101111000000011111011100
|
|||
|
|
Parameter CPLL_FBDIV bound to: 4 - type: integer
|
|||
|
|
Parameter CPLL_FBDIV_45 bound to: 5 - type: integer
|
|||
|
|
Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110
|
|||
|
|
Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000
|
|||
|
|
Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer
|
|||
|
|
Parameter DEC_MCOMMA_DETECT bound to: FALSE - type: string
|
|||
|
|
Parameter DEC_PCOMMA_DETECT bound to: FALSE - type: string
|
|||
|
|
Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string
|
|||
|
|
Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000
|
|||
|
|
Parameter ES_CLK_PHASE_SEL bound to: 1'b0
|
|||
|
|
Parameter ES_CONTROL bound to: 6'b000000
|
|||
|
|
Parameter ES_ERRDET_EN bound to: FALSE - type: string
|
|||
|
|
Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string
|
|||
|
|
Parameter ES_HORZ_OFFSET bound to: 12'b000000000000
|
|||
|
|
Parameter ES_PMA_CFG bound to: 10'b0000000000
|
|||
|
|
Parameter ES_PRESCALE bound to: 5'b00000
|
|||
|
|
Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|||
|
|
Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|||
|
|
Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|||
|
|
Parameter ES_VERT_OFFSET bound to: 9'b000000000
|
|||
|
|
Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111
|
|||
|
|
Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111
|
|||
|
|
Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string
|
|||
|
|
Parameter GEARBOX_MODE bound to: 3'b001
|
|||
|
|
Parameter IS_CLKRSVD0_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_CLKRSVD1_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_CPLLLOCKDETCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_DMONITORCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_DRPCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_RXUSRCLK2_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_RXUSRCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_SIGVALIDCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_TXPHDLYTSTCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_TXUSRCLK2_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_TXUSRCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter LOOPBACK_CFG bound to: 1'b0
|
|||
|
|
Parameter OUTREFCLK_SEL_INV bound to: 2'b11
|
|||
|
|
Parameter PCS_PCIE_EN bound to: FALSE - type: string
|
|||
|
|
Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000
|
|||
|
|
Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100
|
|||
|
|
Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00011001
|
|||
|
|
Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100
|
|||
|
|
Parameter PMA_RSV bound to: 128 - type: integer
|
|||
|
|
Parameter PMA_RSV2 bound to: 469762058 - type: integer
|
|||
|
|
Parameter PMA_RSV3 bound to: 2'b00
|
|||
|
|
Parameter PMA_RSV4 bound to: 15'b000000000001000
|
|||
|
|
Parameter PMA_RSV5 bound to: 4'b0000
|
|||
|
|
Parameter RESET_POWERSAVE_DISABLE bound to: 1'b0
|
|||
|
|
Parameter RXBUFRESET_TIME bound to: 5'b00001
|
|||
|
|
Parameter RXBUF_ADDR_MODE bound to: FAST - type: string
|
|||
|
|
Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000
|
|||
|
|
Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000
|
|||
|
|
Parameter RXBUF_EN bound to: TRUE - type: string
|
|||
|
|
Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string
|
|||
|
|
Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string
|
|||
|
|
Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string
|
|||
|
|
Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string
|
|||
|
|
Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer
|
|||
|
|
Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string
|
|||
|
|
Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer
|
|||
|
|
Parameter RXCDRFREQRESET_TIME bound to: 5'b00001
|
|||
|
|
Parameter RXCDRPHRESET_TIME bound to: 5'b00001
|
|||
|
|
Parameter RXCDR_CFG bound to: 83'b00000000000001000000000011111111110001000000000000011000010000010000000000000011010
|
|||
|
|
Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0
|
|||
|
|
Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0
|
|||
|
|
Parameter RXCDR_LOCK_CFG bound to: 6'b010101
|
|||
|
|
Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0
|
|||
|
|
Parameter RXDFELPMRESET_TIME bound to: 7'b0001111
|
|||
|
|
Parameter RXDLY_CFG bound to: 16'b0000000000011111
|
|||
|
|
Parameter RXDLY_LCFG bound to: 9'b000110000
|
|||
|
|
Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000
|
|||
|
|
Parameter RXGEARBOX_EN bound to: TRUE - type: string
|
|||
|
|
Parameter RXISCANRESET_TIME bound to: 5'b00001
|
|||
|
|
Parameter RXLPM_HF_CFG bound to: 14'b00001000000000
|
|||
|
|
Parameter RXLPM_LF_CFG bound to: 18'b001001000000000000
|
|||
|
|
Parameter RXOOB_CFG bound to: 7'b0000110
|
|||
|
|
Parameter RXOOB_CLK_CFG bound to: PMA - type: string
|
|||
|
|
Parameter RXOSCALRESET_TIME bound to: 5'b00011
|
|||
|
|
Parameter RXOSCALRESET_TIMEOUT bound to: 5'b00000
|
|||
|
|
Parameter RXOUT_DIV bound to: 1 - type: integer
|
|||
|
|
Parameter RXPCSRESET_TIME bound to: 5'b00001
|
|||
|
|
Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000
|
|||
|
|
Parameter RXPH_CFG bound to: 24'b110000000000000000000010
|
|||
|
|
Parameter RXPH_MONITOR_SEL bound to: 5'b00000
|
|||
|
|
Parameter RXPI_CFG0 bound to: 2'b00
|
|||
|
|
Parameter RXPI_CFG1 bound to: 2'b11
|
|||
|
|
Parameter RXPI_CFG2 bound to: 2'b11
|
|||
|
|
Parameter RXPI_CFG3 bound to: 2'b11
|
|||
|
|
Parameter RXPI_CFG4 bound to: 1'b0
|
|||
|
|
Parameter RXPI_CFG5 bound to: 1'b0
|
|||
|
|
Parameter RXPI_CFG6 bound to: 3'b100
|
|||
|
|
Parameter RXPMARESET_TIME bound to: 5'b00011
|
|||
|
|
Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0
|
|||
|
|
Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer
|
|||
|
|
Parameter RXSLIDE_MODE bound to: OFF - type: string
|
|||
|
|
Parameter RXSYNC_MULTILANE bound to: 1'b0
|
|||
|
|
Parameter RXSYNC_OVRD bound to: 1'b0
|
|||
|
|
Parameter RXSYNC_SKIP_DA bound to: 1'b0
|
|||
|
|
Parameter RX_BIAS_CFG bound to: 24'b000011000000000000010000
|
|||
|
|
Parameter RX_BUFFER_CFG bound to: 6'b000000
|
|||
|
|
Parameter RX_CLK25_DIV bound to: 7 - type: integer
|
|||
|
|
Parameter RX_CLKMUX_PD bound to: 1'b1
|
|||
|
|
Parameter RX_CM_SEL bound to: 2'b11
|
|||
|
|
Parameter RX_CM_TRIM bound to: 4'b1010
|
|||
|
|
Parameter RX_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter RX_DDI_SEL bound to: 6'b000000
|
|||
|
|
Parameter RX_DEBUG_CFG bound to: 14'b00000000000000
|
|||
|
|
Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string
|
|||
|
|
Parameter RX_DFELPM_CFG0 bound to: 4'b0110
|
|||
|
|
Parameter RX_DFELPM_CFG1 bound to: 1'b0
|
|||
|
|
Parameter RX_DFELPM_KLKH_AGC_STUP_EN bound to: 1'b1
|
|||
|
|
Parameter RX_DFE_AGC_CFG0 bound to: 2'b00
|
|||
|
|
Parameter RX_DFE_AGC_CFG1 bound to: 3'b100
|
|||
|
|
Parameter RX_DFE_AGC_CFG2 bound to: 4'b0000
|
|||
|
|
Parameter RX_DFE_AGC_OVRDEN bound to: 1'b1
|
|||
|
|
Parameter RX_DFE_GAIN_CFG bound to: 23'b00000000010000011000000
|
|||
|
|
Parameter RX_DFE_H2_CFG bound to: 12'b000000000000
|
|||
|
|
Parameter RX_DFE_H3_CFG bound to: 12'b000001000000
|
|||
|
|
Parameter RX_DFE_H4_CFG bound to: 11'b00011100000
|
|||
|
|
Parameter RX_DFE_H5_CFG bound to: 11'b00011100000
|
|||
|
|
Parameter RX_DFE_H6_CFG bound to: 11'b00000100000
|
|||
|
|
Parameter RX_DFE_H7_CFG bound to: 11'b00000100000
|
|||
|
|
Parameter RX_DFE_KL_CFG bound to: 33'b001000001000000000000001100010000
|
|||
|
|
Parameter RX_DFE_KL_LPM_KH_CFG0 bound to: 2'b01
|
|||
|
|
Parameter RX_DFE_KL_LPM_KH_CFG1 bound to: 3'b010
|
|||
|
|
Parameter RX_DFE_KL_LPM_KH_CFG2 bound to: 4'b0010
|
|||
|
|
Parameter RX_DFE_KL_LPM_KH_OVRDEN bound to: 1'b1
|
|||
|
|
Parameter RX_DFE_KL_LPM_KL_CFG0 bound to: 2'b10
|
|||
|
|
Parameter RX_DFE_KL_LPM_KL_CFG1 bound to: 3'b010
|
|||
|
|
Parameter RX_DFE_KL_LPM_KL_CFG2 bound to: 4'b0010
|
|||
|
|
Parameter RX_DFE_KL_LPM_KL_OVRDEN bound to: 1'b1
|
|||
|
|
Parameter RX_DFE_LPM_CFG bound to: 16'b0000000010000000
|
|||
|
|
Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0
|
|||
|
|
Parameter RX_DFE_ST_CFG bound to: 54'b000000111000010000000000000000000011000000000000111111
|
|||
|
|
Parameter RX_DFE_UT_CFG bound to: 17'b00011100000000000
|
|||
|
|
Parameter RX_DFE_VP_CFG bound to: 17'b00011101010100011
|
|||
|
|
Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string
|
|||
|
|
Parameter RX_INT_DATAWIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter RX_OS_CFG bound to: 13'b0000010000000
|
|||
|
|
Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer
|
|||
|
|
Parameter RX_XCLK_SEL bound to: RXREC - type: string
|
|||
|
|
Parameter SAS_MAX_COM bound to: 64 - type: integer
|
|||
|
|
Parameter SAS_MIN_COM bound to: 36 - type: integer
|
|||
|
|
Parameter SATA_BURST_SEQ_LEN bound to: 4'b1111
|
|||
|
|
Parameter SATA_BURST_VAL bound to: 3'b100
|
|||
|
|
Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string
|
|||
|
|
Parameter SATA_EIDLE_VAL bound to: 3'b100
|
|||
|
|
Parameter SATA_MAX_BURST bound to: 8 - type: integer
|
|||
|
|
Parameter SATA_MAX_INIT bound to: 21 - type: integer
|
|||
|
|
Parameter SATA_MAX_WAKE bound to: 7 - type: integer
|
|||
|
|
Parameter SATA_MIN_BURST bound to: 4 - type: integer
|
|||
|
|
Parameter SATA_MIN_INIT bound to: 12 - type: integer
|
|||
|
|
Parameter SATA_MIN_WAKE bound to: 4 - type: integer
|
|||
|
|
Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string
|
|||
|
|
Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001
|
|||
|
|
Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string
|
|||
|
|
Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string
|
|||
|
|
Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string
|
|||
|
|
Parameter SIM_VERSION bound to: 2.0 - type: string
|
|||
|
|
Parameter TERM_RCAL_CFG bound to: 15'b100001000010000
|
|||
|
|
Parameter TERM_RCAL_OVRD bound to: 3'b000
|
|||
|
|
Parameter TRANS_TIME_RATE bound to: 8'b00001110
|
|||
|
|
Parameter TST_RSV bound to: 0 - type: integer
|
|||
|
|
Parameter TXBUF_EN bound to: TRUE - type: string
|
|||
|
|
Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string
|
|||
|
|
Parameter TXDLY_CFG bound to: 16'b0000000000011111
|
|||
|
|
Parameter TXDLY_LCFG bound to: 9'b000110000
|
|||
|
|
Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000
|
|||
|
|
Parameter TXGEARBOX_EN bound to: TRUE - type: string
|
|||
|
|
Parameter TXOOB_CFG bound to: 1'b0
|
|||
|
|
Parameter TXOUT_DIV bound to: 1 - type: integer
|
|||
|
|
Parameter TXPCSRESET_TIME bound to: 5'b00001
|
|||
|
|
Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000
|
|||
|
|
Parameter TXPH_CFG bound to: 16'b0000011110000000
|
|||
|
|
Parameter TXPH_MONITOR_SEL bound to: 5'b00000
|
|||
|
|
Parameter TXPI_CFG0 bound to: 2'b00
|
|||
|
|
Parameter TXPI_CFG1 bound to: 2'b00
|
|||
|
|
Parameter TXPI_CFG2 bound to: 2'b00
|
|||
|
|
Parameter TXPI_CFG3 bound to: 1'b0
|
|||
|
|
Parameter TXPI_CFG4 bound to: 1'b0
|
|||
|
|
Parameter TXPI_CFG5 bound to: 3'b100
|
|||
|
|
Parameter TXPI_GREY_SEL bound to: 1'b0
|
|||
|
|
Parameter TXPI_INVSTROBE_SEL bound to: 1'b0
|
|||
|
|
Parameter TXPI_PPMCLK_SEL bound to: TXUSRCLK2 - type: string
|
|||
|
|
Parameter TXPI_PPM_CFG bound to: 8'b00000000
|
|||
|
|
Parameter TXPI_SYNFREQ_PPM bound to: 3'b000
|
|||
|
|
Parameter TXPMARESET_TIME bound to: 5'b00001
|
|||
|
|
Parameter TXSYNC_MULTILANE bound to: 1'b0
|
|||
|
|
Parameter TXSYNC_OVRD bound to: 1'b0
|
|||
|
|
Parameter TXSYNC_SKIP_DA bound to: 1'b0
|
|||
|
|
Parameter TX_CLK25_DIV bound to: 7 - type: integer
|
|||
|
|
Parameter TX_CLKMUX_PD bound to: 1'b1
|
|||
|
|
Parameter TX_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter TX_DEEMPH0 bound to: 6'b000000
|
|||
|
|
Parameter TX_DEEMPH1 bound to: 6'b000000
|
|||
|
|
Parameter TX_DRIVE_MODE bound to: DIRECT - type: string
|
|||
|
|
Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110
|
|||
|
|
Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100
|
|||
|
|
Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string
|
|||
|
|
Parameter TX_MAINCURSOR_SEL bound to: 1'b0
|
|||
|
|
Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110
|
|||
|
|
Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001
|
|||
|
|
Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101
|
|||
|
|
Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010
|
|||
|
|
Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000
|
|||
|
|
Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110
|
|||
|
|
Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100
|
|||
|
|
Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010
|
|||
|
|
Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000
|
|||
|
|
Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000
|
|||
|
|
Parameter TX_QPI_STATUS_EN bound to: 1'b0
|
|||
|
|
Parameter TX_RXDETECT_CFG bound to: 14'b01100000110010
|
|||
|
|
Parameter TX_RXDETECT_PRECHARGE_TIME bound to: 17'b10101010111001100
|
|||
|
|
Parameter TX_RXDETECT_REF bound to: 3'b100
|
|||
|
|
Parameter TX_XCLK_SEL bound to: TXOUT - type: string
|
|||
|
|
Parameter UCODEER_CLR bound to: 1'b0
|
|||
|
|
Parameter USE_PCS_CLK_PHASE_SEL bound to: 1'b0
|
|||
|
|
WARNING: [Synth 8-689] width (2) of port connection 'mac_status_vector' does not match port width (3) of module 'axi_10g_ethernet_shared' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:163]
|
|||
|
|
WARNING: [Synth 8-350] instance 'axi_10g_ethernet_i' of module 'axi_10g_ethernet_shared' requires 51 connections, but only 50 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:147]
|
|||
|
|
Parameter C_OPERATION bound to: not - type: string
|
|||
|
|
Parameter C_SIZE bound to: 1 - type: integer
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_DEFAULT_VALUE_ENABLE bound to: 1 - type: integer
|
|||
|
|
Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer
|
|||
|
|
Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH_INTERNAL bound to: 64 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH_INTERNAL bound to: 64 - type: integer
|
|||
|
|
Parameter NUM_RW_REGS bound to: 1 - type: integer
|
|||
|
|
Parameter NUM_RO_REGS bound to: 17 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_USE_WSTRB bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:117]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:118]
|
|||
|
|
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:119]
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-5534' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
Parameter C_NUM_SYNC_REGS bound to: 6 - type: integer
|
|||
|
|
Parameter AXI_DATA_WIDTH bound to: 64 - type: integer
|
|||
|
|
Parameter IDLE bound to: 0 - type: integer
|
|||
|
|
Parameter WAIT_FOR_EOP bound to: 1 - type: integer
|
|||
|
|
Parameter DROP bound to: 2 - type: integer
|
|||
|
|
Parameter BUBBLE bound to: 3 - type: integer
|
|||
|
|
Parameter ERR_IDLE bound to: 0 - type: integer
|
|||
|
|
Parameter ERR_WAIT bound to: 1 - type: integer
|
|||
|
|
Parameter ERR_BUBBLE bound to: 2 - type: integer
|
|||
|
|
Parameter ALMOST_EMPTY_OFFSET bound to: 9'b000001010
|
|||
|
|
Parameter ALMOST_FULL_OFFSET bound to: 9'b100101100
|
|||
|
|
Parameter DATA_WIDTH bound to: 72 - type: integer
|
|||
|
|
Parameter DO_REG bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ECC_READ bound to: FALSE - type: string
|
|||
|
|
Parameter EN_ECC_WRITE bound to: FALSE - type: string
|
|||
|
|
Parameter EN_SYN bound to: FALSE - type: string
|
|||
|
|
Parameter FIFO_MODE bound to: FIFO36_72 - type: string
|
|||
|
|
Parameter FIRST_WORD_FALL_THROUGH bound to: TRUE - type: string
|
|||
|
|
Parameter INIT bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000
|
|||
|
|
Parameter IS_RDCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_RDEN_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_RSTREG_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_RST_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_WRCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_WREN_INVERTED bound to: 1'b0
|
|||
|
|
Parameter SIM_DEVICE bound to: 7SERIES - type: string
|
|||
|
|
Parameter SRVAL bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'fifo_generator_1_9' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/synth/fifo_generator_1_9.vhd:75]
|
|||
|
|
Parameter C_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter C_SELECT_XPM bound to: 0 - type: integer
|
|||
|
|
Parameter C_COUNT_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_DATA_COUNT_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
|
|||
|
|
Parameter C_DIN_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
|
|||
|
|
Parameter C_DOUT_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
|
|||
|
|
Parameter C_FAMILY bound to: virtex7 - type: string
|
|||
|
|
Parameter C_FULL_FLAGS_RST_VAL bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_BACKUP bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_RD_RST bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_RST bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_SRST bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_VALID bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_WR_RST bound to: 0 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
|
|||
|
|
Parameter C_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
|
|||
|
|
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
|
|||
|
|
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 15 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 14 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_RD_DATA_COUNT_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_RD_DEPTH bound to: 16 - type: integer
|
|||
|
|
Parameter C_RD_FREQ bound to: 1 - type: integer
|
|||
|
|
Parameter C_RD_PNTR_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_DOUT_RST bound to: 1 - type: integer
|
|||
|
|
Parameter C_USE_ECC bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
|
|||
|
|
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer
|
|||
|
|
Parameter C_VALID_LOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_WR_DATA_COUNT_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH bound to: 16 - type: integer
|
|||
|
|
Parameter C_WR_FREQ bound to: 1 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
|
|||
|
|
Parameter C_MSGON_VAL bound to: 1 - type: integer
|
|||
|
|
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
|
|||
|
|
Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer
|
|||
|
|
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_AXI_TYPE bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_MASTER_CE bound to: 0 - type: integer
|
|||
|
|
Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer
|
|||
|
|
Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
|
|||
|
|
Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer
|
|||
|
|
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TID bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer
|
|||
|
|
Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_WACH_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_WDCH_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_WRCH_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_RACH_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_RDCH_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_AXIS_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string
|
|||
|
|
Parameter C_USE_ECC_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_ECC_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_ECC_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_ECC_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_ECC_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_ECC_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-3491] module 'fifo_generator_v13_2_2' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/fifo_generator_v13_2_2/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38483' bound to instance 'U0' of component 'fifo_generator_v13_2_2' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/synth/fifo_generator_1_9.vhd:545]
|
|||
|
|
INFO: [Synth 8-256] done synthesizing module 'fifo_generator_1_9' (528#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/synth/fifo_generator_1_9.vhd:75]
|
|||
|
|
WARNING: [Synth 8-350] instance 'rx_info_fifo' of module 'fifo_generator_1_9' requires 11 connections, but only 9 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/rx_queue.v:148]
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/rx_queue.v:175]
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/rx_queue.v:247]
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 64 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_LEN_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter C_SPT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_DPT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_DEFAULT_VALUE_ENABLE bound to: 1 - type: integer
|
|||
|
|
Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer
|
|||
|
|
Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 64 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_LEN_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter C_SPT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_DPT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_DEFAULT_VALUE_ENABLE bound to: 1 - type: integer
|
|||
|
|
Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer
|
|||
|
|
Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_PKT_SIZE bound to: 1600 - type: integer
|
|||
|
|
Parameter LENGTH_COUNTER_WIDTH bound to: 3 - type: integer
|
|||
|
|
Parameter IN_FIFO_DEPTH_BIT bound to: 8 - type: integer
|
|||
|
|
Parameter M_S_RATIO_COUNT bound to: 4 - type: integer
|
|||
|
|
Parameter S_M_RATIO_COUNT bound to: 0 - type: integer
|
|||
|
|
Parameter METADATA_STATE_WAIT_START bound to: 0 - type: integer
|
|||
|
|
Parameter METADATA_STATE_WAIT_END bound to: 1 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 5 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 5 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 32 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 73 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 255 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 73 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 8 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 255 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WAIT_START bound to: 0 - type: integer
|
|||
|
|
Parameter RCV_WORD bound to: 1 - type: integer
|
|||
|
|
Parameter L2_IFSM_STATES bound to: 1 - type: integer
|
|||
|
|
Parameter RFSM_START bound to: 0 - type: integer
|
|||
|
|
Parameter RFSM_FINISH_PKT bound to: 1 - type: integer
|
|||
|
|
Parameter L2_RFSM_STATES bound to: 1 - type: integer
|
|||
|
|
Parameter MAX_PKT_SIZE bound to: 2048 - type: integer
|
|||
|
|
Parameter MIN_PKT_SIZE bound to: 64 - type: integer
|
|||
|
|
Parameter MAX_PKTS bound to: 32 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 8 - type: integer
|
|||
|
|
Parameter L2_MAX_DEPTH bound to: 3 - type: integer
|
|||
|
|
Parameter L2_MAX_PKTS bound to: 5 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 289 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 3 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 7 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 289 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 3 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 7 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 8 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 5 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 5 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 64 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_LEN_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter C_SPT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_DPT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_DEFAULT_VALUE_ENABLE bound to: 1'b0
|
|||
|
|
Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer
|
|||
|
|
Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 64 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_LEN_WIDTH bound to: 16 - type: integer
|
|||
|
|
Parameter C_SPT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_DPT_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_DEFAULT_VALUE_ENABLE bound to: 1'b0
|
|||
|
|
Parameter C_DEFAULT_SRC_PORT bound to: 0 - type: integer
|
|||
|
|
Parameter C_DEFAULT_DST_PORT bound to: 0 - type: integer
|
|||
|
|
Parameter MAX_PKT_SIZE bound to: 1600 - type: integer
|
|||
|
|
Parameter LENGTH_COUNTER_WIDTH bound to: 5 - type: integer
|
|||
|
|
Parameter IN_FIFO_DEPTH_BIT bound to: 6 - type: integer
|
|||
|
|
Parameter M_S_RATIO_COUNT bound to: 0 - type: integer
|
|||
|
|
Parameter S_M_RATIO_COUNT bound to: 4 - type: integer
|
|||
|
|
Parameter METADATA_STATE_WAIT_START bound to: 0 - type: integer
|
|||
|
|
Parameter METADATA_STATE_WAIT_END bound to: 1 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 289 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 6 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 289 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 6 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 63 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 64 - type: integer
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element SLAVE_WIDER.length_prev_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_axis_converter_main.v:514]
|
|||
|
|
Parameter C_AXIS_DATA_WIDTH bound to: 64 - type: integer
|
|||
|
|
Parameter C_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter WAIT_START bound to: 0 - type: integer
|
|||
|
|
Parameter RCV_WORD bound to: 1 - type: integer
|
|||
|
|
Parameter L2_IFSM_STATES bound to: 1 - type: integer
|
|||
|
|
Parameter RFSM_START bound to: 0 - type: integer
|
|||
|
|
Parameter RFSM_FINISH_PKT bound to: 1 - type: integer
|
|||
|
|
Parameter L2_RFSM_STATES bound to: 1 - type: integer
|
|||
|
|
Parameter MAX_PKT_SIZE bound to: 2048 - type: integer
|
|||
|
|
Parameter MIN_PKT_SIZE bound to: 64 - type: integer
|
|||
|
|
Parameter MAX_PKTS bound to: 32 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 32 - type: integer
|
|||
|
|
Parameter L2_MAX_DEPTH bound to: 5 - type: integer
|
|||
|
|
Parameter L2_MAX_PKTS bound to: 5 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 73 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 5 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer
|
|||
|
|
Parameter WIDTH bound to: 73 - type: integer
|
|||
|
|
Parameter MAX_DEPTH_BITS bound to: 5 - type: integer
|
|||
|
|
Parameter PROG_FULL_THRESHOLD bound to: 31 - type: integer
|
|||
|
|
Parameter MAX_DEPTH bound to: 32 - type: integer
|
|||
|
|
Parameter AXI_DATA_WIDTH bound to: 64 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter IDLE bound to: 2'b00
|
|||
|
|
Parameter SEND_PKT bound to: 2'b01
|
|||
|
|
Parameter METADATA bound to: 1'b0
|
|||
|
|
Parameter EOP bound to: 1'b1
|
|||
|
|
Parameter ALMOST_EMPTY_OFFSET bound to: 9'b000001010
|
|||
|
|
Parameter ALMOST_FULL_OFFSET bound to: 9'b100000000
|
|||
|
|
Parameter DATA_WIDTH bound to: 72 - type: integer
|
|||
|
|
Parameter DO_REG bound to: 1 - type: integer
|
|||
|
|
Parameter EN_ECC_READ bound to: FALSE - type: string
|
|||
|
|
Parameter EN_ECC_WRITE bound to: FALSE - type: string
|
|||
|
|
Parameter EN_SYN bound to: FALSE - type: string
|
|||
|
|
Parameter FIFO_MODE bound to: FIFO36_72 - type: string
|
|||
|
|
Parameter FIRST_WORD_FALL_THROUGH bound to: TRUE - type: string
|
|||
|
|
Parameter INIT bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000
|
|||
|
|
Parameter IS_RDCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_RDEN_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_RSTREG_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_RST_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_WRCLK_INVERTED bound to: 1'b0
|
|||
|
|
Parameter IS_WREN_INVERTED bound to: 1'b0
|
|||
|
|
Parameter SIM_DEVICE bound to: 7SERIES - type: string
|
|||
|
|
Parameter SRVAL bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000
|
|||
|
|
WARNING: [Synth 8-350] instance 'tx_info_fifo' of module 'fifo_generator_1_9' requires 11 connections, but only 9 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/tx_queue.v:153]
|
|||
|
|
INFO: [Synth 8-226] default block is never used [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/tx_queue.v:208]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'rx_fifo_intf'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:180]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'converter_rx'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:222]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'converter_tx'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:258]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'tx_fifo_intf'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_attachment.v:290]
|
|||
|
|
INFO: [Synth 8-638] synthesizing module 'fifo_generator_status' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/synth/fifo_generator_status.vhd:72]
|
|||
|
|
Parameter C_COMMON_CLOCK bound to: 0 - type: integer
|
|||
|
|
Parameter C_SELECT_XPM bound to: 0 - type: integer
|
|||
|
|
Parameter C_COUNT_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_DATA_COUNT_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
|
|||
|
|
Parameter C_DIN_WIDTH bound to: 458 - type: integer
|
|||
|
|
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
|
|||
|
|
Parameter C_DOUT_WIDTH bound to: 458 - type: integer
|
|||
|
|
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
|
|||
|
|
Parameter C_FAMILY bound to: virtex7 - type: string
|
|||
|
|
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_BACKUP bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
|
|||
|
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Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
|
|||
|
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Parameter C_HAS_RD_RST bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_RST bound to: 0 - type: integer
|
|||
|
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Parameter C_HAS_SRST bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_VALID bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
|
|||
|
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Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_WR_RST bound to: 0 - type: integer
|
|||
|
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Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer
|
|||
|
|
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
|
|||
|
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Parameter C_MEMORY_TYPE bound to: 1 - type: integer
|
|||
|
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Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
|
|||
|
|
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
|
|||
|
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Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
|
|||
|
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Parameter C_PRELOAD_REGS bound to: 1 - type: integer
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE bound to: 512x72 - type: string
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
|
|||
|
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Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 15 - type: integer
|
|||
|
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Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 14 - type: integer
|
|||
|
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Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
|
|||
|
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Parameter C_RD_DATA_COUNT_WIDTH bound to: 4 - type: integer
|
|||
|
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Parameter C_RD_DEPTH bound to: 16 - type: integer
|
|||
|
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Parameter C_RD_FREQ bound to: 1 - type: integer
|
|||
|
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Parameter C_RD_PNTR_WIDTH bound to: 4 - type: integer
|
|||
|
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Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
|
|||
|
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Parameter C_USE_DOUT_RST bound to: 0 - type: integer
|
|||
|
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Parameter C_USE_ECC bound to: 0 - type: integer
|
|||
|
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Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
|
|||
|
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Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
|
|||
|
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Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
|
|||
|
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Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
|
|||
|
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Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer
|
|||
|
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Parameter C_VALID_LOW bound to: 0 - type: integer
|
|||
|
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Parameter C_WR_ACK_LOW bound to: 0 - type: integer
|
|||
|
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Parameter C_WR_DATA_COUNT_WIDTH bound to: 4 - type: integer
|
|||
|
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Parameter C_WR_DEPTH bound to: 16 - type: integer
|
|||
|
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Parameter C_WR_FREQ bound to: 1 - type: integer
|
|||
|
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Parameter C_WR_PNTR_WIDTH bound to: 4 - type: integer
|
|||
|
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Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
|
|||
|
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Parameter C_MSGON_VAL bound to: 1 - type: integer
|
|||
|
|
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
|
|||
|
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Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer
|
|||
|
|
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_AXI_TYPE bound to: 1 - type: integer
|
|||
|
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Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_MASTER_CE bound to: 0 - type: integer
|
|||
|
|
Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer
|
|||
|
|
Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
|
|||
|
|
Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer
|
|||
|
|
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TID bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer
|
|||
|
|
Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer
|
|||
|
|
Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer
|
|||
|
|
Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer
|
|||
|
|
Parameter C_WACH_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_WDCH_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_WRCH_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_RACH_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_RDCH_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_AXIS_TYPE bound to: 0 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer
|
|||
|
|
Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string
|
|||
|
|
Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string
|
|||
|
|
Parameter C_USE_ECC_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_ECC_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_ECC_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_ECC_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_ECC_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_USE_ECC_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer
|
|||
|
|
Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer
|
|||
|
|
Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer
|
|||
|
|
Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer
|
|||
|
|
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer
|
|||
|
|
Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer
|
|||
|
|
INFO: [Synth 8-3491] module 'fifo_generator_v13_2_2' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/fifo_generator_v13_2_2/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38483' bound to instance 'U0' of component 'fifo_generator_v13_2_2' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/synth/fifo_generator_status.vhd:542]
|
|||
|
|
INFO: [Synth 8-256] done synthesizing module 'fifo_generator_status' (535#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/synth/fifo_generator_status.vhd:72]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'xge_attachment'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:228]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'axi_10g_ethernet_i'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_block.v:147]
|
|||
|
|
Parameter C_BASE_ADDRESS bound to: 0 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_cpu_regs.v:322]
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_BASE_ADDRESS bound to: 0 - type: integer
|
|||
|
|
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
|||
|
|
Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
|
|||
|
|
Parameter tuser_bits_per_byte bound to: 16 - type: integer
|
|||
|
|
Parameter interface_byte_width bound to: 32 - type: integer
|
|||
|
|
Parameter tuser_width_intern bound to: 512 - type: integer
|
|||
|
|
Parameter tuser_width_remain bound to: 384 - type: integer
|
|||
|
|
Parameter C_M_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_S_AXIS_DATA_WIDTH bound to: 256 - type: integer
|
|||
|
|
Parameter C_AXIS_DATA_INTERNAL_WIDTH bound to: 64 - type: integer
|
|||
|
|
Parameter C_M_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter C_S_AXIS_TUSER_WIDTH bound to: 128 - type: integer
|
|||
|
|
Parameter MASTER_WATCHDOG_TIMER_RESET bound to: 29'b00110111111000010010110100000
|
|||
|
|
Parameter RXRESETTIME_NOM bound to: 24'b000000000000011000011011
|
|||
|
|
Parameter RXRESETTIME_MAX bound to: 24'b000100011010010010100110
|
|||
|
|
Parameter SYNTH_VALUE bound to: 24'b000100011010010010100110
|
|||
|
|
Parameter SIM_VALUE bound to: 24'b000000000000011000011011
|
|||
|
|
Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer
|
|||
|
|
Parameter C_RVAL bound to: 1'b1
|
|||
|
|
Parameter C_NUM_SYNC_REGS bound to: 7 - type: integer
|
|||
|
|
Parameter C_RVAL bound to: 1'b1
|
|||
|
|
Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer
|
|||
|
|
Parameter C_NUM_SYNC_REGS bound to: 5 - type: integer
|
|||
|
|
Parameter C_RVAL bound to: 1'b0
|
|||
|
|
Parameter CABLE_PULL_WATCHDOG_RESET bound to: 20'b00100000000000000000
|
|||
|
|
Parameter CABLE_UNPULL_WATCHDOG_RESET bound to: 20'b00100000000000000000
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Parameter GEARBOXSLIP_IGNORE_COUNT bound to: 4'b1111
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Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer
|
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Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string
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Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string
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Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer
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Parameter TXSYNC_OVRD_IN bound to: 1'b0
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Parameter TXSYNC_MULTILANE_IN bound to: 1'b0
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WARNING: [Synth 8-689] width (2) of port connection 'mac_status_vector' does not match port width (3) of module 'axi_10g_ethernet_nonshared' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_block.v:164]
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WARNING: [Synth 8-350] instance 'axi_10g_ethernet_i' of module 'axi_10g_ethernet_nonshared' requires 51 connections, but only 50 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_block.v:148]
|
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'axi_10g_ethernet_i'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_block.v:148]
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Parameter C_BASE_ADDRESS bound to: 0 - type: integer
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Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
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Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer
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INFO: [Synth 8-155] case statement is not full and has no default [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:322]
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INFO: [Synth 8-638] synthesizing module 'identifier_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/synth/identifier_ip.vhd:85]
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Parameter C_FAMILY bound to: virtex7 - type: string
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Parameter C_XDEVICEFAMILY bound to: virtex7 - type: string
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Parameter C_ELABORATION_DIR bound to: ./ - type: string
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Parameter C_INTERFACE_TYPE bound to: 1 - type: integer
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Parameter C_AXI_TYPE bound to: 0 - type: integer
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Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer
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Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer
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Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer
|
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Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string
|
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Parameter C_HAS_AXI_ID bound to: 0 - type: integer
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Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer
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Parameter C_MEM_TYPE bound to: 1 - type: integer
|
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Parameter C_BYTE_SIZE bound to: 8 - type: integer
|
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Parameter C_ALGORITHM bound to: 1 - type: integer
|
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Parameter C_PRIM_TYPE bound to: 1 - type: integer
|
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Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer
|
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Parameter C_INIT_FILE_NAME bound to: identifier_ip.mif - type: string
|
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Parameter C_INIT_FILE bound to: identifier_ip.mem - type: string
|
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Parameter C_USE_DEFAULT_DATA bound to: 1 - type: integer
|
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Parameter C_DEFAULT_DATA bound to: DEADDEAD - type: string
|
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Parameter C_HAS_RSTA bound to: 0 - type: integer
|
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Parameter C_RST_PRIORITY_A bound to: CE - type: string
|
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Parameter C_RSTRAM_A bound to: 0 - type: integer
|
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Parameter C_INITA_VAL bound to: 0 - type: string
|
|||
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Parameter C_HAS_ENA bound to: 1 - type: integer
|
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Parameter C_HAS_REGCEA bound to: 0 - type: integer
|
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Parameter C_USE_BYTE_WEA bound to: 1 - type: integer
|
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Parameter C_WEA_WIDTH bound to: 4 - type: integer
|
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Parameter C_WRITE_MODE_A bound to: READ_FIRST - type: string
|
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Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer
|
|||
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Parameter C_READ_WIDTH_A bound to: 32 - type: integer
|
|||
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Parameter C_WRITE_DEPTH_A bound to: 4096 - type: integer
|
|||
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Parameter C_READ_DEPTH_A bound to: 4096 - type: integer
|
|||
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Parameter C_ADDRA_WIDTH bound to: 12 - type: integer
|
|||
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Parameter C_HAS_RSTB bound to: 1 - type: integer
|
|||
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Parameter C_RST_PRIORITY_B bound to: CE - type: string
|
|||
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Parameter C_RSTRAM_B bound to: 0 - type: integer
|
|||
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Parameter C_INITB_VAL bound to: 0 - type: string
|
|||
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Parameter C_HAS_ENB bound to: 1 - type: integer
|
|||
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Parameter C_HAS_REGCEB bound to: 0 - type: integer
|
|||
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Parameter C_USE_BYTE_WEB bound to: 1 - type: integer
|
|||
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Parameter C_WEB_WIDTH bound to: 4 - type: integer
|
|||
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Parameter C_WRITE_MODE_B bound to: READ_FIRST - type: string
|
|||
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Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer
|
|||
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Parameter C_READ_WIDTH_B bound to: 32 - type: integer
|
|||
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Parameter C_WRITE_DEPTH_B bound to: 4096 - type: integer
|
|||
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Parameter C_READ_DEPTH_B bound to: 4096 - type: integer
|
|||
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Parameter C_ADDRB_WIDTH bound to: 12 - type: integer
|
|||
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Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 0 - type: integer
|
|||
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Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer
|
|||
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Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer
|
|||
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Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer
|
|||
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Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer
|
|||
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Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer
|
|||
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Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer
|
|||
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Parameter C_USE_SOFTECC bound to: 0 - type: integer
|
|||
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Parameter C_USE_ECC bound to: 0 - type: integer
|
|||
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Parameter C_EN_ECC_PIPE bound to: 0 - type: integer
|
|||
|
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Parameter C_HAS_INJECTERR bound to: 0 - type: integer
|
|||
|
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Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string
|
|||
|
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Parameter C_COMMON_CLK bound to: 1 - type: integer
|
|||
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Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer
|
|||
|
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Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer
|
|||
|
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Parameter C_USE_URAM bound to: 0 - type: integer
|
|||
|
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Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer
|
|||
|
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Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer
|
|||
|
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Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer
|
|||
|
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Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer
|
|||
|
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Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer
|
|||
|
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Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer
|
|||
|
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Parameter C_COUNT_36K_BRAM bound to: 4 - type: string
|
|||
|
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Parameter C_COUNT_18K_BRAM bound to: 0 - type: string
|
|||
|
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Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 21.0181 mW - type: string
|
|||
|
|
INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_1' declared at '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/blk_mem_gen_v8_4_1/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195313' bound to instance 'U0' of component 'blk_mem_gen_v8_4_1' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/synth/identifier_ip.vhd:265]
|
|||
|
|
INFO: [Synth 8-256] done synthesizing module 'identifier_ip' (567#1) [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/synth/identifier_ip.vhd:85]
|
|||
|
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WARNING: [Synth 8-689] width (12) of port connection 's_axi_awaddr' does not match port width (32) of module 'identifier_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1229]
|
|||
|
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WARNING: [Synth 8-689] width (12) of port connection 's_axi_araddr' does not match port width (32) of module 'identifier_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1239]
|
|||
|
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WARNING: [Synth 8-350] instance 'identifier' of module 'identifier_ip' requires 21 connections, but only 19 given [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1226]
|
|||
|
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_datapath_0'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:564]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_0'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:908]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_1'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:990]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_2'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1068]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'nf_10g_interface_3'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:1148]
|
|||
|
|
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'control_sub_i'. This will prevent further optimization [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:696]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_RLAST
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_R_LAST_INT
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[7]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[6]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[5]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[4]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[3]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[2]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[1]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_fsm has unconnected port S_AXI_ARLEN[0]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARSIZE[2]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARSIZE[1]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARSIZE[0]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARBURST[1]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARBURST[0]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[3]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[2]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[1]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_axi_read_wrapper has unconnected port S_AXI_ARID[0]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MUX_RST[0]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MEM_LAT_RST
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MEM_REG_RST
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MUX_REGCE[0]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port MEM_REGCE
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port WE
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[11]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[10]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[9]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[8]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[7]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[6]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[5]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[4]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[3]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[2]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[1]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[0]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[7]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[6]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[5]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[3]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[0]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[7]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[6]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[5]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[4]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[3]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[2]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[1]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[0]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux__parameterized0 has unconnected port ECCPIPECE
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MUX_RST[0]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MEM_LAT_RST
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MEM_REG_RST
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MUX_REGCE[0]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port MEM_REGCE
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port WE
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[11]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[10]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[9]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[8]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[7]
|
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[6]
|
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[5]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[4]
|
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[3]
|
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[2]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[1]
|
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ADDR_IN[0]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[7]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[6]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[5]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[4]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[3]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[2]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[1]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port SBITERRIN[0]
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|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[7]
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[6]
|
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[5]
|
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[4]
|
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|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[3]
|
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|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[2]
|
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|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[1]
|
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|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port DBITERRIN[0]
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|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_mux has unconnected port ECCPIPECE
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WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port SSRA
|
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|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port REGCEA
|
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|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port SSRB
|
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|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port WEB[0]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[8]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[7]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[6]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[5]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[4]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[3]
|
|||
|
|
WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_1_blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port DINB[2]
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
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|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished RTL Elaboration : Time (s): cpu = 00:02:37 ; elapsed = 00:03:03 . Memory (MB): peak = 2240.238 ; gain = 915.746 ; free physical = 11422 ; free virtual = 14339
|
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|
---------------------------------------------------------------------------------
|
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|
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|
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Report Check Netlist:
|
|||
|
|
+------+------------------+-------+---------+-------+------------------+
|
|||
|
|
| |Item |Errors |Warnings |Status |Description |
|
|||
|
|
+------+------------------+-------+---------+-------+------------------+
|
|||
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
|||
|
|
+------+------------------+-------+---------+-------+------------------+
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin arbiter_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/input_arbiter.v:348]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin lf3x44qdk2z74a1s0gndyt27sldl_779:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:409]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin lf3x44qdk2z74a1s0gndyt27sldl_779:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:409]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin q7gvskyh9rdb9henjto295zvigo9_974:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:450]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin q7gvskyh9rdb9henjto295zvigo9_974:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:450]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:491]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:491]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin blb6zofu4m1iwfz7b9fn78j_619:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:534]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin blb6zofu4m1iwfz7b9fn78j_619:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v:534]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin xnn8oc66i3dtvlfhp0bahskooll2x2_2380:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:661]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin xnn8oc66i3dtvlfhp0bahskooll2x2_2380:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:661]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin xw49r6188i46a9wjd0nkk1oksp_526:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:702]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin xw49r6188i46a9wjd0nkk1oksp_526:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:702]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin nqj3a7on863ee2q57ufzkn6sb2_2042:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:743]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin nqj3a7on863ee2q57ufzkn6sb2_2042:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:743]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin f2xqwifp1sq1wjip1qs5_1422:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:786]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin f2xqwifp1sq1wjip1qs5_1422:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:786]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin vgsz2hwji6xt2tcnqha3_994:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:829]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin vgsz2hwji6xt2tcnqha3_994:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:829]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin jwu7vwv11bfiar50ae_2490:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:872]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin jwu7vwv11bfiar50ae_2490:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:872]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin m150wixgtma9i0g8y0g7_645:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:915]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin m150wixgtma9i0g8y0g7_645:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:915]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin y06wki9vylrmylq2v_2571:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:958]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin y06wki9vylrmylq2v_2571:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v:958]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin avehixb9cn0lazkk9ssg_157:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:787]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin avehixb9cn0lazkk9ssg_157:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:787]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin u34kvw4geng8wp39esl2j727nx7c0_647:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:828]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin u34kvw4geng8wp39esl2j727nx7c0_647:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:828]
|
|||
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WARNING: [Synth 8-3295] tying undriven pin gbqfimspskm6hnlgzqqao1mt5w_1310:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:869]
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WARNING: [Synth 8-3295] tying undriven pin gbqfimspskm6hnlgzqqao1mt5w_1310:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:869]
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|||
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WARNING: [Synth 8-3295] tying undriven pin xvxcv5ctaicypzrsuzoa92bpsxv_1486:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:912]
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WARNING: [Synth 8-3295] tying undriven pin xvxcv5ctaicypzrsuzoa92bpsxv_1486:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:912]
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WARNING: [Synth 8-3295] tying undriven pin itav5rgzqhzrf7n00dmq9hj_2570:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:955]
|
|||
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WARNING: [Synth 8-3295] tying undriven pin itav5rgzqhzrf7n00dmq9hj_2570:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:955]
|
|||
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WARNING: [Synth 8-3295] tying undriven pin rqlk2vb5gdzd29aq4s0qdonhh2_1914:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:998]
|
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WARNING: [Synth 8-3295] tying undriven pin rqlk2vb5gdzd29aq4s0qdonhh2_1914:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:998]
|
|||
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WARNING: [Synth 8-3295] tying undriven pin wboy95wr5obljm9n9nzzz5j30dc2v6h_2139:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1041]
|
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WARNING: [Synth 8-3295] tying undriven pin wboy95wr5obljm9n9nzzz5j30dc2v6h_2139:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1041]
|
|||
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WARNING: [Synth 8-3295] tying undriven pin xan657w55lznzq3hcpp22k9a_2275:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1084]
|
|||
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WARNING: [Synth 8-3295] tying undriven pin xan657w55lznzq3hcpp22k9a_2275:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1084]
|
|||
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|
WARNING: [Synth 8-3295] tying undriven pin uswzetjhoap7d9wrf4i9dhm9lwzf_2235:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1127]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin uswzetjhoap7d9wrf4i9dhm9lwzf_2235:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1127]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin xe63wyalaxqi3pjbu72rro2_1653:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1170]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin xe63wyalaxqi3pjbu72rro2_1653:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v:1170]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin jkyzocxmm0s4149oa1_1899:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:661]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin jkyzocxmm0s4149oa1_1899:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:661]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin izzp83m68hsu2ozh14472qcg_421:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:702]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin izzp83m68hsu2ozh14472qcg_421:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:702]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin pvmmu0cz9e244pe3fiu49stpb6kwfc_144:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:743]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin pvmmu0cz9e244pe3fiu49stpb6kwfc_144:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:743]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin r0sf3f4b9u0hx8wiyii96zm26iev_2414:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:786]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin r0sf3f4b9u0hx8wiyii96zm26iev_2414:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:786]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin ht1zdw1pp2sdohld_2567:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:829]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin ht1zdw1pp2sdohld_2567:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:829]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin itbaw93kgsedybjcawtjyy1ivrr3ksj_977:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:872]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin itbaw93kgsedybjcawtjyy1ivrr3ksj_977:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:872]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin bg3rgtuwucqmjzmclir9q2k5ps_794:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:915]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin bg3rgtuwucqmjzmclir9q2k5ps_794:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:915]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin xdgk72zc6lz2v1f6_638:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:958]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin xdgk72zc6lz2v1f6_638:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v:958]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin gp7dlwqm2bugfp4a69nq18to_18:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:479]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin gp7dlwqm2bugfp4a69nq18to_18:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:479]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin wfqws46340wyslrwid2yow_1831:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:520]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin wfqws46340wyslrwid2yow_1831:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:520]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin ffbkdipo4aqln89eo1a_180:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:561]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin ffbkdipo4aqln89eo1a_180:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:561]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin t3nvy4hx7fbwz0fzqej0kwod6wj_790:injectsbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:604]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin t3nvy4hx7fbwz0fzqej0kwod6wj_790:injectdbiterr to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v:604]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin sss_output_queues_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_output_queues.v:643]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin nf_10g_interface_shared_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared.v:261]
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin nf_10g_interface_cpu_regs_inst:cpu_resetn_soft to constant 0 [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface.v:262]
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Handling Custom Attributes
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:02:41 ; elapsed = 00:03:07 . Memory (MB): peak = 2240.238 ; gain = 915.746 ; free physical = 11521 ; free virtual = 14438
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:02:41 ; elapsed = 00:03:07 . Memory (MB): peak = 2240.238 ; gain = 915.746 ; free physical = 11521 ; free virtual = 14438
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
INFO: [Netlist 29-17] Analyzing 246 Unisim elements for replacement
|
|||
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|||
|
|
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
|
|||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|||
|
|
|
|||
|
|
Processing XDC Constraints
|
|||
|
|
Initializing timing engine
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0'
|
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0/control_sub_mdm_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0/control_sub_mdm_1_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0/control_sub_microblaze_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0/control_sub_microblaze_0_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10'
|
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0/control_sub_lmb_bram_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0/control_sub_lmb_bram_0_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1/control_sub_xbar_1_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1/control_sub_xbar_1_in_context.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie_reset_inv'
|
|||
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie_reset_inv'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0_in_context.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0/control_sub_xbar_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0/control_sub_xbar_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo'
|
|||
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo'
|
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|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo'
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|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo'
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo'
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0/control_sub_m07_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0/control_sub_auto_cc_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0/control_sub_auto_cc_0_in_context.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
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|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:53]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:55]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:57]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:60]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:62]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:64]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:67]
|
|||
|
|
WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:69]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:70]
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:53]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:55]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:57]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:60]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:62]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:64]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:67]
|
|||
|
|
WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:69]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:70]
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:53]
|
|||
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WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:55]
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WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:57]
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WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:60]
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WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:62]
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WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:64]
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WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:67]
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WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:69]
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WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:70]
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:54]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:56]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:58]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:61]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:63]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:65]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:68]
|
|||
|
|
WARNING: [Vivado 12-180] No cells matched 'get_cells -of [filter [all_fanout -flat -endpoints_only -from [get_pins -filter NAME=~*/Q -of_objects [get_cells -hierarchical -filter {NAME =~ *rxratecounter_i*rxusrclk2_en156*}]]] {NAME =~ *WE}]'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:70]
|
|||
|
|
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:71]
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
|
|||
|
|
INFO: [Timing 38-2] Deriving generated clocks
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
|
|||
|
|
WARNING: [Vivado 12-507] No nets matched 'control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/pipe_txoutclk_out'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc:116]
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
|
|||
|
|
WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/top_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied.
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'xphy_refclk_p' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:92]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:114]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:115]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:116]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:117]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:118]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:119]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:120]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:121]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'clk_250mhz_mux_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'clk_125mhz_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:134]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'clk_125mhz_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'clk_250mhz_mux_x0y1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:135]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:137]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:137]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:138]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:138]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:140]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:140]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:141]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:141]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:143]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:143]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:144]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:144]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:146]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:146]
|
|||
|
|
WARNING: [Vivado 12-627] No clocks matched 'userclk1'. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:147]
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:147]
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
|
|||
|
|
WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/top_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied.
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/dont_touch.xdc]
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/dont_touch.xdc]
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
INFO: [Common 17-14] Message 'Vivado 12-3272' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
INFO: [Common 17-14] Message 'XPM_CDC_GRAY: TCL 1000' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
|
|||
|
|
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
|
|||
|
|
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
|
|||
|
|
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
|
|||
|
|
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
|
|||
|
|
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Completed Processing XDC Constraints
|
|||
|
|
|
|||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|||
|
|
A total of 192 instances were transformed.
|
|||
|
|
BUFGCE => BUFGCTRL: 1 instances
|
|||
|
|
FDR => FDRE: 12 instances
|
|||
|
|
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
|
|||
|
|
MUXCY_L => MUXCY: 176 instances
|
|||
|
|
SRL16 => SRL16E: 1 instances
|
|||
|
|
|
|||
|
|
Constraint Validation Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3891.996 ; gain = 0.000 ; free physical = 9711 ; free virtual = 12633
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_clock_converter_0' at clock pin 's_axi_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_dwidth_dma_rx' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_dwidth_dma_tx' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_fifo_10g_rx' at clock pin 'm_axis_aclk' is different from the actual clock period '4.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axis_fifo_10g_tx' at clock pin 'm_axis_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/xbar' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc' at clock pin 'm_axi_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.
|
|||
|
|
WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram' at clock pin 'clka' is different from the actual clock period '10.000', this can lead to different synthesis results.
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Constraint Validation : Time (s): cpu = 00:04:57 ; elapsed = 00:05:36 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 11016 ; free virtual = 13940
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 4 processes.
|
|||
|
|
INFO: [Synth 8-4471] merging register 'seq_cnt_en_reg' into 'from_sys_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:377]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element seq_cnt_en_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:377]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'sume_to_sdnet'
|
|||
|
|
INFO: [Synth 8-5546] ROM "c3tbszppn1ncxo8s896wp4zsbt_455" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "cm7eal4pxrjzfl5hr_627" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "z8iceu6x6l8iuug6jfho92_74" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5544] ROM "size_0" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "CamReg_reg[3]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "CamReg_reg[2]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "CamReg_reg[1]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "CamReg_reg[0]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'UpdateFSM_reg' in module 'realmain_v4_networks_0_t_Update'
|
|||
|
|
INFO: [Synth 8-5544] ROM "Entry_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "Count_G" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "UpdateFSM_D0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "UpdateFSM_D" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5546] ROM "wack_i" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5544] ROM "term10R" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_0_Editor_FifoReader'
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "MUX_EditCmd_offsetEop" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'FSM_state_reg' in module 'TopDeparser_t_EngineStage_2_Editor_FifoReader'
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "FSM_state1" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "MUX_EditCmd_offsetEop" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "MUX_EditDat_0_MASK" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "MUX_EditDat_0_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "MUX_EditDat_1_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "MUX_EditDat_2_MASK" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "MUX_EditDat_2_POS" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.rst_seq_reentered" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.fifo_wr_rst_i" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.wr_rst_busy_i" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_rrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_rrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'S_PROTOCOL_ADAPTER_INGRESS'
|
|||
|
|
INFO: [Synth 8-5544] ROM "nxt_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "nxt_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "nxt_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "nxt_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized1'
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_fwft.leaving_empty_fwft" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_fwft.next_fwft_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_fwft.next_fwft_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_fwft.next_fwft_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_fwft.next_fwft_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__2'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__2'
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.rst_seq_reentered" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.fifo_wr_rst_i" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.wr_rst_busy_i" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_rrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_rrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__3'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__3'
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.rst_seq_reentered" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.fifo_wr_rst_i" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.wr_rst_busy_i" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_wrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_rrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Synth 8-5544] ROM "gen_rst_ic.next_rrst_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-5544' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized5'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__4'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__4'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__5'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__5'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__6'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__6'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__7'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__7'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__8'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__8'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__9'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__9'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized12'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__10'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__10'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__11'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__11'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__12'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__12'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__13'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__13'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__14'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__14'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__15'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__15'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__16'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__16'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__17'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__17'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized22'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__18'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__18'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__19'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__19'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__20'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__20'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__21'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__21'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__22'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__22'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__23'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__23'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1030]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__24'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__24'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:827]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/sss_output_queues_ip/hdl/sss_small_fifo.v:103]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'sss_output_queues'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[0].metadata_state_reg[0]' in module 'sss_output_queues'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[1].metadata_state_reg[1]' in module 'sss_output_queues'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[2].metadata_state_reg[2]' in module 'sss_output_queues'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[3].metadata_state_reg[3]' in module 'sss_output_queues'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'sss_output_queues[4].metadata_state_reg[4]' in module 'sss_output_queues'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'rs_state_reg' in module 'ten_gig_eth_mac_v15_1_6_rs_64bit'
|
|||
|
|
INFO: [Synth 8-5546] ROM "crc_position_int" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "dic_required" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "dic_returned" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "poss_ifg_count" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5546] ROM "control_frame" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5546] ROM "control_frame" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "frame_size" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "byte_count" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'pause_state_reg' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'legacy_state_reg' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'pause_state_reg' in module 'ten_gig_eth_mac_v15_1_6_tx_pause_cntl'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'rx_state_int_reg' in module 'ten_gig_eth_mac_v15_1_6_rx_fsm'
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5546] ROM "frame_max" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5545] ROM "broadcast_detect" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5546] ROM "control_frame_any_add" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "pause_opcode" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "pfc_opcode" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5545] ROM "special_addr_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5546] ROM "early_truncate" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "early_truncate" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'pause_state_reg' in module 'ten_gig_eth_mac_v15_1_6_rx_control'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'mcp1_state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_idle_delete'
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "s_code_c0" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "s_code_c4" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_tx_pcs_fsm'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'mcp1_state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_block_lock_fsm'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'mcp1_state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_ber_mon_fsm'
|
|||
|
|
INFO: [Synth 8-5546] ROM "mcp1_rx_64_ctrl_out" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "IsValidControl" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "IsValidControl0" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "IsValidControl1" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "IsValidControl2" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "IsValidControl3" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "IsValidControl4" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "IsValidControl5" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "IsValidControl6" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5587] ROM size for "DecodeWord" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-5587] ROM size for "DecodeWord0" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-5587] ROM size for "DecodeWord1" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-5587] ROM size for "DecodeWord2" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-5587] ROM size for "DecodeWord3" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-5587] ROM size for "DecodeWord4" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-5587] ROM size for "DecodeWord5" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-5587] ROM size for "DecodeWord6" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'mcp1_state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_pcs_fsm'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_cs_ipif_access'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ten_gig_eth_pcs_pma_v6_0_13_drp_ipif'
|
|||
|
|
INFO: [Synth 8-5587] ROM size for "gt_txd_mux" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-5587] ROM size for "gt_txc_mux" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'rx_queue__xdcDup__1'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'err_state_reg' in module 'rx_queue__xdcDup__1'
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
|
|||
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/input_arbiter_ip/hdl/small_fifo.v:97]
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'tx_queue__xdcDup__1'
|
|||
|
|
INFO: [Synth 8-5546] ROM "tkeep_encoded_i" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'rx_queue__xdcDup__2'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'err_state_reg' in module 'rx_queue__xdcDup__2'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'tx_queue__xdcDup__2'
|
|||
|
|
INFO: [Synth 8-5546] ROM "tkeep_encoded_i" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'rx_queue__xdcDup__3'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'err_state_reg' in module 'rx_queue__xdcDup__3'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'tx_queue__xdcDup__3'
|
|||
|
|
INFO: [Synth 8-5546] ROM "tkeep_encoded_i" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'rx_queue'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'err_state_reg' in module 'rx_queue'
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'tx_queue'
|
|||
|
|
INFO: [Synth 8-5546] ROM "tkeep_encoded_i" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-802] inferred FSM for state register 'gaxi_lite_sm.present_state_reg' in module 'blk_mem_gen_v8_4_1_blk_mem_axi_write_fsm'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
FIRST | 0 | 00
|
|||
|
|
WAIT | 1 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'sume_to_sdnet'
|
|||
|
|
INFO: [Synth 8-3971] The signal gen_wr_b.gen_word_narrow.mem_reg was recognized as a true dual port RAM template.
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
FSM_INIT | 1010 | 0000
|
|||
|
|
FSM_IDLE | 0011 | 0001
|
|||
|
|
FSM_LOOK_READ2 | 1000 | 1011
|
|||
|
|
FSM_LOOK_READ | 0111 | 0010
|
|||
|
|
FSM_LOOK_WRITE | 0000 | 0011
|
|||
|
|
FSM_CAM_DEL1 | 0001 | 1001
|
|||
|
|
FSM_CAM_DEL2 | 1001 | 1010
|
|||
|
|
FSM_CAM_POP | 0010 | 0111
|
|||
|
|
FSM_CAM_LATCH | 1011 | 1000
|
|||
|
|
FSM_ADD_READ | 0100 | 0100
|
|||
|
|
FSM_CAM_PUSH | 0101 | 0110
|
|||
|
|
FSM_ADD_WRITE | 0110 | 0101
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'UpdateFSM_reg' using encoding 'sequential' in module 'realmain_v4_networks_0_t_Update'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
FSM_IDLE | 0000001 | 000
|
|||
|
|
FSM_INSERT_PAD | 0000010 | 100
|
|||
|
|
FSM_INSERT_2 | 0000100 | 101
|
|||
|
|
FSM_REMOVE_2 | 0001000 | 001
|
|||
|
|
FSM_REMOVE_WAIT_EOP | 0010000 | 010
|
|||
|
|
FSM_INSERT_WAIT_EOP | 0100000 | 110
|
|||
|
|
FSM_INSERT_FLUSH | 1000000 | 111
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_0_Editor_FifoReader'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
FSM_IDLE | 0000001 | 000
|
|||
|
|
FSM_INSERT_PAD | 0000010 | 100
|
|||
|
|
FSM_INSERT_2 | 0000100 | 101
|
|||
|
|
FSM_REMOVE_2 | 0001000 | 001
|
|||
|
|
FSM_REMOVE_WAIT_EOP | 0010000 | 010
|
|||
|
|
FSM_INSERT_WAIT_EOP | 0100000 | 110
|
|||
|
|
FSM_INSERT_FLUSH | 1000000 | 111
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'FSM_state_reg' using encoding 'one-hot' in module 'TopDeparser_t_EngineStage_2_Editor_FifoReader'
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__1'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 00 | 001
|
|||
|
|
RX_SOF_EOF | 01 | 011
|
|||
|
|
RX_SOF | 10 | 010
|
|||
|
|
RX_PKT | 11 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'S_PROTOCOL_ADAPTER_INGRESS'
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
invalid | 00 | 00
|
|||
|
|
stage1_valid | 01 | 10
|
|||
|
|
both_stages_valid | 10 | 11
|
|||
|
|
stage2_valid | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized1'
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__2'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__2'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__3'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__3'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
invalid | 00 | 00
|
|||
|
|
stage1_valid | 01 | 10
|
|||
|
|
both_stages_valid | 10 | 11
|
|||
|
|
stage2_valid | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized5'
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__4'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__4'
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__5'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__5'
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__6'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__6'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__7'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__7'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__8'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__8'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__9'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__9'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
invalid | 00 | 00
|
|||
|
|
stage1_valid | 01 | 10
|
|||
|
|
both_stages_valid | 10 | 11
|
|||
|
|
stage2_valid | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized12'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__10'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__10'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__11'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__11'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__12'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__12'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__13'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__13'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__14'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__14'
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__15'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__15'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__16'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__16'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__17'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__17'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
invalid | 00 | 00
|
|||
|
|
stage1_valid | 01 | 10
|
|||
|
|
both_stages_valid | 10 | 11
|
|||
|
|
stage2_valid | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized22'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__18'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__18'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__19'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__19'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__20'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__20'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__21'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__21'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__22'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__22'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__23'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__23'
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__24'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__24'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WRST_IDLE | 00001 | 000
|
|||
|
|
WRST_IN | 00010 | 010
|
|||
|
|
WRST_OUT | 00100 | 111
|
|||
|
|
WRST_EXIT | 01000 | 110
|
|||
|
|
WRST_GO2IDLE | 10000 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RRST_IDLE | 00 | 00
|
|||
|
|
RRST_IN | 01 | 10
|
|||
|
|
RRST_OUT | 10 | 11
|
|||
|
|
RRST_EXIT | 11 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 001 | 000
|
|||
|
|
WR_PKT | 010 | 001
|
|||
|
|
DROP | 100 | 010
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'sss_output_queues'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WAIT_HEADER | 0 | 00
|
|||
|
|
WAIT_EOP | 1 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[0].metadata_state_reg[0]' using encoding 'sequential' in module 'sss_output_queues'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WAIT_HEADER | 0 | 00
|
|||
|
|
WAIT_EOP | 1 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[1].metadata_state_reg[1]' using encoding 'sequential' in module 'sss_output_queues'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WAIT_HEADER | 0 | 00
|
|||
|
|
WAIT_EOP | 1 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[2].metadata_state_reg[2]' using encoding 'sequential' in module 'sss_output_queues'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WAIT_HEADER | 0 | 00
|
|||
|
|
WAIT_EOP | 1 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[3].metadata_state_reg[3]' using encoding 'sequential' in module 'sss_output_queues'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
WAIT_HEADER | 0 | 00
|
|||
|
|
WAIT_EOP | 1 | 01
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'sss_output_queues[4].metadata_state_reg[4]' using encoding 'sequential' in module 'sss_output_queues'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INIT | 00 | 00
|
|||
|
|
COUNT | 01 | 01
|
|||
|
|
FAULT | 10 | 11
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'rs_state_reg' using encoding 'sequential' in module 'ten_gig_eth_mac_v15_1_6_rs_64bit'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 0001 | 000
|
|||
|
|
REQ | 0010 | 001
|
|||
|
|
WAIT | 0100 | 010
|
|||
|
|
COUNT | 1000 | 011
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'legacy_state_reg' using encoding 'one-hot' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
P_IDLE | 00 | 00
|
|||
|
|
P_REQ | 01 | 01
|
|||
|
|
P_WAIT | 10 | 10
|
|||
|
|
P_HOLD | 11 | 11
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'pause_state_reg' using encoding 'sequential' in module 'ten_gig_eth_mac_v15_1_6_pfc_tx_cntl'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 001 | 00
|
|||
|
|
REQUEST | 010 | 01
|
|||
|
|
SEND | 100 | 10
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'pause_state_reg' using encoding 'one-hot' in module 'ten_gig_eth_mac_v15_1_6_tx_pause_cntl'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 000 | 000
|
|||
|
|
CHECK_MIN | 001 | 001
|
|||
|
|
DATA | 010 | 010
|
|||
|
|
BAD_STRIP | 011 | 011
|
|||
|
|
VALIDATE | 100 | 100
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'rx_state_int_reg' using encoding 'sequential' in module 'ten_gig_eth_mac_v15_1_6_rx_fsm'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 00001 | 000
|
|||
|
|
LEGACY | 00010 | 001
|
|||
|
|
PFC | 00100 | 100
|
|||
|
|
PFCQ3_Q6 | 01000 | 101
|
|||
|
|
PFCQ7 | 10000 | 110
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'pause_state_reg' using encoding 'one-hot' in module 'ten_gig_eth_mac_v15_1_6_rx_control'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
STRAIGHT | 000 | 000
|
|||
|
|
DELETE3 | 001 | 010
|
|||
|
|
DELETE1 | 010 | 001
|
|||
|
|
TWISTED | 011 | 100
|
|||
|
|
POSSIBLE_DELETE4 | 100 | 011
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'mcp1_state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_idle_delete'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
TX_INIT | 000 | 000
|
|||
|
|
TX_E | 001 | 100
|
|||
|
|
TX_C | 010 | 001
|
|||
|
|
TX_D | 011 | 010
|
|||
|
|
TX_T | 100 | 011
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_tx_pcs_fsm'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
LOCK_INIT | 00 | 00
|
|||
|
|
RESET_CNT | 01 | 01
|
|||
|
|
TEST_VALID_INVALID_SH | 10 | 10
|
|||
|
|
SLIP | 11 | 11
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'mcp1_state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_block_lock_fsm'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
BER_MT_INIT | 000 | 000
|
|||
|
|
START_TIMER | 001 | 001
|
|||
|
|
BER_TEST_SH | 010 | 010
|
|||
|
|
BER_BAD_SH | 011 | 011
|
|||
|
|
HI_BER | 100 | 100
|
|||
|
|
GOOD_BER | 101 | 101
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'mcp1_state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_ber_mon_fsm'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
RX_INIT | 000 | 000
|
|||
|
|
RX_E | 001 | 100
|
|||
|
|
RX_T | 010 | 011
|
|||
|
|
RX_C | 011 | 001
|
|||
|
|
RX_D | 100 | 010
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'mcp1_state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_rx_pcs_fsm'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 00 | 000
|
|||
|
|
RDREQ1 | 01 | 001
|
|||
|
|
RDPENDING1 | 10 | 010
|
|||
|
|
RDRESP1 | 11 | 011
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_cs_ipif_access'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 00 | 00
|
|||
|
|
REQ | 01 | 01
|
|||
|
|
GNT | 10 | 10
|
|||
|
|
GNT1 | 11 | 11
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ten_gig_eth_pcs_pma_v6_0_13_drp_ipif'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
ERR_BUBBLE | 00 | 010
|
|||
|
|
ERR_IDLE | 01 | 000
|
|||
|
|
ERR_WAIT | 10 | 001
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'err_state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__1'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 00 | 0000
|
|||
|
|
WAIT_FOR_EOP | 01 | 0001
|
|||
|
|
BUBBLE | 10 | 0011
|
|||
|
|
DROP | 11 | 0010
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__1'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 0 | 000
|
|||
|
|
SEND_PKT | 1 | 001
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'tx_queue__xdcDup__1'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
ERR_BUBBLE | 00 | 010
|
|||
|
|
ERR_IDLE | 01 | 000
|
|||
|
|
ERR_WAIT | 10 | 001
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'err_state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__2'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 00 | 0000
|
|||
|
|
WAIT_FOR_EOP | 01 | 0001
|
|||
|
|
BUBBLE | 10 | 0011
|
|||
|
|
DROP | 11 | 0010
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__2'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 0 | 000
|
|||
|
|
SEND_PKT | 1 | 001
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'tx_queue__xdcDup__2'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
ERR_BUBBLE | 00 | 010
|
|||
|
|
ERR_IDLE | 01 | 000
|
|||
|
|
ERR_WAIT | 10 | 001
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'err_state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__3'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 00 | 0000
|
|||
|
|
WAIT_FOR_EOP | 01 | 0001
|
|||
|
|
BUBBLE | 10 | 0011
|
|||
|
|
DROP | 11 | 0010
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'rx_queue__xdcDup__3'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 0 | 000
|
|||
|
|
SEND_PKT | 1 | 001
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'tx_queue__xdcDup__3'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
ERR_BUBBLE | 00 | 010
|
|||
|
|
ERR_IDLE | 01 | 000
|
|||
|
|
ERR_WAIT | 10 | 001
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'err_state_reg' using encoding 'sequential' in module 'rx_queue'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 00 | 0000
|
|||
|
|
WAIT_FOR_EOP | 01 | 0001
|
|||
|
|
BUBBLE | 10 | 0011
|
|||
|
|
DROP | 11 | 0010
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'rx_queue'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
IDLE | 0 | 000
|
|||
|
|
SEND_PKT | 1 | 001
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'tx_queue'
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
State | New Encoding | Previous Encoding
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
wait_wraddr | 00 | 00
|
|||
|
|
reg_wraddr | 01 | 01
|
|||
|
|
os_wr | 10 | 10
|
|||
|
|
wr_mem | 11 | 11
|
|||
|
|
---------------------------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'gaxi_lite_sm.present_state_reg' using encoding 'sequential' in module 'blk_mem_gen_v8_4_1_blk_mem_axi_write_fsm'
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:05:32 ; elapsed = 00:06:14 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 8726 ; free virtual = 11672
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
|
|||
|
|
Report RTL Partitions:
|
|||
|
|
+------+-------------------------------------------+------------+----------+
|
|||
|
|
| |RTL Partition |Replication |Instances |
|
|||
|
|
+------+-------------------------------------------+------------+----------+
|
|||
|
|
|1 |clk_wiz_ip_clk_wiz__GC0 | 1| 13|
|
|||
|
|
|2 |TopParser_t_EngineStage_0__GB0 | 1| 28775|
|
|||
|
|
|3 |TopParser_t_EngineStage_0__GB1 | 1| 25887|
|
|||
|
|
|4 |TopParser_t_EngineStage_0__GB2 | 1| 28664|
|
|||
|
|
|5 |TopParser_t_EngineStage_0__GB3 | 1| 16349|
|
|||
|
|
|6 |TopParser_t_EngineStage_0__GB4 | 1| 10235|
|
|||
|
|
|7 |TopParser_t_EngineStage_1__GB0 | 1| 31065|
|
|||
|
|
|8 |TopParser_t_EngineStage_1__GB1 | 1| 8421|
|
|||
|
|
|9 |TopParser_t_EngineStage_1__GB2 | 1| 11093|
|
|||
|
|
|10 |TopParser_t_EngineStage_1__GB3 | 1| 9735|
|
|||
|
|
|11 |TopParser_t_EngineStage_1__GB4 | 1| 13021|
|
|||
|
|
|12 |TopParser_t_Engine__GC0 | 1| 4217|
|
|||
|
|
|13 |TopParser_t__GC0 | 1| 19|
|
|||
|
|
|14 |TopPipe_lvl_0_t_Engine__GB0 | 1| 36027|
|
|||
|
|
|15 |TopPipe_lvl_0_t_Engine__GB1 | 1| 21037|
|
|||
|
|
|16 |TopDeparser_t_EngineStage_0__GB0 | 1| 33016|
|
|||
|
|
|17 |TopDeparser_t_EngineStage_0__GB1 | 1| 6497|
|
|||
|
|
|18 |TopDeparser_t_EngineStage_0__GB2 | 1| 18695|
|
|||
|
|
|19 |reg__1136 | 1| 1403|
|
|||
|
|
|20 |TopDeparser_t_EngineStage_2_Editor__GB0 | 1| 29502|
|
|||
|
|
|21 |TopDeparser_t_EngineStage_2_Editor__GB1 | 1| 12589|
|
|||
|
|
|22 |TopDeparser_t_EngineStage_2__GC0 | 1| 29563|
|
|||
|
|
|23 |TopDeparser_t_Engine__GC0 | 1| 34743|
|
|||
|
|
|24 |TopDeparser_t__GC0 | 1| 21|
|
|||
|
|
|25 |SimpleSumeSwitch__GCB0 | 1| 29429|
|
|||
|
|
|26 |SimpleSumeSwitch__GCB1 | 1| 13513|
|
|||
|
|
|27 |SimpleSumeSwitch__GCB2 | 1| 15125|
|
|||
|
|
|28 |nf_sume_sdnet__GC0 | 1| 11|
|
|||
|
|
|29 |nf_datapath__GCB0 | 1| 23530|
|
|||
|
|
|30 |nf_datapath__GCB1 | 1| 10473|
|
|||
|
|
|31 |bd_a1aa_xpcs_0_shared_clock_and_reset__GC0 | 1| 53|
|
|||
|
|
|32 |ten_gig_eth_pcs_pma_v6_0_13 | 2| 14863|
|
|||
|
|
|33 |bd_a1aa_xpcs_0_block__GC0 | 1| 899|
|
|||
|
|
|34 |bd_a1aa_xpcs_0_support__GC0 | 1| 2|
|
|||
|
|
|35 |bd_a1aa__GC0 | 1| 15327|
|
|||
|
|
|36 |nf_10g_interface_shared_block__GC0 | 1| 11027|
|
|||
|
|
|37 |nf_10g_interface_shared__GC0 | 1| 2767|
|
|||
|
|
|38 |bd_7ad4_xmac_0_block | 3| 15327|
|
|||
|
|
|39 |bd_7ad4_xpcs_0_block__GC0 | 1| 899|
|
|||
|
|
|40 |nf_10g_interface_block__xdcDup__1__GC0 | 1| 11027|
|
|||
|
|
|41 |nf_10g_interface__xdcDup__1__GC0 | 1| 2758|
|
|||
|
|
|42 |nf_10g_interface_block__xdcDup__2__GC0 | 1| 11027|
|
|||
|
|
|43 |nf_10g_interface__xdcDup__2__GC0 | 1| 2758|
|
|||
|
|
|44 |nf_10g_interface_block__GC0 | 1| 11027|
|
|||
|
|
|45 |nf_10g_interface__GC0 | 1| 2758|
|
|||
|
|
|46 |top__GC0 | 1| 8070|
|
|||
|
|
+------+-------------------------------------------+------------+----------+
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start RTL Component Statistics
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished RTL Component Statistics
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start RTL Hierarchical Component Statistics
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished RTL Hierarchical Component Statistics
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Part Resource Summary
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Part Resources:
|
|||
|
|
DSPs: 3600 (col length:200)
|
|||
|
|
BRAMs: 2940 (col length: RAMB18 200 RAMB36 100)
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Part Resource Summary
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Cross Boundary and Area Optimization
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25)
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_shared_cpu_regs_inst/resetn_soft_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_shared_ip/hdl/nf_10g_interface_shared_cpu_regs.v:155]
|
|||
|
|
INFO: [Synth 8-5545] ROM "master_watchdog_barking" won't be mapped to RAM because address size (29) is larger than maximum supported(25)
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_cpu_regs_inst/resetn_soft_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:155]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_cpu_regs_inst/resetn_soft_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:155]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element nf_10g_interface_cpu_regs_inst/resetn_soft_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_10g_interface_ip/hdl/nf_10g_interface_cpu_regs.v:155]
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[0] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[1] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[2] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[3] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[4] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[5] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[6] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[7] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[8] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[9] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[10] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[11] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[12] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[13] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[14] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[15] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[16] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[17] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[18] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[19] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[20] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[21] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[22] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[23] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[24] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[25] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[26] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[27] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[28] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[29] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[30] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_extracts_0_reg[31] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[0] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[1] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[2] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[3] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[4] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[5] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[6] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[7] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[8] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[9] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[10] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[11] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[12] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[13] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[14] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[15] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[16] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[17] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[18] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[19] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[20] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[21] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[22] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[23] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[24] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[25] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[26] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[27] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[28] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[29] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[30] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[31] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[32] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[33] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[34] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[35] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[36] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[37] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[38] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[39] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[40] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[41] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[42] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[43] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[44] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[45] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[46] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[47] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[48] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[49] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[50] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[51] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[52] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[53] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[54] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[55] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[56] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[57] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[58] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[59] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[60] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[61] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[62] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[63] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[64] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[65] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[66] )
|
|||
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (nf_datapath_0/nf_sume_sdnet_wrapper_1/\inst/SimpleSumeSwitch_inst/TopParser/TopParser_t_inst /i_0/\TUPLE_TopParser_fl_0_reg[67] )
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[0]' (FD) to 'nf_10g_interface_0/insti_0/id_reg_reg[4]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[0]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[1]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[1]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[2]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[2]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[3]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[3]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[4]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[4]' (FD) to 'nf_10g_interface_0/insti_0/id_reg_reg[8]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[5]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[5]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[6]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[6]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[7]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[7]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[8]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[9]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[8]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[8]' (FD) to 'nf_10g_interface_0/insti_0/id_reg_reg[9]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[9]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[10]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[9]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[9]' (FD) to 'nf_10g_interface_0/insti_0/id_reg_reg[10]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[10]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[11]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[10]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[10]' (FD) to 'nf_10g_interface_0/insti_0/id_reg_reg[11]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[11]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[12]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[11]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[11]' (FD) to 'nf_10g_interface_0/insti_0/id_reg_reg[12]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[12]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[13]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[12]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[13]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[14]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[13]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[13]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[14]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[15]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[14]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[14]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[15]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[16]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[15]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[15]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[16]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[17]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[16]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[17]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[18]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[17]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[18]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[19]'
|
|||
|
|
INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[18]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[19]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[20]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[19]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[20]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[21]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[20]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[21]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[22]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[21]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[22]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[23]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[22]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[23]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[24]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[23]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[24]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[25]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[24]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[24]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[25]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[26]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[25]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[25]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[26]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[27]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[26]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[26]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[27]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[28]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[27]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[27]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[28]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[29]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[28]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[29]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[30]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[29]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[29]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[30]' (FDR) to 'nf_10g_interface_0/insti_0/interfaceid_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[30]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/id_reg_reg[30]' (FD) to 'nf_10g_interface_0/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/version_reg_reg[31]' (FD) to 'nf_10g_interface_0/insti_0/id_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/nf_10g_interface_shared_cpu_regs_inst/axi_bresp_reg[0]' (FDRE) to 'nf_10g_interface_0/insti_0/nf_10g_interface_shared_cpu_regs_inst/axi_bresp_reg[1]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_0/insti_0/nf_10g_interface_shared_cpu_regs_inst/axi_rresp_reg[0]' (FDRE) to 'nf_10g_interface_0/insti_0/nf_10g_interface_shared_cpu_regs_inst/axi_rresp_reg[1]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/interfaceid_reg_reg[0]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[16]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/id_reg_reg[0]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[1]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/interfaceid_reg_reg[1]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[17]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/version_reg_reg[1]' (FD) to 'nf_10g_interface_1/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/id_reg_reg[1]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[2]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/interfaceid_reg_reg[2]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[18]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/version_reg_reg[2]' (FD) to 'nf_10g_interface_1/insti_0/version_reg_reg[31]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/id_reg_reg[2]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[3]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/interfaceid_reg_reg[3]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[19]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/version_reg_reg[3]' (FD) to 'nf_10g_interface_1/insti_0/version_reg_reg[31]'
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/id_reg_reg[3]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[5]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/interfaceid_reg_reg[4]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[20]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/version_reg_reg[4]' (FD) to 'nf_10g_interface_1/insti_0/version_reg_reg[31]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/id_reg_reg[4]' (FDS) to 'nf_10g_interface_1/insti_0/id_reg_reg[8]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/interfaceid_reg_reg[5]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[21]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/version_reg_reg[5]' (FD) to 'nf_10g_interface_1/insti_0/version_reg_reg[31]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/id_reg_reg[5]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[6]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/interfaceid_reg_reg[6]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[22]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/version_reg_reg[6]' (FD) to 'nf_10g_interface_1/insti_0/version_reg_reg[31]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/id_reg_reg[6]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[7]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/interfaceid_reg_reg[7]' (FDR) to 'nf_10g_interface_1/insti_0/id_reg_reg[23]'
|
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INFO: [Synth 8-3886] merging instance 'nf_10g_interface_1/insti_0/version_reg_reg[7]' (FD) to 'nf_10g_interface_1/insti_0/version_reg_reg[31]'
|
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INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
|
|||
|
|
INFO: [Synth 8-3332] Sequential element (inst_blk_mem_gen/gnbram.gaxibmg.axi_blk_mem_gen/valid.cstr/has_mux_b.B/no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]) is unused and will be removed from module blk_mem_gen_v8_4_1__parameterized3.
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4031]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/p_arp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4151]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/p_icmp6_option_link_layer_addr_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4123]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/p_icmp6_na_ns_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4374]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/p_icmp6_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4147]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/p_cpu_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4019]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/p_icmp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3907]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/p_udp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4295]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/p_tcp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3943]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/p_ipv6_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3887]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/p_ipv4_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4171]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ipv4_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4163]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ipv6_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4402]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_tcp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4095]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_udp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3959]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_icmp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4091]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_cpu_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4035]
|
|||
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|
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_icmp6_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4143]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_icmp6_na_ns_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4398]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4255]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_arp_isValid_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4243]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_dma_q_size_1_reg[15:0]' into 'section_start_inst/sume_metadata_dma_q_size_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4207]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_nf3_q_size_1_reg[15:0]' into 'section_start_inst/sume_metadata_nf3_q_size_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3883]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_nf2_q_size_1_reg[15:0]' into 'section_start_inst/sume_metadata_nf2_q_size_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3919]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_nf1_q_size_1_reg[15:0]' into 'section_start_inst/sume_metadata_nf1_q_size_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3923]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_nf0_q_size_1_reg[15:0]' into 'section_start_inst/sume_metadata_nf0_q_size_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3911]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_send_dig_to_cpu_1_reg[7:0]' into 'section_start_inst/sume_metadata_send_dig_to_cpu_1_reg[7:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4382]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_drop_1_reg[7:0]' into 'section_start_inst/sume_metadata_drop_1_reg[7:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4155]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_dst_port_1_reg[7:0]' into 'section_start_inst/sume_metadata_dst_port_1_reg[7:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4283]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_src_port_1_reg[7:0]' into 'section_start_inst/sume_metadata_src_port_1_reg[7:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4259]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_standard_metadata_pkt_len_1_reg[15:0]' into 'section_start_inst/sume_metadata_pkt_len_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4370]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ethernet_isValid_1_reg[0:0]' into 'section_start_inst/p_ethernet_isValid_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4410]
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ethernet_dst_addr_1_reg[47:0]' into 'section_start_inst/p_ethernet_dst_addr_1_reg[47:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3875]
|
|||
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|
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ethernet_src_addr_1_reg[47:0]' into 'section_start_inst/p_ethernet_src_addr_1_reg[47:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3951]
|
|||
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INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_hdr_1_ethernet_ethertype_1_reg[15:0]' into 'section_start_inst/p_ethernet_ethertype_1_reg[15:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3935]
|
|||
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|
INFO: [Synth 8-4471] merging register 'section_start_inst/TopParser_fl_digest_data_1_unused_1_reg[255:0]' into 'section_start_inst/digest_data_unused_1_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4079]
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INFO: [Synth 8-4471] merging register 'section_reject_inst/control_1_reg[20:0]' into 'section_start_inst/control_1_reg[20:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14396]
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INFO: [Synth 8-4471] merging register 'section_reject_inst/control_increment_offsetEop_1_reg[0:0]' into 'section_start_inst/control_nextDone_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14385]
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INFO: [Synth 8-4471] merging register 'section_reject_inst/TopParser_fl_1_reg[1946:0]' into 'section_start_inst/TopParser_fl_1_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14416]
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INFO: [Synth 8-4471] merging register 'TopParser_fl_3_reg[1946:0]' into 'section_start_inst/TopParser_fl_1_reg[1946:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:915]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/control_increment_offsetEop_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4031]
|
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_arp_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4151]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_icmp6_option_link_layer_addr_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4123]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_icmp6_na_ns_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4374]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_icmp6_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4147]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_cpu_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4019]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_icmp_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3907]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_udp_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4295]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_tcp_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3943]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_ipv6_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3887]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/p_ipv4_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4171]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ipv4_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4163]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ipv6_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4402]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_tcp_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4095]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_udp_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3959]
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_icmp_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4091]
|
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_cpu_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4035]
|
|||
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_icmp6_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4143]
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|||
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|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_icmp6_na_ns_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4398]
|
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WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_icmp6_option_link_layer_addr_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4255]
|
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|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_arp_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4243]
|
|||
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|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_dma_q_size_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4207]
|
|||
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|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_nf3_q_size_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3883]
|
|||
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|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_nf2_q_size_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3919]
|
|||
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|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_nf1_q_size_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3923]
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|
|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_nf0_q_size_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3911]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_send_dig_to_cpu_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4382]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_drop_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4155]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_dst_port_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4283]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_src_port_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4259]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_standard_metadata_pkt_len_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4370]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ethernet_isValid_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4410]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ethernet_dst_addr_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3875]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ethernet_src_addr_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3951]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_hdr_1_ethernet_ethertype_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:3935]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_start_inst/TopParser_fl_digest_data_1_unused_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:4079]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_reject_inst/control_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14396]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_reject_inst/control_increment_offsetEop_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14385]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element section_reject_inst/TopParser_fl_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:14416]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element TopParser_fl_3_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:915]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'ErrorCheck_inst/EOP_i1_reg[0:0]' into 'PKT_EOP_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:1076]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element ErrorCheck_inst/EOP_i1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:1076]
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (compute_control_nextSection_inst/term1_reg[3]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (compute_control_nextSection_inst/term1_reg[2]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (compute_control_nextSection_inst/term1_reg[1]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (compute_control_nextSection_inst/term1_reg[0]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_1_reg[8]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_1_reg[7]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_1_reg[6]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_1_reg[5]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_1_reg[3]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offsetEop_1_reg[0]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offset_1_reg[10]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offset_1_reg[9]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offset_1_reg[8]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offset_1_reg[7]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offset_1_reg[6]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offset_1_reg[5]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offset_1_reg[4]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offset_1_reg[3]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offset_1_reg[2]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offset_1_reg[1]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (control_increment_offset_1_reg[0]) is unused and will be removed from module TopParser_t_accept.
|
|||
|
|
INFO: [Synth 8-4471] merging register 'ErrorCheck_inst/EOP_i1_reg[0:0]' into 'PKT_EOP_1_reg[0:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:15508]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element ErrorCheck_inst/EOP_i1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp:15508]
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_control_reg[20]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[15]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[14]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[13]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[12]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[11]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[10]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[9]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[8]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[7]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[6]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[5]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[4]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[3]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[2]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[1]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_local_state_reg[0]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[99]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[98]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[97]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[96]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[95]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[94]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[93]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[92]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[91]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[90]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[89]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[88]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[87]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[86]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[85]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[84]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[83]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[82]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[81]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[80]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[79]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[78]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[77]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[76]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[75]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[74]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[73]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[72]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[71]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[70]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[69]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[68]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[67]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[66]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[65]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[64]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
|
|||
|
|
WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[63]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[62]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[61]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[60]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[59]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[58]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[57]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[56]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[55]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[54]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[53]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[52]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[51]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[50]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[49]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[48]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[47]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[46]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[45]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[44]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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WARNING: [Synth 8-3332] Sequential element (MUX_TUPLE_realmain_v4_networks_0_resp_reg[43]) is unused and will be removed from module TopPipe_lvl_0_t_EngineStage_1.
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INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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INFO: [Synth 8-4471] merging register 'control_increment_offsetEop_1_reg[0:0]' into 'compute_control_nextSection_inst/flag10R_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:894]
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WARNING: [Synth 8-6014] Unused sequential element control_increment_offsetEop_1_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp:894]
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INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
|
|||
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INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
|
|||
|
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INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
|
|||
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|
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
|
|||
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|
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
|
|||
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INFO: [Synth 8-5784] Optimized 5 bits of RAM "RAM/RAM_reg" due to constant propagation. Old ram width 44 bits, new ram width 39 bits.
|
|||
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INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-4471] merging register 'p_3_reg[1402:0]' into 'extract_headers_sec_p_3_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:844]
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|||
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|
INFO: [Synth 8-4471] merging register 'p_4_reg[1402:0]' into 'extract_headers_sec_p_4_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:845]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'p_5_reg[1402:0]' into 'extract_headers_sec_p_5_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:846]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element p_5_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:846]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element p_4_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:845]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element p_3_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:844]
|
|||
|
|
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "empty" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "full" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-5546] ROM "DscFifo_inst/empty" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "DscFifo_inst/full" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_p_3_reg[1402:0]' into 'p_3_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5602]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_p_4_reg[1402:0]' into 'p_4_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5603]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_p_5_reg[1402:0]' into 'p_5_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5604]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_p_6_reg[1402:0]' into 'p_6_reg[1402:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5605]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_user_metadata_3_reg[159:0]' into 'user_metadata_3_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5609]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_user_metadata_4_reg[159:0]' into 'user_metadata_4_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5610]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_user_metadata_5_reg[159:0]' into 'user_metadata_5_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5611]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_user_metadata_6_reg[159:0]' into 'user_metadata_6_reg[159:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5612]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_digest_data_3_reg[255:0]' into 'digest_data_3_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5616]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_digest_data_4_reg[255:0]' into 'digest_data_4_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5617]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_digest_data_5_reg[255:0]' into 'digest_data_5_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5618]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_digest_data_6_reg[255:0]' into 'digest_data_6_reg[255:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5619]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_sume_metadata_3_reg[127:0]' into 'sume_metadata_3_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5623]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_sume_metadata_4_reg[127:0]' into 'sume_metadata_4_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5624]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_sume_metadata_5_reg[127:0]' into 'sume_metadata_5_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5625]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_sume_metadata_6_reg[127:0]' into 'sume_metadata_6_reg[127:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5626]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_TopDeparser_extracts_3_reg[31:0]' into 'TopDeparser_extracts_3_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5630]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_TopDeparser_extracts_4_reg[31:0]' into 'TopDeparser_extracts_4_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5631]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_TopDeparser_extracts_5_reg[31:0]' into 'TopDeparser_extracts_5_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5632]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'act_sec_TopDeparser_extracts_6_reg[31:0]' into 'TopDeparser_extracts_6_reg[31:0]' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5633]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_p_3_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5602]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_p_4_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5603]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_p_5_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5604]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_p_6_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5605]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_user_metadata_3_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5609]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_user_metadata_4_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5610]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_user_metadata_5_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5611]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_user_metadata_6_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5612]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_digest_data_3_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5616]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_digest_data_4_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5617]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_digest_data_5_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5618]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_digest_data_6_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5619]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_sume_metadata_3_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5623]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_sume_metadata_4_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5624]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_sume_metadata_5_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5625]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_sume_metadata_6_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5626]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_TopDeparser_extracts_3_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5630]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_TopDeparser_extracts_4_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5631]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_TopDeparser_extracts_5_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5632]
|
|||
|
|
WARNING: [Synth 8-6014] Unused sequential element act_sec_TopDeparser_extracts_6_reg was removed. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp:5633]
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5784] Optimized 1 bits of RAM "gen_wr_a.gen_word_narrow.mem_reg" due to constant propagation. Old ram width 266 bits, new ram width 265 bits.
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-5775' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-5546] ROM "wack_i" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "S_RESET_clk_control/z8iceu6x6l8iuug6jfho92_74" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "S_RESET_clk_lookup/cm7eal4pxrjzfl5hr_627" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "S_RESET_clk_line/c3tbszppn1ncxo8s896wp4zsbt_455" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power
|
|||
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power
|
|||
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power
|
|||
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power
|
|||
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power
|
|||
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power
|
|||
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power
|
|||
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power
|
|||
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 33 RAM instances of RAM fifo/queue_reg to conserve power
|
|||
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM fifo/queue_reg to conserve power
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
|
|
INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
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INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
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INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
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INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
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INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
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INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
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INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
|||
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INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
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INFO: [Synth 8-5546] ROM "t_code" won't be mapped to RAM because it is too sparse
|
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INFO: [Synth 8-5546] ROM "s_code_c4" won't be mapped to RAM because it is too sparse
|
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INFO: [Synth 8-5546] ROM "s_code_c0" won't be mapped to RAM because it is too sparse
|
|||
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INFO: [Synth 8-5546] ROM "p_0_out" won't be mapped to RAM because it is too sparse
|
|||
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INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
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INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord" is below threshold of ROM address width. It will be mapped to LUTs
|
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INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord0" is below threshold of ROM address width. It will be mapped to LUTs
|
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INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord1" is below threshold of ROM address width. It will be mapped to LUTs
|
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INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord2" is below threshold of ROM address width. It will be mapped to LUTs
|
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INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord3" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
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INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord4" is below threshold of ROM address width. It will be mapped to LUTs
|
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INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord5" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
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INFO: [Synth 8-5587] ROM size for "rx_pcs_i/rx_decoder_i/DecodeWord6" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-4471] merging register 'ieee_registers_i/common_reg_block/reg_1_8_10/re_prev_reg' into 'ieee_registers_i/common_reg_block/reg_1_8_11/re_prev_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/hdl/ten_gig_eth_pcs_pma_v6_0_rfs.v:19478]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'ieee_registers_i/common_reg_block/reg_3_8_10/re_prev_reg' into 'ieee_registers_i/common_reg_block/reg_3_8_11/re_prev_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/hdl/ten_gig_eth_pcs_pma_v6_0_rfs.v:19478]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'ieee_registers_i/common_reg_block/reg_3_33_14/re_prev_reg' into 'ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/hdl/ten_gig_eth_pcs_pma_v6_0_rfs.v:19478]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'ieee_registers_i/common_reg_block/reg_3_33_13_8/re_prev_reg' into 'ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/hdl/ten_gig_eth_pcs_pma_v6_0_rfs.v:19478]
|
|||
|
|
INFO: [Synth 8-4471] merging register 'ieee_registers_i/common_reg_block/reg_3_33_7_0/re_prev_reg' into 'ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_reg' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/hdl/ten_gig_eth_pcs_pma_v6_0_rfs.v:19478]
|
|||
|
|
INFO: [Synth 8-3936] Found unconnected internal register 'drp_ipif_i/synch_1/q_reg' and it is trimmed from '34' to '33' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/hdl/ten_gig_eth_pcs_pma_v6_0_rfs.v:40303]
|
|||
|
|
INFO: [Synth 8-3936] Found unconnected internal register 'drp_ipif_i/synch_1/d_reg_reg' and it is trimmed from '34' to '33' bits. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/hdl/ten_gig_eth_pcs_pma_v6_0_rfs.v:40277]
|
|||
|
|
INFO: [Synth 8-5587] ROM size for "gt_txc_mux" is below threshold of ROM address width. It will be mapped to LUTs
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port is_eval driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port gt_progdiv_reset driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[4] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[3] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[2] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[1] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_minus_1[0] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[4] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[3] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[2] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[1] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_plus_1[0] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[6] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[5] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[4] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[3] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[2] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[1] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port coeff_zero[0] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port txdiffctrl[4] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port txdiffctrl[3] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port txdiffctrl[2] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port txdiffctrl[1] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port txdiffctrl[0] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[15] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[14] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[13] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[12] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[11] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[10] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[9] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[8] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[7] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[6] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[5] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[4] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[3] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[2] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[1] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rddata[0] driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_rdack driven by constant 0
|
|||
|
|
INFO: [Synth 8-3917] design ten_gig_eth_pcs_pma_v6_0_13 has port training_wrack driven by constant 0
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "broadcast_detect" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits.
|
|||
|
|
INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM.
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-5545] ROM "broadcast_frame" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "crc_valid_int" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|||
|
|
INFO: [Synth 8-5545] ROM "broadcast_detect" won't be mapped to RAM because address size (48) is larger than maximum supported(25)
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits.
|
|||
|
|
INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM.
|
|||
|
|
INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits.
|
|||
|
|
INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM.
|
|||
|
|
INFO: [Synth 8-5784] Optimized 104 bits of RAM "axis_fifo_inst/meta_fifo/fifo/queue_reg" due to constant propagation. Old ram width 128 bits, new ram width 24 bits.
|
|||
|
|
INFO: [Synth 8-5583] The signal axis_fifo_inst/meta_fifo/fifo/queue_reg is implemented as block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (5 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM.
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:06:51 ; elapsed = 00:08:04 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 7762 ; free virtual = 10939
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
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INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_7 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_8 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_9 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_10 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_11 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_12 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_13 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_14 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_15 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_16 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_17 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_18 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_19 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_2/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
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|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
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|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_7 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_8 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_9 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_10 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_11 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_12 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_13 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_14 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_15 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_16 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_17 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_18 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_19 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_7 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_8 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_9 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Synth 8-4480] The timing for the instance nf_datapath_0/nf_sume_sdnet_wrapper_1/SimpleSumeSwitch_insti_3/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_1/gen_wr_a.gen_word_narrow.mem_reg_10 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|||
|
|
INFO: [Common 17-14] Message 'Synth 8-4480' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
|
|||
|
|
Report RTL Partitions:
|
|||
|
|
+------+-------------------------------------------+------------+----------+
|
|||
|
|
| |RTL Partition |Replication |Instances |
|
|||
|
|
+------+-------------------------------------------+------------+----------+
|
|||
|
|
|1 |clk_wiz_ip_clk_wiz__GC0 | 1| 13|
|
|||
|
|
|2 |TopParser_t_EngineStage_0__GB0 | 1| 18385|
|
|||
|
|
|3 |TopParser_t_EngineStage_0__GB1 | 1| 24313|
|
|||
|
|
|4 |TopParser_t_EngineStage_0__GB2 | 1| 28664|
|
|||
|
|
|5 |TopParser_t_EngineStage_0__GB3 | 1| 16349|
|
|||
|
|
|6 |TopParser_t_EngineStage_0__GB4 | 1| 7245|
|
|||
|
|
|7 |TopParser_t_EngineStage_1__GB0 | 1| 30971|
|
|||
|
|
|8 |TopParser_t_EngineStage_1__GB1 | 1| 8421|
|
|||
|
|
|9 |TopParser_t_EngineStage_1__GB2 | 1| 10989|
|
|||
|
|
|10 |TopParser_t_EngineStage_1__GB3 | 1| 7788|
|
|||
|
|
|11 |TopParser_t_EngineStage_1__GB4 | 1| 12920|
|
|||
|
|
|12 |TopParser_t_Engine__GC0 | 1| 398|
|
|||
|
|
|13 |TopParser_t__GC0 | 1| 19|
|
|||
|
|
|14 |TopPipe_lvl_0_t_Engine__GB0 | 1| 17590|
|
|||
|
|
|15 |TopPipe_lvl_0_t_Engine__GB1 | 1| 20892|
|
|||
|
|
|16 |TopDeparser_t_EngineStage_0__GB0 | 1| 19222|
|
|||
|
|
|17 |TopDeparser_t_EngineStage_0__GB1 | 1| 3041|
|
|||
|
|
|18 |TopDeparser_t_EngineStage_0__GB2 | 1| 14002|
|
|||
|
|
|19 |reg__1136 | 1| 1403|
|
|||
|
|
|20 |TopDeparser_t_EngineStage_2_Editor__GB0 | 1| 21242|
|
|||
|
|
|21 |TopDeparser_t_EngineStage_2_Editor__GB1 | 1| 6970|
|
|||
|
|
|22 |TopDeparser_t_EngineStage_2__GC0 | 1| 16344|
|
|||
|
|
|23 |TopDeparser_t_Engine__GC0 | 1| 20456|
|
|||
|
|
|24 |TopDeparser_t__GC0 | 1| 21|
|
|||
|
|
|25 |SimpleSumeSwitch__GCB0 | 1| 15736|
|
|||
|
|
|26 |SimpleSumeSwitch__GCB1 | 1| 10691|
|
|||
|
|
|27 |SimpleSumeSwitch__GCB2 | 1| 11420|
|
|||
|
|
|28 |nf_sume_sdnet__GC0 | 1| 11|
|
|||
|
|
|29 |nf_datapath__GCB0 | 1| 14815|
|
|||
|
|
|30 |nf_datapath__GCB1 | 1| 9225|
|
|||
|
|
|31 |bd_a1aa_xpcs_0_shared_clock_and_reset__GC0 | 1| 53|
|
|||
|
|
|32 |ten_gig_eth_pcs_pma_v6_0_13 | 4| 9273|
|
|||
|
|
|33 |bd_a1aa_xpcs_0_block__GC0 | 1| 674|
|
|||
|
|
|34 |bd_a1aa_xpcs_0_support__GC0 | 1| 2|
|
|||
|
|
|35 |bd_a1aa__GC0 | 1| 9790|
|
|||
|
|
|36 |nf_10g_interface_shared_block__GC0 | 1| 7932|
|
|||
|
|
|37 |nf_10g_interface_shared__GC0 | 1| 1851|
|
|||
|
|
|38 |bd_7ad4_xmac_0_block | 3| 9790|
|
|||
|
|
|39 |bd_7ad4_xpcs_0_block__GC0 | 3| 674|
|
|||
|
|
|40 |nf_10g_interface_block__xdcDup__1__GC0 | 1| 7932|
|
|||
|
|
|41 |nf_10g_interface__xdcDup__1__GC0 | 1| 1789|
|
|||
|
|
|42 |nf_10g_interface_block__xdcDup__2__GC0 | 1| 7932|
|
|||
|
|
|43 |nf_10g_interface__xdcDup__2__GC0 | 1| 1789|
|
|||
|
|
|44 |nf_10g_interface_block__GC0 | 1| 7932|
|
|||
|
|
|45 |nf_10g_interface__GC0 | 1| 1789|
|
|||
|
|
|46 |top__GC0 | 1| 7748|
|
|||
|
|
+------+-------------------------------------------+------------+----------+
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Applying XDC Timing Constraints
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/clk_wiz_1/clk_out1' to pin 'control_sub_i/nf_mbsys/clk_wiz_1/bbstub_clk_out1/O'
|
|||
|
|
INFO: [Synth 8-5783] Moving clock source from hierarchical pin 'control_sub_i/nf_mbsys/clk_wiz_1/clk_in1' to 'axi_lite_bufg0/I'
|
|||
|
|
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/Dbg_Clk_0' to pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/bbstub_Dbg_Clk_0/O'
|
|||
|
|
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/Dbg_Update_0' to pin 'control_sub_i/nf_mbsys/mbsys/mdm_1/bbstub_Dbg_Update_0/O'
|
|||
|
|
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr/BRAM_Clk_A' to pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr/bbstub_BRAM_Clk_A/O'
|
|||
|
|
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr/BRAM_Clk_A' to pin 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr/bbstub_BRAM_Clk_A/O'
|
|||
|
|
INFO: [Synth 8-5578] Moved timing constraint from pin 'control_sub_i/dma_sub/pcie3_7x_1/user_clk' to pin 'control_sub_i/dma_sub/pcie3_7x_1/bbstub_user_clk/O'
|
|||
|
|
WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 75 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:75]
|
|||
|
|
WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 75 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:75]
|
|||
|
|
WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 75 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc:75]
|
|||
|
|
WARNING: [Synth 8-3321] set_false_path : Empty from list for constraint at line 76 of /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc:76]
|
|||
|
|
INFO: [Synth 8-5578] Moved timing constraint from pin 'axi_clocking_i/clk_wiz_i/inst/clk_in1' to pin 'axi_clocking_i/clkin1_buf/O'
|
|||
|
|
INFO: [Synth 8-5578] Moved timing constraint from pin 'axi_clocking_i/clk_wiz_i/clk_out1' to pin 'clkout1_buf/O'
|
|||
|
|
WARNING: [Synth 8-565] redefining clock 'xphy_refclk_p'
|
|||
|
|
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK'
|
|||
|
|
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK'
|
|||
|
|
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK'
|
|||
|
|
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK'
|
|||
|
|
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK'
|
|||
|
|
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK'
|
|||
|
|
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK'
|
|||
|
|
WARNING: [Synth 8-565] redefining clock 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK'
|
|||
|
|
INFO: [Synth 8-5819] Moved 9 constraints on hierarchical pins to their respective driving/loading pins
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:07:24 ; elapsed = 00:08:39 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 7247 ; free virtual = 10604
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Timing Optimization
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Timing Optimization : Time (s): cpu = 00:08:13 ; elapsed = 00:09:30 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 7273 ; free virtual = 10620
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
Report RTL Partitions:
|
|||
|
|
+------+-------------------------------------------+------------+----------+
|
|||
|
|
| |RTL Partition |Replication |Instances |
|
|||
|
|
+------+-------------------------------------------+------------+----------+
|
|||
|
|
|1 |clk_wiz_ip_clk_wiz__GC0 | 1| 13|
|
|||
|
|
|2 |TopParser_t_EngineStage_0__GB0 | 1| 623|
|
|||
|
|
|3 |TopParser_t_EngineStage_0__GB1 | 1| 279|
|
|||
|
|
|4 |TopParser_t_EngineStage_0__GB2 | 1| 113|
|
|||
|
|
|5 |TopParser_t_EngineStage_0__GB3 | 1| 1685|
|
|||
|
|
|6 |TopParser_t_EngineStage_0__GB4 | 1| 5325|
|
|||
|
|
|7 |TopParser_t_EngineStage_1__GB0 | 1| 725|
|
|||
|
|
|8 |TopParser_t_EngineStage_1__GB1 | 1| 679|
|
|||
|
|
|9 |TopParser_t_EngineStage_1__GB2 | 1| 844|
|
|||
|
|
|10 |TopParser_t_EngineStage_1__GB4 | 1| 4660|
|
|||
|
|
|11 |TopParser_t_Engine__GC0 | 1| 398|
|
|||
|
|
|12 |TopParser_t__GC0 | 1| 17|
|
|||
|
|
|13 |TopPipe_lvl_0_t_Engine__GB0 | 1| 15446|
|
|||
|
|
|14 |TopPipe_lvl_0_t_Engine__GB1 | 1| 8198|
|
|||
|
|
|15 |TopDeparser_t_EngineStage_0__GB0 | 1| 17397|
|
|||
|
|
|16 |TopDeparser_t_EngineStage_0__GB1 | 1| 2465|
|
|||
|
|
|17 |TopDeparser_t_EngineStage_0__GB2 | 1| 2329|
|
|||
|
|
|18 |reg__1136 | 1| 179|
|
|||
|
|
|19 |TopDeparser_t_EngineStage_2_Editor__GB0 | 1| 18952|
|
|||
|
|
|20 |TopDeparser_t_EngineStage_2_Editor__GB1 | 1| 6932|
|
|||
|
|
|21 |TopDeparser_t_EngineStage_2__GC0 | 1| 5951|
|
|||
|
|
|22 |TopDeparser_t_Engine__GC0 | 1| 7496|
|
|||
|
|
|23 |TopDeparser_t__GC0 | 1| 3|
|
|||
|
|
|24 |SimpleSumeSwitch__GCB0 | 1| 15734|
|
|||
|
|
|25 |SimpleSumeSwitch__GCB1 | 1| 10691|
|
|||
|
|
|26 |SimpleSumeSwitch__GCB2 | 1| 11301|
|
|||
|
|
|27 |nf_sume_sdnet__GC0 | 1| 11|
|
|||
|
|
|28 |nf_datapath__GCB0 | 1| 14808|
|
|||
|
|
|29 |nf_datapath__GCB1 | 1| 9225|
|
|||
|
|
|30 |bd_a1aa_xpcs_0_shared_clock_and_reset__GC0 | 1| 53|
|
|||
|
|
|31 |ten_gig_eth_pcs_pma_v6_0_13 | 4| 9273|
|
|||
|
|
|32 |bd_a1aa_xpcs_0_block__GC0 | 1| 674|
|
|||
|
|
|33 |bd_a1aa_xpcs_0_support__GC0 | 1| 2|
|
|||
|
|
|34 |bd_a1aa__GC0 | 1| 9790|
|
|||
|
|
|35 |nf_10g_interface_shared_block__GC0 | 1| 7932|
|
|||
|
|
|36 |nf_10g_interface_shared__GC0 | 1| 1851|
|
|||
|
|
|37 |bd_7ad4_xmac_0_block | 3| 9790|
|
|||
|
|
|38 |bd_7ad4_xpcs_0_block__GC0 | 3| 674|
|
|||
|
|
|39 |nf_10g_interface_block__xdcDup__1__GC0 | 1| 7932|
|
|||
|
|
|40 |nf_10g_interface__xdcDup__1__GC0 | 1| 1789|
|
|||
|
|
|41 |nf_10g_interface_block__xdcDup__2__GC0 | 1| 7932|
|
|||
|
|
|42 |nf_10g_interface__xdcDup__2__GC0 | 1| 1789|
|
|||
|
|
|43 |nf_10g_interface_block__GC0 | 1| 7932|
|
|||
|
|
|44 |nf_10g_interface__GC0 | 1| 1789|
|
|||
|
|
|45 |top__GC0 | 1| 7748|
|
|||
|
|
+------+-------------------------------------------+------------+----------+
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Technology Mapping
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Warning: Parallel synthesis criteria is not met
|
|||
|
|
INFO: [Synth 8-4765] Removing register instance (\S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/rd_en_d1_reg ) from module (SimpleSumeSwitch__GCB2) as it is equivalent to (\S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/rd_en_d1_reg__0 ) and driving same net [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request.v:89]
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Technology Mapping : Time (s): cpu = 00:09:16 ; elapsed = 00:10:35 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 7332 ; free virtual = 10672
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
Report RTL Partitions:
|
|||
|
|
+-+--------------+------------+----------+
|
|||
|
|
| |RTL Partition |Replication |Instances |
|
|||
|
|
+-+--------------+------------+----------+
|
|||
|
|
+-+--------------+------------+----------+
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start IO Insertion
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Flattening Before IO Insertion
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Flattening Before IO Insertion
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Final Netlist Cleanup
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-5365] Flop stage_0/ErrorCheck_inst/validBits_i1_reg[10] is being inverted and renamed to stage_0/ErrorCheck_inst/validBits_i1_reg[10]_inv.
|
|||
|
|
INFO: [Synth 8-5365] Flop stage_0/ErrorCheck_inst/validBits_i1_reg[10] is being inverted and renamed to stage_0/ErrorCheck_inst/validBits_i1_reg[10]_inv.
|
|||
|
|
INFO: [Synth 8-5365] Flop inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT______TopDeparser_BACKPRESSURE_3_reg is being inverted and renamed to inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT______TopDeparser_BACKPRESSURE_3_reg_inv.
|
|||
|
|
INFO: [Synth 8-6064] Net \inst/wr_en [4] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver.
|
|||
|
|
INFO: [Synth 8-6064] Net \inst/wr_en [3] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver.
|
|||
|
|
INFO: [Synth 8-6064] Net \inst/wr_en [2] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver.
|
|||
|
|
INFO: [Synth 8-6064] Net \inst/wr_en [1] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver.
|
|||
|
|
INFO: [Synth 8-6064] Net \inst/wr_en [0] is driving 130 big block pins (URAM, BRAM and DSP loads). Created 13 replicas of its driver.
|
|||
|
|
INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 is sub-optimal because some of its loads are not in same hierarchy as its driver
|
|||
|
|
INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas.
|
|||
|
|
INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 is sub-optimal because some of its loads are not in same hierarchy as its driver
|
|||
|
|
INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas.
|
|||
|
|
INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 is sub-optimal because some of its loads are not in same hierarchy as its driver
|
|||
|
|
INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas.
|
|||
|
|
INFO: [Synth 8-5778] max_fanout handling on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 is sub-optimal because some of its loads are not in same hierarchy as its driver
|
|||
|
|
INFO: [Synth 8-4618] Found max_fanout attribute set to 50 on net \ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 . Fanout reduced from 697 to 155 by creating 11 replicas.
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Final Netlist Cleanup
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin m_axis_rx_tready_inferred:in0 to constant 0
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin m_axis_rx_tready_inferred:in0 to constant 0
|
|||
|
|
WARNING: [Synth 8-3295] tying undriven pin m_axis_rx_tready_inferred:in0 to constant 0
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished IO Insertion : Time (s): cpu = 00:09:22 ; elapsed = 00:10:42 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 7331 ; free virtual = 10671
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
Report Check Netlist:
|
|||
|
|
+------+------------------+-------+---------+-------+------------------+
|
|||
|
|
| |Item |Errors |Warnings |Status |Description |
|
|||
|
|
+------+------------------+-------+---------+-------+------------------+
|
|||
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
|||
|
|
+------+------------------+-------+---------+-------+------------------+
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Renaming Generated Instances
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:09:23 ; elapsed = 00:10:42 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 7334 ; free virtual = 10674
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
Report RTL Partitions:
|
|||
|
|
+-+--------------+------------+----------+
|
|||
|
|
| |RTL Partition |Replication |Instances |
|
|||
|
|
+-+--------------+------------+----------+
|
|||
|
|
+-+--------------+------------+----------+
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Rebuilding User Hierarchy
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:09:36 ; elapsed = 00:10:56 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 7322 ; free virtual = 10662
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Renaming Generated Ports
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:09:37 ; elapsed = 00:10:57 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 7322 ; free virtual = 10662
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Handling Custom Attributes
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:09:42 ; elapsed = 00:11:02 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 7309 ; free virtual = 10650
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Renaming Generated Nets
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:09:42 ; elapsed = 00:11:03 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 7309 ; free virtual = 10649
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Writing Synthesis Report
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
Report BlackBoxes:
|
|||
|
|
+------+------------------------------------+----------+
|
|||
|
|
| |BlackBox name |Instances |
|
|||
|
|
+------+------------------------------------+----------+
|
|||
|
|
|1 |control_sub_xbar_0 | 1|
|
|||
|
|
|2 |control_sub_m00_data_fifo_0 | 1|
|
|||
|
|
|3 |control_sub_m01_data_fifo_0 | 1|
|
|||
|
|
|4 |control_sub_m02_data_fifo_0 | 1|
|
|||
|
|
|5 |control_sub_m03_data_fifo_0 | 1|
|
|||
|
|
|6 |control_sub_m04_data_fifo_0 | 1|
|
|||
|
|
|7 |control_sub_m05_data_fifo_0 | 1|
|
|||
|
|
|8 |control_sub_m06_data_fifo_0 | 1|
|
|||
|
|
|9 |control_sub_m07_data_fifo_0 | 1|
|
|||
|
|
|10 |control_sub_m08_data_fifo_0 | 1|
|
|||
|
|
|11 |control_sub_auto_cc_0 | 1|
|
|||
|
|
|12 |control_sub_s00_data_fifo_0 | 1|
|
|||
|
|
|13 |control_sub_axi_clock_converter_0_0 | 1|
|
|||
|
|
|14 |control_sub_axis_dwidth_dma_rx_0 | 1|
|
|||
|
|
|15 |control_sub_axis_dwidth_dma_tx_0 | 1|
|
|||
|
|
|16 |control_sub_axis_fifo_10g_rx_0 | 1|
|
|||
|
|
|17 |control_sub_axis_fifo_10g_tx_0 | 1|
|
|||
|
|
|18 |control_sub_nf_riffa_dma_1_0 | 1|
|
|||
|
|
|19 |control_sub_pcie3_7x_1_0 | 1|
|
|||
|
|
|20 |control_sub_pcie_reset_inv_0 | 1|
|
|||
|
|
|21 |control_sub_axi_iic_0_0 | 1|
|
|||
|
|
|22 |control_sub_axi_uartlite_0_0 | 1|
|
|||
|
|
|23 |control_sub_clk_wiz_1_0 | 1|
|
|||
|
|
|24 |control_sub_xbar_1 | 1|
|
|||
|
|
|25 |control_sub_mdm_1_0 | 1|
|
|||
|
|
|26 |control_sub_microblaze_0_0 | 1|
|
|||
|
|
|27 |control_sub_microblaze_0_axi_intc_0 | 1|
|
|||
|
|
|28 |control_sub_microblaze_0_xlconcat_0 | 1|
|
|||
|
|
|29 |control_sub_rst_clk_wiz_1_100M_0 | 1|
|
|||
|
|
|30 |control_sub_dlmb_bram_if_cntlr_0 | 1|
|
|||
|
|
|31 |control_sub_dlmb_v10_0 | 1|
|
|||
|
|
|32 |control_sub_ilmb_bram_if_cntlr_0 | 1|
|
|||
|
|
|33 |control_sub_ilmb_v10_0 | 1|
|
|||
|
|
|34 |control_sub_lmb_bram_0 | 1|
|
|||
|
|
+------+------------------------------------+----------+
|
|||
|
|
|
|||
|
|
Report Cell Usage:
|
|||
|
|
+------+------------------------------------+------+
|
|||
|
|
| |Cell |Count |
|
|||
|
|
+------+------------------------------------+------+
|
|||
|
|
|1 |control_sub_auto_cc_0 | 1|
|
|||
|
|
|2 |control_sub_axi_clock_converter_0_0 | 1|
|
|||
|
|
|3 |control_sub_axi_iic_0_0 | 1|
|
|||
|
|
|4 |control_sub_axi_uartlite_0_0 | 1|
|
|||
|
|
|5 |control_sub_axis_dwidth_dma_rx_0 | 1|
|
|||
|
|
|6 |control_sub_axis_dwidth_dma_tx_0 | 1|
|
|||
|
|
|7 |control_sub_axis_fifo_10g_rx_0 | 1|
|
|||
|
|
|8 |control_sub_axis_fifo_10g_tx_0 | 1|
|
|||
|
|
|9 |control_sub_clk_wiz_1_0 | 1|
|
|||
|
|
|10 |control_sub_dlmb_bram_if_cntlr_0 | 1|
|
|||
|
|
|11 |control_sub_dlmb_v10_0 | 1|
|
|||
|
|
|12 |control_sub_ilmb_bram_if_cntlr_0 | 1|
|
|||
|
|
|13 |control_sub_ilmb_v10_0 | 1|
|
|||
|
|
|14 |control_sub_lmb_bram_0 | 1|
|
|||
|
|
|15 |control_sub_m00_data_fifo_0 | 1|
|
|||
|
|
|16 |control_sub_m01_data_fifo_0 | 1|
|
|||
|
|
|17 |control_sub_m02_data_fifo_0 | 1|
|
|||
|
|
|18 |control_sub_m03_data_fifo_0 | 1|
|
|||
|
|
|19 |control_sub_m04_data_fifo_0 | 1|
|
|||
|
|
|20 |control_sub_m05_data_fifo_0 | 1|
|
|||
|
|
|21 |control_sub_m06_data_fifo_0 | 1|
|
|||
|
|
|22 |control_sub_m07_data_fifo_0 | 1|
|
|||
|
|
|23 |control_sub_m08_data_fifo_0 | 1|
|
|||
|
|
|24 |control_sub_mdm_1_0 | 1|
|
|||
|
|
|25 |control_sub_microblaze_0_0 | 1|
|
|||
|
|
|26 |control_sub_microblaze_0_axi_intc_0 | 1|
|
|||
|
|
|27 |control_sub_microblaze_0_xlconcat_0 | 1|
|
|||
|
|
|28 |control_sub_nf_riffa_dma_1_0 | 1|
|
|||
|
|
|29 |control_sub_pcie3_7x_1_0 | 1|
|
|||
|
|
|30 |control_sub_pcie_reset_inv_0 | 1|
|
|||
|
|
|31 |control_sub_rst_clk_wiz_1_100M_0 | 1|
|
|||
|
|
|32 |control_sub_s00_data_fifo_0 | 1|
|
|||
|
|
|33 |control_sub_xbar_0 | 1|
|
|||
|
|
|34 |control_sub_xbar_1 | 1|
|
|||
|
|
|35 |BUFG | 4|
|
|||
|
|
|36 |BUFGCE | 1|
|
|||
|
|
|37 |BUFH | 5|
|
|||
|
|
|38 |CARRY4 | 1580|
|
|||
|
|
|39 |FIFO36E1 | 4|
|
|||
|
|
|40 |FIFO36E1_1 | 4|
|
|||
|
|
|41 |GTHE2_CHANNEL | 4|
|
|||
|
|
|42 |GTHE2_COMMON | 1|
|
|||
|
|
|43 |IBUFDS_GTE2 | 2|
|
|||
|
|
|44 |LUT1 | 1505|
|
|||
|
|
|45 |LUT2 | 6731|
|
|||
|
|
|46 |LUT3 | 15904|
|
|||
|
|
|47 |LUT4 | 7664|
|
|||
|
|
|48 |LUT5 | 6980|
|
|||
|
|
|49 |LUT6 | 20346|
|
|||
|
|
|50 |MMCME2_ADV | 1|
|
|||
|
|
|51 |MUXCY_L | 176|
|
|||
|
|
|52 |MUXF7 | 343|
|
|||
|
|
|53 |MUXF8 | 1|
|
|||
|
|
|54 |RAM128X1D | 20|
|
|||
|
|
|55 |RAM32M | 192|
|
|||
|
|
|56 |RAM64M | 236|
|
|||
|
|
|57 |RAM64X1D | 60|
|
|||
|
|
|58 |RAMB18E1 | 9|
|
|||
|
|
|59 |RAMB18E1_1 | 5|
|
|||
|
|
|60 |RAMB18E1_2 | 5|
|
|||
|
|
|61 |RAMB18E1_3 | 12|
|
|||
|
|
|62 |RAMB18E1_4 | 20|
|
|||
|
|
|63 |RAMB36E1_1 | 110|
|
|||
|
|
|64 |RAMB36E1_10 | 1|
|
|||
|
|
|65 |RAMB36E1_11 | 28|
|
|||
|
|
|66 |RAMB36E1_2 | 20|
|
|||
|
|
|67 |RAMB36E1_3 | 160|
|
|||
|
|
|68 |RAMB36E1_4 | 35|
|
|||
|
|
|69 |RAMB36E1_5 | 86|
|
|||
|
|
|70 |RAMB36E1_6 | 24|
|
|||
|
|
|71 |RAMB36E1_7 | 1|
|
|||
|
|
|72 |RAMB36E1_8 | 1|
|
|||
|
|
|73 |RAMB36E1_9 | 1|
|
|||
|
|
|74 |SRL16 | 1|
|
|||
|
|
|75 |SRL16E | 3607|
|
|||
|
|
|76 |FDCE | 74|
|
|||
|
|
|77 |FDPE | 318|
|
|||
|
|
|78 |FDR | 8|
|
|||
|
|
|79 |FDRE | 93418|
|
|||
|
|
|80 |FDSE | 1956|
|
|||
|
|
|81 |LDCE | 4|
|
|||
|
|
|82 |IBUF | 27|
|
|||
|
|
|83 |IBUFDS | 1|
|
|||
|
|
|84 |IOBUF | 2|
|
|||
|
|
|85 |OBUF | 33|
|
|||
|
|
+------+------------------------------------+------+
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:09:42 ; elapsed = 00:11:03 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 7309 ; free virtual = 10649
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Synthesis finished with 0 errors, 0 critical warnings and 30123 warnings.
|
|||
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:07:31 ; elapsed = 00:08:41 . Memory (MB): peak = 3891.996 ; gain = 915.746 ; free physical = 10245 ; free virtual = 13585
|
|||
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:09:43 ; elapsed = 00:11:06 . Memory (MB): peak = 3891.996 ; gain = 2567.504 ; free physical = 10257 ; free virtual = 13583
|
|||
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
|||
|
|
INFO: [Netlist 29-17] Analyzing 3175 Unisim elements for replacement
|
|||
|
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|||
|
|
WARNING: [Opt 31-35] Removing redundant IBUF, axi_clocking_i/clk_wiz_i/inst/clkin1_ibufg, from the path connected to top-level port: fpga_sysclk_p
|
|||
|
|
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
|
|||
|
|
INFO: [Opt 31-140] Inserted 8 IBUFs to IO ports without IO buffers.
|
|||
|
|
INFO: [Opt 31-141] Inserted 8 OBUFs to IO ports without IO buffers.
|
|||
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|||
|
|
A total of 584 instances were transformed.
|
|||
|
|
(MUXCY,XORCY) => CARRY4: 64 instances
|
|||
|
|
BUFGCE => BUFGCTRL: 1 instances
|
|||
|
|
FDR => FDRE: 8 instances
|
|||
|
|
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
|
|||
|
|
RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 20 instances
|
|||
|
|
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 192 instances
|
|||
|
|
RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 236 instances
|
|||
|
|
RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 60 instances
|
|||
|
|
SRL16 => SRL16E: 1 instances
|
|||
|
|
|
|||
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
|||
|
|
1703 Infos, 746 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
synth_design completed successfully
|
|||
|
|
synth_design: Time (s): cpu = 00:10:11 ; elapsed = 00:11:33 . Memory (MB): peak = 3908.004 ; gain = 2583.512 ; free physical = 10236 ; free virtual = 13562
|
|||
|
|
WARNING: [Constraints 18-5210] No constraint will be written out.
|
|||
|
|
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/top.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 3932.016 ; gain = 24.012 ; free physical = 10207 ; free virtual = 13563
|
|||
|
|
INFO: [runtcl-4] Executing : report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb
|
|||
|
|
report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 3932.016 ; gain = 0.000 ; free physical = 10205 ; free virtual = 13561
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 28 18:01:48 2019...
|
|||
|
|
[Sun Jul 28 18:01:48 2019] synth finished
|
|||
|
|
wait_on_run: Time (s): cpu = 00:37:04 ; elapsed = 00:57:59 . Memory (MB): peak = 2872.812 ; gain = 0.000 ; free physical = 12292 ; free virtual = 15231
|
|||
|
|
# launch_runs impl_1 -to_step write_bitstream
|
|||
|
|
[Sun Jul 28 18:01:50 2019] Launched synth_1...
|
|||
|
|
Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth_1/runme.log
|
|||
|
|
[Sun Jul 28 18:01:50 2019] Launched impl_1...
|
|||
|
|
Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/runme.log
|
|||
|
|
# wait_on_run impl_1
|
|||
|
|
[Sun Jul 28 18:01:50 2019] Waiting for impl_1 to finish...
|
|||
|
|
|
|||
|
|
*** Running vivado
|
|||
|
|
with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace
|
|||
|
|
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source top.tcl -notrace
|
|||
|
|
Command: link_design -top top -part xc7vx690tffg1761-3
|
|||
|
|
Design is defaulting to srcset: sources_1
|
|||
|
|
Design is defaulting to constrset: constrs_1
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0.dcp' for cell 'control_sub_i/dma_sub/axi_clock_converter_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0.dcp' for cell 'control_sub_i/dma_sub/nf_riffa_dma_1'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0.dcp' for cell 'control_sub_i/dma_sub/pcie3_7x_1'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0.dcp' for cell 'control_sub_i/dma_sub/pcie_reset_inv'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_iic_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_uartlite_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.dcp' for cell 'control_sub_i/nf_mbsys/clk_wiz_1'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram'
|
|||
|
|
INFO: [Netlist 29-17] Analyzing 4601 Unisim elements for replacement
|
|||
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|||
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
|
|||
|
|
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
|
|||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0'
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INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc:50]
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get_clocks: Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 3282.309 ; gain = 924.016 ; free physical = 10163 ; free virtual = 13165
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst'
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INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc:124]
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst'
|
|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
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|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
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INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc:57]
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
|
|||
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'xphy_refclk_p' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:92]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:114]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:115]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:116]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:117]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:118]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:119]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:120]
|
|||
|
|
WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:121]
|
|||
|
|
INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:149]
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
|
|||
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
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|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
|
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
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|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
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|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
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|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
INFO: [Common 17-14] Message 'Vivado 12-3272' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
INFO: [Common 17-14] Message 'XPM_CDC_GRAY: TCL 1000' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
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|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
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|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
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Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
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|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
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|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
|
|||
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|||
|
|
Generating merged BMM file for the design top 'top'...
|
|||
|
|
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/data/mb_bootloop_le.elf
|
|||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|||
|
|
A total of 808 instances were transformed.
|
|||
|
|
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
|
|||
|
|
LUT6_2 => LUT6_2 (LUT5, LUT6): 80 instances
|
|||
|
|
RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 20 instances
|
|||
|
|
RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
|
|||
|
|
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 367 instances
|
|||
|
|
RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances
|
|||
|
|
RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 245 instances
|
|||
|
|
RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 60 instances
|
|||
|
|
|
|||
|
|
148 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
link_design completed successfully
|
|||
|
|
link_design: Time (s): cpu = 00:01:57 ; elapsed = 00:02:35 . Memory (MB): peak = 4282.207 ; gain = 2957.805 ; free physical = 10254 ; free virtual = 13258
|
|||
|
|
Command: opt_design
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
Running DRC as a precondition to command opt_design
|
|||
|
|
|
|||
|
|
Starting DRC Task
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
INFO: [Project 1-461] DRC finished with 0 Errors
|
|||
|
|
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10250 ; free virtual = 13254
|
|||
|
|
|
|||
|
|
Starting Cache Timing Information Task
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
Ending Cache Timing Information Task | Checksum: 198abdbdc
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:14 ; elapsed = 00:00:05 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10063 ; free virtual = 13067
|
|||
|
|
|
|||
|
|
Starting Logic Optimization Task
|
|||
|
|
|
|||
|
|
Phase 1 Retarget
|
|||
|
|
INFO: [Opt 31-138] Pushed 24 inverter(s) to 93 load pin(s).
|
|||
|
|
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
|||
|
|
Phase 1 Retarget | Checksum: 182ab964f
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10243 ; free virtual = 13247
|
|||
|
|
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
|||
|
|
|
|||
|
|
Phase 2 Constant propagation
|
|||
|
|
INFO: [Opt 31-138] Pushed 17 inverter(s) to 49 load pin(s).
|
|||
|
|
Phase 2 Constant propagation | Checksum: 1654929bf
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:26 ; elapsed = 00:00:18 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10243 ; free virtual = 13247
|
|||
|
|
INFO: [Opt 31-389] Phase Constant propagation created 1234 cells and removed 2976 cells
|
|||
|
|
|
|||
|
|
Phase 3 Sweep
|
|||
|
|
Phase 3 Sweep | Checksum: 1ac460825
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:33 ; elapsed = 00:01:25 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10247 ; free virtual = 13251
|
|||
|
|
INFO: [Opt 31-389] Phase Sweep created 9 cells and removed 31795 cells
|
|||
|
|
|
|||
|
|
Phase 4 BUFG optimization
|
|||
|
|
Phase 4 BUFG optimization | Checksum: 19b194d70
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:35 ; elapsed = 00:01:27 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10246 ; free virtual = 13250
|
|||
|
|
INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 2 cells.
|
|||
|
|
|
|||
|
|
Phase 5 Shift Register Optimization
|
|||
|
|
Phase 5 Shift Register Optimization | Checksum: 17315a67a
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:41 ; elapsed = 00:01:33 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10250 ; free virtual = 13255
|
|||
|
|
INFO: [Opt 31-389] Phase Shift Register Optimization created 1 cells and removed 0 cells
|
|||
|
|
|
|||
|
|
Phase 6 Post Processing Netlist
|
|||
|
|
Phase 6 Post Processing Netlist | Checksum: 18e7a450b
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:44 ; elapsed = 00:01:36 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10249 ; free virtual = 13254
|
|||
|
|
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 20 cells
|
|||
|
|
|
|||
|
|
Starting Connectivity Check Task
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.31 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10249 ; free virtual = 13254
|
|||
|
|
Ending Logic Optimization Task | Checksum: 1c7fc2267
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:45 ; elapsed = 00:01:37 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10251 ; free virtual = 13255
|
|||
|
|
|
|||
|
|
Starting Power Optimization Task
|
|||
|
|
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
|||
|
|
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.163 | TNS=0.000 |
|
|||
|
|
Running Vector-less Activity Propagation...
|
|||
|
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|
|||
|
|
Finished Running Vector-less Activity Propagation
|
|||
|
|
|
|||
|
|
|
|||
|
|
Starting PowerOpt Patch Enables Task
|
|||
|
|
INFO: [Pwropt 34-162] WRITE_MODE attribute of 1 BRAM(s) out of a total of 486 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
|||
|
|
INFO: [Pwropt 34-201] Structural ODC has moved 18 WE to EN ports
|
|||
|
|
Number of BRAM Ports augmented: 110 newly gated: 100 Total Ports: 972
|
|||
|
|
Ending PowerOpt Patch Enables Task | Checksum: 98fba02d
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9983 ; free virtual = 12991
|
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|
Ending Power Optimization Task | Checksum: 98fba02d
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:24 ; elapsed = 00:00:57 . Memory (MB): peak = 5080.711 ; gain = 798.504 ; free physical = 10167 ; free virtual = 13175
|
|||
|
|
|
|||
|
|
Starting Final Cleanup Task
|
|||
|
|
|
|||
|
|
Starting Logic Optimization Task
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
Ending Logic Optimization Task | Checksum: 11bfdf046
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10174 ; free virtual = 13183
|
|||
|
|
Ending Final Cleanup Task | Checksum: 11bfdf046
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10174 ; free virtual = 13183
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
171 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
opt_design completed successfully
|
|||
|
|
opt_design: Time (s): cpu = 00:04:52 ; elapsed = 00:02:55 . Memory (MB): peak = 5080.711 ; gain = 798.504 ; free physical = 10174 ; free virtual = 13183
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Writing placer database...
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Write XDEF Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.11 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10150 ; free virtual = 13166
|
|||
|
|
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_opt.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:46 ; elapsed = 00:00:40 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10129 ; free virtual = 13174
|
|||
|
|
INFO: [runtcl-4] Executing : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
|
|||
|
|
Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_opted.rpt.
|
|||
|
|
report_drc completed successfully
|
|||
|
|
report_drc: Time (s): cpu = 00:00:20 ; elapsed = 00:00:10 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10103 ; free virtual = 13149
|
|||
|
|
Command: place_design -directive Explore
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
|||
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
Running DRC as a precondition to command place_design
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
|
|||
|
|
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/ENBWREN (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[0] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[1] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[2] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings
|
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|
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
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|
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Starting Placer Task
|
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INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.
|
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
|
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|
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Phase 1 Placer Initialization
|
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|
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Phase 1.1 Placer Initialization Netlist Sorting
|
|||
|
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Netlist sorting complete. Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10101 ; free virtual = 13147
|
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9ff384e5
|
|||
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|
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|
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Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.27 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10100 ; free virtual = 13147
|
|||
|
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INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|||
|
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Netlist sorting complete. Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.20 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10094 ; free virtual = 13141
|
|||
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|
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
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|
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INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
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WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
|
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
|
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
|
WARNING: [Place 30-139] Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
|||
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|
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|
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control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23
|
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|
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control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
|
|||
|
|
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: bac26f65
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:57 ; elapsed = 00:00:30 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9889 ; free virtual = 12940
|
|||
|
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|
|||
|
|
Phase 1.3 Build Placer Netlist Model
|
|||
|
|
Phase 1.3 Build Placer Netlist Model | Checksum: 19b30d1ca
|
|||
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|
|||
|
|
Time (s): cpu = 00:02:01 ; elapsed = 00:00:56 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9594 ; free virtual = 12645
|
|||
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|
|||
|
|
Phase 1.4 Constrain Clocks/Macros
|
|||
|
|
Phase 1.4 Constrain Clocks/Macros | Checksum: 19b30d1ca
|
|||
|
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|
|||
|
|
Time (s): cpu = 00:02:02 ; elapsed = 00:00:57 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9594 ; free virtual = 12645
|
|||
|
|
Phase 1 Placer Initialization | Checksum: 19b30d1ca
|
|||
|
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|
|||
|
|
Time (s): cpu = 00:02:02 ; elapsed = 00:00:57 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9593 ; free virtual = 12644
|
|||
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|
|||
|
|
Phase 2 Global Placement
|
|||
|
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|
|||
|
|
Phase 2.1 Floorplanning
|
|||
|
|
Phase 2.1 Floorplanning | Checksum: c6d613c2
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:35 ; elapsed = 00:01:08 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9490 ; free virtual = 12541
|
|||
|
|
|
|||
|
|
Phase 2.2 Physical Synthesis In Placer
|
|||
|
|
WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins.
|
|||
|
|
INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization.
|
|||
|
|
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_reset_i/cpllreset. Replicated 13 times.
|
|||
|
|
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/SS[0]. Replicated 11 times.
|
|||
|
|
WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins.
|
|||
|
|
INFO: [Physopt 32-232] Optimized 2 nets. Created 24 new instances.
|
|||
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 24 new cells, deleted 0 existing cell and moved 0 existing cell
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.29 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9407 ; free virtual = 12460
|
|||
|
|
INFO: [Physopt 32-64] No nets found for fanout-optimization.
|
|||
|
|
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
|||
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_2[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__3 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_0_i_1__3_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_0_i_1__3 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_0[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__1 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/D[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_3__3 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/wea[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/Addr1_i[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst_i_4__0 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_1[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__2 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/Addr3_i[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst_i_2__0 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].metadata_fifo/fifo/metadata_wr_en[4] could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].metadata_fifo/fifo/queue_reg_0_i_1__8 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst_i_2_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst_i_2 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/Addr1_i[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst_i_2__1 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/Addr2_i[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst_i_3__2 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_3_i_1__0_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_3_i_1__0 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_23_i_1_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_23_i_1 could not be replicated
|
|||
|
|
INFO: [Physopt 32-68] No nets found for critical-cell optimization.
|
|||
|
|
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
|||
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.20 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9414 ; free virtual = 12467
|
|||
|
|
|
|||
|
|
Summary of Physical Synthesis Optimizations
|
|||
|
|
============================================
|
|||
|
|
|
|||
|
|
|
|||
|
|
-----------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
|||
|
|
-----------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Very High Fanout | 24 | 0 | 2 | 0 | 1 | 00:00:02 |
|
|||
|
|
| Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| Total | 24 | 0 | 2 | 0 | 3 | 00:00:03 |
|
|||
|
|
-----------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
|
|||
|
|
Phase 2.2 Physical Synthesis In Placer | Checksum: a1c4c65b
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:07:10 ; elapsed = 00:02:59 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9406 ; free virtual = 12459
|
|||
|
|
Phase 2 Global Placement | Checksum: 18f96503a
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:07:19 ; elapsed = 00:03:03 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9477 ; free virtual = 12531
|
|||
|
|
|
|||
|
|
Phase 3 Detail Placement
|
|||
|
|
|
|||
|
|
Phase 3.1 Commit Multi Column Macros
|
|||
|
|
Phase 3.1 Commit Multi Column Macros | Checksum: 18f96503a
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:07:20 ; elapsed = 00:03:04 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9476 ; free virtual = 12529
|
|||
|
|
|
|||
|
|
Phase 3.2 Commit Most Macros & LUTRAMs
|
|||
|
|
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1a2742584
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:08:20 ; elapsed = 00:03:24 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9446 ; free virtual = 12500
|
|||
|
|
|
|||
|
|
Phase 3.3 Area Swap Optimization
|
|||
|
|
Phase 3.3 Area Swap Optimization | Checksum: 17ba149d3
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:08:22 ; elapsed = 00:03:26 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9445 ; free virtual = 12499
|
|||
|
|
|
|||
|
|
Phase 3.4 Pipeline Register Optimization
|
|||
|
|
Phase 3.4 Pipeline Register Optimization | Checksum: 118e960d4
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:08:23 ; elapsed = 00:03:26 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9445 ; free virtual = 12499
|
|||
|
|
|
|||
|
|
Phase 3.5 Timing Path Optimizer
|
|||
|
|
Phase 3.5 Timing Path Optimizer | Checksum: 118e960d4
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:08:23 ; elapsed = 00:03:26 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9445 ; free virtual = 12499
|
|||
|
|
|
|||
|
|
Phase 3.6 Fast Optimization
|
|||
|
|
Phase 3.6 Fast Optimization | Checksum: 1707d8e40
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:08:25 ; elapsed = 00:03:28 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9446 ; free virtual = 12500
|
|||
|
|
|
|||
|
|
Phase 3.7 Small Shape Detail Placement
|
|||
|
|
Phase 3.7 Small Shape Detail Placement | Checksum: 13da19a18
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:09 ; elapsed = 00:04:08 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9298 ; free virtual = 12351
|
|||
|
|
|
|||
|
|
Phase 3.8 Re-assign LUT pins
|
|||
|
|
Phase 3.8 Re-assign LUT pins | Checksum: 193238061
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:13 ; elapsed = 00:04:12 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9304 ; free virtual = 12358
|
|||
|
|
|
|||
|
|
Phase 3.9 Pipeline Register Optimization
|
|||
|
|
Phase 3.9 Pipeline Register Optimization | Checksum: d40b202e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:14 ; elapsed = 00:04:14 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9303 ; free virtual = 12357
|
|||
|
|
Phase 3 Detail Placement | Checksum: d40b202e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:15 ; elapsed = 00:04:14 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9304 ; free virtual = 12357
|
|||
|
|
|
|||
|
|
Phase 4 Post Placement Optimization and Clean-Up
|
|||
|
|
|
|||
|
|
Phase 4.1 Post Commit Optimization
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
|
|||
|
|
Phase 4.1.1 Post Placement Optimization
|
|||
|
|
Post Placement Optimization Initialization | Checksum: c8296051
|
|||
|
|
|
|||
|
|
Phase 4.1.1.1 BUFG Insertion
|
|||
|
|
INFO: [Place 46-33] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[2].output_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-33] Processed net nf_datapath_0/input_arbiter_v1_0/inst/in_arb_queues[3].in_arb_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-33] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-33] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-33] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-33] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-31] BUFG insertion identified 6 candidate nets, 0 success, 6 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
|
|||
|
|
Phase 4.1.1.1 BUFG Insertion | Checksum: c8296051
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:10:18 ; elapsed = 00:04:32 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9422 ; free virtual = 12475
|
|||
|
|
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.096. For the most accurate timing information please run report_timing.
|
|||
|
|
Phase 4.1.1 Post Placement Optimization | Checksum: 10b11ac44
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:20 ; elapsed = 00:06:49 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9396 ; free virtual = 12449
|
|||
|
|
Phase 4.1 Post Commit Optimization | Checksum: 10b11ac44
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:20 ; elapsed = 00:06:50 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9396 ; free virtual = 12449
|
|||
|
|
|
|||
|
|
Phase 4.2 Post Placement Cleanup
|
|||
|
|
Phase 4.2 Post Placement Cleanup | Checksum: 10b11ac44
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:22 ; elapsed = 00:06:51 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9411 ; free virtual = 12465
|
|||
|
|
|
|||
|
|
Phase 4.3 Placer Reporting
|
|||
|
|
Phase 4.3 Placer Reporting | Checksum: 10b11ac44
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:23 ; elapsed = 00:06:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9412 ; free virtual = 12466
|
|||
|
|
|
|||
|
|
Phase 4.4 Final Placement Cleanup
|
|||
|
|
Phase 4.4 Final Placement Cleanup | Checksum: ca7172b5
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:24 ; elapsed = 00:06:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9412 ; free virtual = 12466
|
|||
|
|
Phase 4 Post Placement Optimization and Clean-Up | Checksum: ca7172b5
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:25 ; elapsed = 00:06:53 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9412 ; free virtual = 12465
|
|||
|
|
Ending Placer Task | Checksum: c3a2ca39
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:25 ; elapsed = 00:06:53 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9651 ; free virtual = 12705
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
224 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
place_design completed successfully
|
|||
|
|
place_design: Time (s): cpu = 00:13:38 ; elapsed = 00:07:04 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9652 ; free virtual = 12705
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Writing placer database...
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Write XDEF Complete: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9347 ; free virtual = 12638
|
|||
|
|
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_placed.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:53 ; elapsed = 00:00:42 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9572 ; free virtual = 12689
|
|||
|
|
INFO: [runtcl-4] Executing : report_io -file top_io_placed.rpt
|
|||
|
|
report_io: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.34 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9531 ; free virtual = 12648
|
|||
|
|
INFO: [runtcl-4] Executing : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb
|
|||
|
|
report_utilization: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9568 ; free virtual = 12685
|
|||
|
|
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_control_sets_placed.rpt
|
|||
|
|
report_control_sets: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.81 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9565 ; free virtual = 12684
|
|||
|
|
Command: phys_opt_design -directive ExploreWithHoldFix
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: ExploreWithHoldFix
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9527 ; free virtual = 12646
|
|||
|
|
|
|||
|
|
Starting Physical Synthesis Task
|
|||
|
|
|
|||
|
|
Phase 1 Physical Synthesis Initialization
|
|||
|
|
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.096 | TNS=0.000 |
|
|||
|
|
Phase 1 Physical Synthesis Initialization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:10 ; elapsed = 00:00:20 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9452 ; free virtual = 12571
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.096 | TNS=0.000 |
|
|||
|
|
|
|||
|
|
Phase 2 Fanout Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Fanout Optimization was not performed.
|
|||
|
|
Phase 2 Fanout Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 3 Placement Based Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Placement Based Optimization was not performed.
|
|||
|
|
Phase 3 Placement Based Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 4 MultiInst Placement Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. MultiInst Placement Optimization was not performed.
|
|||
|
|
Phase 4 MultiInst Placement Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 5 Rewire
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Rewire was not performed.
|
|||
|
|
Phase 5 Rewire | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 6 Critical Cell Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Critical Cell Optimization was not performed.
|
|||
|
|
Phase 6 Critical Cell Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 7 Fanout Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Fanout Optimization was not performed.
|
|||
|
|
Phase 7 Fanout Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 8 Placement Based Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Placement Based Optimization was not performed.
|
|||
|
|
Phase 8 Placement Based Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 9 MultiInst Placement Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. MultiInst Placement Optimization was not performed.
|
|||
|
|
Phase 9 MultiInst Placement Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 10 Rewire
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Rewire was not performed.
|
|||
|
|
Phase 10 Rewire | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 11 Critical Cell Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Critical Cell Optimization was not performed.
|
|||
|
|
Phase 11 Critical Cell Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 12 Slr Crossing Optimization
|
|||
|
|
Phase 12 Slr Crossing Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 13 Fanout Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Fanout Optimization was not performed.
|
|||
|
|
Phase 13 Fanout Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 14 Placement Based Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Placement Based Optimization was not performed.
|
|||
|
|
Phase 14 Placement Based Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 15 MultiInst Placement Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. MultiInst Placement Optimization was not performed.
|
|||
|
|
Phase 15 MultiInst Placement Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 16 Rewire
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Rewire was not performed.
|
|||
|
|
Phase 16 Rewire | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 17 Critical Cell Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Critical Cell Optimization was not performed.
|
|||
|
|
Phase 17 Critical Cell Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 18 DSP Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
|||
|
|
Phase 18 DSP Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 19 BRAM Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
|||
|
|
Phase 19 BRAM Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 20 URAM Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
|
|||
|
|
Phase 20 URAM Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 21 Shift Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
|||
|
|
Phase 21 Shift Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 22 DSP Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
|||
|
|
Phase 22 DSP Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 23 BRAM Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
|||
|
|
Phase 23 BRAM Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 24 URAM Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
|
|||
|
|
Phase 24 URAM Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 25 Shift Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
|||
|
|
Phase 25 Shift Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 26 Critical Pin Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Critical Pin Optimization was not performed.
|
|||
|
|
Phase 26 Critical Pin Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 27 Very High Fanout Optimization
|
|||
|
|
INFO: [Physopt 32-76] Pass 1. Identified 71 candidate nets for fanout optimization.
|
|||
|
|
INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/rRst was not replicated.
|
|||
|
|
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
|
|||
|
|
INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/rRst was not replicated.
|
|||
|
|
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/wr_en. Replicated 1 times.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/valid_6. Replicated 1 times.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_1/valid_6. Replicated 1 times.
|
|||
|
|
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/user_reset. Replicated 2 times.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/valid_6. Replicated 1 times.
|
|||
|
|
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_RESET_clk_line/clk_line_rst_high was not replicated.
|
|||
|
|
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_datapath_0/input_arbiter_v1_0/inst/in_arb_queues[3].in_arb_fifo/fifo/SR[0]. Replicated 8 times.
|
|||
|
|
INFO: [Physopt 32-572] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[2].output_fifo/fifo/SR[0] was not replicated.
|
|||
|
|
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_cpu_regs_inst/id_reg1. Replicated 1 times.
|
|||
|
|
INFO: [Physopt 32-232] Optimized 7 nets. Created 15 new instances.
|
|||
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 7 nets or cells. Created 15 new cells, deleted 0 existing cell and moved 0 existing cell
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.096 | TNS=0.000 |
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.33 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9438 ; free virtual = 12558
|
|||
|
|
Phase 27 Very High Fanout Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:21 ; elapsed = 00:00:51 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9438 ; free virtual = 12558
|
|||
|
|
|
|||
|
|
Phase 28 Placement Based Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Placement Based Optimization was not performed.
|
|||
|
|
Phase 28 Placement Based Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:21 ; elapsed = 00:00:51 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9438 ; free virtual = 12558
|
|||
|
|
|
|||
|
|
Phase 29 MultiInst Placement Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. MultiInst Placement Optimization was not performed.
|
|||
|
|
Phase 29 MultiInst Placement Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:21 ; elapsed = 00:00:51 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9438 ; free virtual = 12558
|
|||
|
|
|
|||
|
|
Phase 30 Critical Path Optimization
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.096 | TNS=0.000 |
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.096 | TNS=0.000 |
|
|||
|
|
Phase 30 Critical Path Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:24 ; elapsed = 00:00:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9439 ; free virtual = 12558
|
|||
|
|
|
|||
|
|
Phase 31 BRAM Enable Optimization
|
|||
|
|
Phase 31 BRAM Enable Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:25 ; elapsed = 00:00:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9439 ; free virtual = 12558
|
|||
|
|
|
|||
|
|
Phase 32 Hold Fix Optimization
|
|||
|
|
INFO: [Physopt 32-668] Estimated Timing Summary | WNS=0.096 | TNS=0.000 | WHS=-0.404 | THS=-369.561 |
|
|||
|
|
INFO: [Physopt 32-45] Identified 36 candidate nets for hold slack optimization.
|
|||
|
|
INFO: [Physopt 32-234] Optimized 36 nets. Inserted 0 new ZHOLD_DELAYs. Calibrated 0 existing ZHOLD_DELAYs. Inserted 36 buffers.
|
|||
|
|
|
|||
|
|
INFO: [Physopt 32-668] Estimated Timing Summary | WNS=0.096 | TNS=0.000 | WHS=-0.250 | THS=-358.993 |
|
|||
|
|
Phase 32 Hold Fix Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:59 ; elapsed = 00:00:59 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9392 ; free virtual = 12511
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.28 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9399 ; free virtual = 12519
|
|||
|
|
INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=0.096 | TNS=0.000 | WHS=-0.250 | THS=-358.993 |
|
|||
|
|
|
|||
|
|
Summary of Physical Synthesis Optimizations
|
|||
|
|
============================================
|
|||
|
|
|
|||
|
|
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Fanout | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Placement Based | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| MultiInst Placement | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Rewire | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Critical Cell | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Slr Crossing | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| BRAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| URAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Shift Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Critical Pin | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Very High Fanout | 0.000 | 0.000 | 15 | 0 | 7 | 4 | 1 | 00:00:29 |
|
|||
|
|
| BRAM Enable | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| Critical Path | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| Total | 0.000 | 0.000 | 15 | 0 | 7 | 4 | 4 | 00:00:30 |
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
|
|||
|
|
Summary of Hold Fix Optimizations
|
|||
|
|
=================================
|
|||
|
|
|
|||
|
|
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Optimization | WHS Gain (ns) | THS Gain (ns) | Added LUTs | Added FFs | Optimized Nets | Dont Touch | Iterations | Elapsed |
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| LUT1 and ZHOLD Insertion | 0.154 | 10.568 | 36 | 0 | 36 | 4 | 1 | 00:00:03 |
|
|||
|
|
| Total | 0.154 | 10.568 | 36 | 0 | 36 | 4 | 1 | 00:00:03 |
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
|
|||
|
|
Ending Physical Synthesis Task | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:00 ; elapsed = 00:01:00 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9399 ; free virtual = 12518
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
283 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
phys_opt_design completed successfully
|
|||
|
|
phys_opt_design: Time (s): cpu = 00:04:11 ; elapsed = 00:01:16 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9508 ; free virtual = 12627
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Writing placer database...
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Write XDEF Complete: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9246 ; free virtual = 12598
|
|||
|
|
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_physopt.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:55 ; elapsed = 00:00:43 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9468 ; free virtual = 12649
|
|||
|
|
Command: route_design
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
|||
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
Running DRC as a precondition to command route_design
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
WARNING: [DRC PLCK-18] Clock Placer Checks: Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region.
|
|||
|
|
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
|||
|
|
|
|||
|
|
control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23
|
|||
|
|
control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
|
|||
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
|
|||
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
|
|||
|
|
|
|||
|
|
Starting Routing Task
|
|||
|
|
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
|
|||
|
|
Checksum: PlaceDB: b96faddb ConstDB: 0 ShapeSum: accbbc0c RouteDB: 0
|
|||
|
|
|
|||
|
|
Phase 1 Build RT Design
|
|||
|
|
Phase 1 Build RT Design | Checksum: 10d97bed8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:28 ; elapsed = 00:00:47 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9056 ; free virtual = 12238
|
|||
|
|
Post Restoration Checksum: NetGraph: 6da0886e NumContArr: 9ff7366a Constraints: 0 Timing: 0
|
|||
|
|
|
|||
|
|
Phase 2 Router Initialization
|
|||
|
|
|
|||
|
|
Phase 2.1 Create Timer
|
|||
|
|
Phase 2.1 Create Timer | Checksum: 10d97bed8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:33 ; elapsed = 00:00:51 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9059 ; free virtual = 12241
|
|||
|
|
|
|||
|
|
Phase 2.2 Fix Topology Constraints
|
|||
|
|
Phase 2.2 Fix Topology Constraints | Checksum: 10d97bed8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:34 ; elapsed = 00:00:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8990 ; free virtual = 12173
|
|||
|
|
|
|||
|
|
Phase 2.3 Pre Route Cleanup
|
|||
|
|
Phase 2.3 Pre Route Cleanup | Checksum: 10d97bed8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:34 ; elapsed = 00:00:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8990 ; free virtual = 12173
|
|||
|
|
Number of Nodes with overlaps = 0
|
|||
|
|
|
|||
|
|
Phase 2.4 Update Timing
|
|||
|
|
Phase 2.4 Update Timing | Checksum: 19018a1ee
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:54 ; elapsed = 00:01:20 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8926 ; free virtual = 12109
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.227 | TNS=0.000 | WHS=-0.432 | THS=-10847.808|
|
|||
|
|
|
|||
|
|
|
|||
|
|
Phase 2.5 Update Timing for Bus Skew
|
|||
|
|
|
|||
|
|
Phase 2.5.1 Update Timing
|
|||
|
|
Phase 2.5.1 Update Timing | Checksum: 1199e0fe2
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:49 ; elapsed = 00:01:32 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8891 ; free virtual = 12075
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.227 | TNS=0.000 | WHS=N/A | THS=N/A |
|
|||
|
|
|
|||
|
|
Phase 2.5 Update Timing for Bus Skew | Checksum: 1803077f9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:49 ; elapsed = 00:01:33 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8884 ; free virtual = 12068
|
|||
|
|
Phase 2 Router Initialization | Checksum: 19a795a20
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:50 ; elapsed = 00:01:33 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8884 ; free virtual = 12068
|
|||
|
|
|
|||
|
|
Phase 3 Initial Routing
|
|||
|
|
Phase 3 Initial Routing | Checksum: 13cafeaba
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:06:33 ; elapsed = 00:02:17 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8850 ; free virtual = 12034
|
|||
|
|
|
|||
|
|
Phase 4 Rip-up And Reroute
|
|||
|
|
|
|||
|
|
Phase 4.1 Global Iteration 0
|
|||
|
|
Number of Nodes with overlaps = 12175
|
|||
|
|
Number of Nodes with overlaps = 1084
|
|||
|
|
Number of Nodes with overlaps = 216
|
|||
|
|
Number of Nodes with overlaps = 60
|
|||
|
|
Number of Nodes with overlaps = 14
|
|||
|
|
Number of Nodes with overlaps = 2
|
|||
|
|
Number of Nodes with overlaps = 0
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.113 | TNS=0.000 | WHS=N/A | THS=N/A |
|
|||
|
|
|
|||
|
|
Phase 4.1 Global Iteration 0 | Checksum: 152d3fe99
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:10:51 ; elapsed = 00:03:30 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8861 ; free virtual = 12045
|
|||
|
|
Phase 4 Rip-up And Reroute | Checksum: 152d3fe99
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:10:51 ; elapsed = 00:03:30 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8861 ; free virtual = 12045
|
|||
|
|
|
|||
|
|
Phase 5 Delay and Skew Optimization
|
|||
|
|
|
|||
|
|
Phase 5.1 Delay CleanUp
|
|||
|
|
|
|||
|
|
Phase 5.1.1 Update Timing
|
|||
|
|
Phase 5.1.1 Update Timing | Checksum: c1e010b3
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:04 ; elapsed = 00:03:34 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8855 ; free virtual = 12039
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.186 | TNS=0.000 | WHS=N/A | THS=N/A |
|
|||
|
|
|
|||
|
|
Phase 5.1 Delay CleanUp | Checksum: 18c220186
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:05 ; elapsed = 00:03:34 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8860 ; free virtual = 12044
|
|||
|
|
|
|||
|
|
Phase 5.2 Clock Skew Optimization
|
|||
|
|
Phase 5.2 Clock Skew Optimization | Checksum: 18c220186
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:05 ; elapsed = 00:03:34 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8861 ; free virtual = 12045
|
|||
|
|
Phase 5 Delay and Skew Optimization | Checksum: 18c220186
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:05 ; elapsed = 00:03:35 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8861 ; free virtual = 12045
|
|||
|
|
|
|||
|
|
Phase 6 Post Hold Fix
|
|||
|
|
|
|||
|
|
Phase 6.1 Hold Fix Iter
|
|||
|
|
|
|||
|
|
Phase 6.1.1 Update Timing
|
|||
|
|
Phase 6.1.1 Update Timing | Checksum: 1a58fcf4a
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:20 ; elapsed = 00:03:39 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8862 ; free virtual = 12046
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.186 | TNS=0.000 | WHS=-0.180 | THS=-0.522 |
|
|||
|
|
|
|||
|
|
Phase 6.1 Hold Fix Iter | Checksum: 1c1ba59e3
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:22 ; elapsed = 00:03:39 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8842 ; free virtual = 12026
|
|||
|
|
Phase 6 Post Hold Fix | Checksum: 12f533860
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:23 ; elapsed = 00:03:40 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8842 ; free virtual = 12026
|
|||
|
|
|
|||
|
|
Phase 7 Route finalize
|
|||
|
|
|
|||
|
|
Router Utilization Summary
|
|||
|
|
Global Vertical Routing Utilization = 5.86655 %
|
|||
|
|
Global Horizontal Routing Utilization = 6.67007 %
|
|||
|
|
Routable Net Status*
|
|||
|
|
*Does not include unroutable nets such as driverless and loadless.
|
|||
|
|
Run report_route_status for detailed report.
|
|||
|
|
Number of Failed Nets = 0
|
|||
|
|
Number of Unrouted Nets = 0
|
|||
|
|
Number of Partially Routed Nets = 0
|
|||
|
|
Number of Node Overlaps = 0
|
|||
|
|
|
|||
|
|
Phase 7 Route finalize | Checksum: 1ec49cbbe
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:24 ; elapsed = 00:03:40 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8837 ; free virtual = 12021
|
|||
|
|
|
|||
|
|
Phase 8 Verifying routed nets
|
|||
|
|
|
|||
|
|
Verification completed successfully
|
|||
|
|
Phase 8 Verifying routed nets | Checksum: 1ec49cbbe
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:25 ; elapsed = 00:03:41 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8835 ; free virtual = 12019
|
|||
|
|
|
|||
|
|
Phase 9 Depositing Routes
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_gt_common_block/gthe2_common_0_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y9/GTNORTHREFCLK0
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y23/GTREFCLK1
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y5/GTREFCLK1
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y22/GTREFCLK1
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y21/GTREFCLK1
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y20/GTREFCLK1
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK0
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y4/GTSOUTHREFCLK0
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK0
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK0
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK0
|
|||
|
|
Phase 9 Depositing Routes | Checksum: 1515d35bd
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:32 ; elapsed = 00:03:48 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8845 ; free virtual = 12029
|
|||
|
|
|
|||
|
|
Phase 10 Post Router Timing
|
|||
|
|
|
|||
|
|
Phase 10.1 Update Timing
|
|||
|
|
Phase 10.1 Update Timing | Checksum: 16170ac28
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:47 ; elapsed = 00:03:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8853 ; free virtual = 12037
|
|||
|
|
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.186 | TNS=0.000 | WHS=0.014 | THS=0.000 |
|
|||
|
|
|
|||
|
|
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
|||
|
|
Phase 10 Post Router Timing | Checksum: 16170ac28
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:47 ; elapsed = 00:03:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8853 ; free virtual = 12037
|
|||
|
|
INFO: [Route 35-16] Router Completed Successfully
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:47 ; elapsed = 00:03:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9011 ; free virtual = 12195
|
|||
|
|
|
|||
|
|
Routing Is Done.
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
313 Infos, 161 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
route_design completed successfully
|
|||
|
|
route_design: Time (s): cpu = 00:12:05 ; elapsed = 00:04:05 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9011 ; free virtual = 12195
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Writing placer database...
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Write XDEF Complete: Time (s): cpu = 00:00:18 ; elapsed = 00:00:07 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8654 ; free virtual = 12132
|
|||
|
|
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_routed.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:57 ; elapsed = 00:00:44 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8920 ; free virtual = 12180
|
|||
|
|
INFO: [runtcl-4] Executing : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
|
|||
|
|
Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_routed.rpt.
|
|||
|
|
report_drc completed successfully
|
|||
|
|
report_drc: Time (s): cpu = 00:00:39 ; elapsed = 00:00:13 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8835 ; free virtual = 12095
|
|||
|
|
INFO: [runtcl-4] Executing : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
|
|||
|
|
Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [DRC 23-133] Running Methodology with 8 threads
|
|||
|
|
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_methodology_drc_routed.rpt.
|
|||
|
|
report_methodology completed successfully
|
|||
|
|
report_methodology: Time (s): cpu = 00:02:45 ; elapsed = 00:00:35 . Memory (MB): peak = 5178.754 ; gain = 98.043 ; free physical = 8059 ; free virtual = 11320
|
|||
|
|
INFO: [runtcl-4] Executing : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
|
|||
|
|
Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
Running Vector-less Activity Propagation...
|
|||
|
|
|
|||
|
|
Finished Running Vector-less Activity Propagation
|
|||
|
|
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
|
|||
|
|
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
|
|||
|
|
325 Infos, 162 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
report_power completed successfully
|
|||
|
|
report_power: Time (s): cpu = 00:01:14 ; elapsed = 00:00:31 . Memory (MB): peak = 5404.172 ; gain = 225.418 ; free physical = 7922 ; free virtual = 11199
|
|||
|
|
INFO: [runtcl-4] Executing : report_route_status -file top_route_status.rpt -pb top_route_status.pb
|
|||
|
|
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx
|
|||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
|
|||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
|||
|
|
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
|
|||
|
|
report_timing_summary: Time (s): cpu = 00:00:29 ; elapsed = 00:00:07 . Memory (MB): peak = 5425.145 ; gain = 20.973 ; free physical = 7864 ; free virtual = 11146
|
|||
|
|
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_incremental_reuse_routed.rpt
|
|||
|
|
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
|
|||
|
|
INFO: [runtcl-4] Executing : report_clock_utilization -file top_clock_utilization_routed.rpt
|
|||
|
|
report_clock_utilization: Time (s): cpu = 00:00:52 ; elapsed = 00:00:52 . Memory (MB): peak = 5425.145 ; gain = 0.000 ; free physical = 7860 ; free virtual = 11143
|
|||
|
|
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx
|
|||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
|
|||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
|||
|
|
Command: phys_opt_design -directive AggressiveExplore
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 99.3% nets are fully routed)
|
|||
|
|
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AggressiveExplore
|
|||
|
|
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
|
|||
|
|
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
341 Infos, 163 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
phys_opt_design completed successfully
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Writing placer database...
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Write XDEF Complete: Time (s): cpu = 00:00:17 ; elapsed = 00:00:07 . Memory (MB): peak = 5432.551 ; gain = 7.402 ; free physical = 7469 ; free virtual = 11048
|
|||
|
|
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_postroute_physopt.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:55 ; elapsed = 00:00:43 . Memory (MB): peak = 5432.551 ; gain = 7.402 ; free physical = 7748 ; free virtual = 11108
|
|||
|
|
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -warn_on_violation -file top_timing_summary_postroute_physopted.rpt -pb top_timing_summary_postroute_physopted.pb -rpx top_timing_summary_postroute_physopted.rpx
|
|||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
|
|||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
|||
|
|
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
|
|||
|
|
report_timing_summary: Time (s): cpu = 00:00:16 ; elapsed = 00:00:05 . Memory (MB): peak = 5464.551 ; gain = 32.000 ; free physical = 7739 ; free virtual = 11105
|
|||
|
|
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_postroute_physopted.rpt -pb top_bus_skew_postroute_physopted.pb -rpx top_bus_skew_postroute_physopted.rpx
|
|||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
|
|||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
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INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
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INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
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|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
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|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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Command: write_bitstream -force top.bit
|
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Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
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CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.
|
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Evaluation cores found in this design:
|
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IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features:
|
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|
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IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
|
|||
|
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IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
|
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IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
|
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IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features:
|
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IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
|
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IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
|
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IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
|
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Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
|
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Running DRC as a precondition to command write_bitstream
|
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INFO: [DRC 23-27] Running DRC with 8 threads
|
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WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
|
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WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
|
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WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
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WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
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WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
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WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
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WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
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control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
|
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WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
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control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
|
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WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
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control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
|
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WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
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control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed).
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_25) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_26) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_27) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 51 Warnings, 103 Advisories
|
|||
|
|
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
|
|||
|
|
Loading data files...
|
|||
|
|
Loading site data...
|
|||
|
|
Loading route data...
|
|||
|
|
Processing options...
|
|||
|
|
Creating bitmap...
|
|||
|
|
Creating bitstream...
|
|||
|
|
Bitstream compression saved 136486912 bits.
|
|||
|
|
Writing bitstream ./top.bit...
|
|||
|
|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
498 Infos, 215 Warnings, 1 Critical Warnings and 0 Errors encountered.
|
|||
|
|
write_bitstream completed successfully
|
|||
|
|
write_bitstream: Time (s): cpu = 00:03:03 ; elapsed = 00:03:16 . Memory (MB): peak = 6174.973 ; gain = 710.422 ; free physical = 7700 ; free virtual = 11085
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 28 18:41:49 2019...
|
|||
|
|
[Sun Jul 28 18:41:50 2019] impl_1 finished
|
|||
|
|
wait_on_run: Time (s): cpu = 01:01:57 ; elapsed = 00:40:00 . Memory (MB): peak = 2876.820 ; gain = 0.000 ; free physical = 11824 ; free virtual = 15211
|
|||
|
|
# exit
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 28 18:41:50 2019...
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
make -C hw export_to_sdk
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
rm -f ../hw/create_ip/id_rom16x32.coe
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
|
|||
|
|
echo 16028002 >> rom_data.txt
|
|||
|
|
echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt
|
|||
|
|
grep: ../../../RELEASE_NOTES: No such file or directory
|
|||
|
|
echo 00000204 >> rom_data.txt
|
|||
|
|
echo 0000FFFF >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
echo FFFF0000 >> rom_data.txt
|
|||
|
|
cp /home/nico/projects/P4-NetFPGA/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py
|
|||
|
|
16
|
|||
|
|
|
|||
|
|
mv -f id_rom16x32.coe ../hw/create_ip/
|
|||
|
|
mv -f rom_data.txt ../hw/create_ip/
|
|||
|
|
if test -d project; then\
|
|||
|
|
echo "export simple_sume_switch project to SDK"; \
|
|||
|
|
vivado -mode tcl -source tcl/export_hardware.tcl -tclargs simple_sume_switch;\
|
|||
|
|
else \
|
|||
|
|
echo "Project simple_sume_switch does not exist.";\
|
|||
|
|
echo "Please run \"make project\" to create and build the project first";\
|
|||
|
|
fi;\
|
|||
|
|
|
|||
|
|
export simple_sume_switch project to SDK
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source tcl/export_hardware.tcl
|
|||
|
|
# set design [lindex $argv 0]
|
|||
|
|
# puts "\nOpening $design XPR project\n"
|
|||
|
|
|
|||
|
|
Opening simple_sume_switch XPR project
|
|||
|
|
|
|||
|
|
# open_project project/$design.xpr
|
|||
|
|
Scanning sources...
|
|||
|
|
Finished scanning sources
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
|
|||
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
|||
|
|
WARNING: [IP_Flow 19-3664] IP 'bd_7ad4_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-5853-nsg-System/coregen/bd_7ad4_xpcs_0_1/elaborate/configure_gt.tcl'. Please regenerate to continue.
|
|||
|
|
WARNING: [IP_Flow 19-3664] IP 'bd_a1aa_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-5853-nsg-System/coregen/bd_a1aa_xpcs_0_2/elaborate/configure_gt.tcl'. Please regenerate to continue.
|
|||
|
|
open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1365.203 ; gain = 184.977 ; free physical = 12562 ; free virtual = 15950
|
|||
|
|
# puts "\nOpening $design Implementation design\n"
|
|||
|
|
|
|||
|
|
Opening simple_sume_switch Implementation design
|
|||
|
|
|
|||
|
|
# open_run impl_1
|
|||
|
|
INFO: [Netlist 29-17] Analyzing 4024 Unisim elements for replacement
|
|||
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|||
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
|
|||
|
|
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
|
|||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|||
|
|
INFO: [Timing 38-478] Restoring timing data from binary archive.
|
|||
|
|
INFO: [Timing 38-479] Binary timing data restore complete.
|
|||
|
|
INFO: [Project 1-856] Restoring constraints from binary archive.
|
|||
|
|
INFO: [Project 1-853] Binary constraint restore complete.
|
|||
|
|
Reading XDEF placement.
|
|||
|
|
Reading placer database...
|
|||
|
|
Reading XDEF routing.
|
|||
|
|
Read XDEF File: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3405.051 ; gain = 162.617 ; free physical = 10640 ; free virtual = 14028
|
|||
|
|
Restored from archive | CPU: 7.620000 secs | Memory: 174.191803 MB |
|
|||
|
|
Finished XDEF File Restore: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3405.051 ; gain = 162.617 ; free physical = 10640 ; free virtual = 14028
|
|||
|
|
Generating merged BMM file for the design top 'top'...
|
|||
|
|
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/data/mb_bootloop_le.elf
|
|||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|||
|
|
A total of 670 instances were transformed.
|
|||
|
|
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
|
|||
|
|
LUT6_2 => LUT6_2 (LUT5, LUT6): 79 instances
|
|||
|
|
RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 20 instances
|
|||
|
|
RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
|
|||
|
|
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 365 instances
|
|||
|
|
RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances
|
|||
|
|
RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 145 instances
|
|||
|
|
RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 24 instances
|
|||
|
|
SRLC16E => SRL16E: 1 instances
|
|||
|
|
|
|||
|
|
open_run: Time (s): cpu = 00:01:15 ; elapsed = 00:02:15 . Memory (MB): peak = 4133.406 ; gain = 2768.203 ; free physical = 10687 ; free virtual = 14076
|
|||
|
|
# puts "\nCopying top.sysdef\n"
|
|||
|
|
|
|||
|
|
Copying top.sysdef
|
|||
|
|
|
|||
|
|
# file copy -force ./project/$design.runs/impl_1/top.sysdef ../sw/embedded/$design.hdf
|
|||
|
|
# exit
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 28 18:44:17 2019...
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
make -C sw/embedded/ project
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
|
|||
|
|
mkdir ./SDK_Workspace
|
|||
|
|
xsdk -batch -source ./tcl/simple_sume_switch_xsdk.tcl
|
|||
|
|
Starting xsdk. This could take few seconds... Eclipse: Cannot open display:
|
|||
|
|
done
|
|||
|
|
INFO: [Hsi 55-1698] elapsed time for repository loading 1 seconds
|
|||
|
|
/opt/Xilinx/SDK/2018.2/gnu/microblaze/lin
|
|||
|
|
BSP project 'bsp' created successfully.
|
|||
|
|
WARNING: [Hsi 61-9] Current Software design may not be compatible with "hello_world" app. Tool is ignoring the MSS file specified in the app directory
|
|||
|
|
Application project 'app' created successfully.
|
|||
|
|
Building '/bsp'
|
|||
|
|
Invoking Make Builder...bsp
|
|||
|
|
18:44:25 **** Build of project bsp ****
|
|||
|
|
make -k all
|
|||
|
|
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
Compiling standalone
|
|||
|
|
microblaze_sleep.c:74:9: note: #pragma message: For the sleep routines, assembly instructions are used
|
|||
|
|
#pragma message ("For the sleep routines, assembly instructions are used")
|
|||
|
|
^~~~~~~
|
|||
|
|
mb-ar: creating ../../../lib/libxil.a
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
Compiling iic
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
Compiling uartlite
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
Compiling bram
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
Compiling cpu
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
Compiling intc
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
Finished building libraries
|
|||
|
|
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'
|
|||
|
|
|
|||
|
|
18:44:27 Build Finished (took 1s.914ms)
|
|||
|
|
|
|||
|
|
Building '/app'
|
|||
|
|
18:44:27 **** Build of configuration Debug for project app ****
|
|||
|
|
make all
|
|||
|
|
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
|
|||
|
|
Building file: ../src/helloworld.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c"
|
|||
|
|
Finished building: ../src/helloworld.c
|
|||
|
|
|
|||
|
|
Building file: ../src/platform.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c"
|
|||
|
|
Finished building: ../src/platform.c
|
|||
|
|
|
|||
|
|
Building target: app.elf
|
|||
|
|
Invoking: MicroBlaze gcc linker
|
|||
|
|
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf" ./src/helloworld.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
|
|||
|
|
Finished building target: app.elf
|
|||
|
|
|
|||
|
|
Invoking: MicroBlaze Print Size
|
|||
|
|
mb-size app.elf |tee "app.elf.size"
|
|||
|
|
text data bss dec hex filename
|
|||
|
|
3112 316 3108 6536 1988 app.elf
|
|||
|
|
Finished building: app.elf.size
|
|||
|
|
|
|||
|
|
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
|
|||
|
|
|
|||
|
|
18:44:27 Build Finished (took 464ms)
|
|||
|
|
|
|||
|
|
Invoking scanner config builder on project
|
|||
|
|
Building '/hw_platform'
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
|
|||
|
|
make -C sw/embedded/ compile
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
|
|||
|
|
Eclipse:
|
|||
|
|
GTK+ Version Check
|
|||
|
|
Eclipse: Cannot open display:
|
|||
|
|
Building All Projects...
|
|||
|
|
Building workspace
|
|||
|
|
Building '/bsp'
|
|||
|
|
Invoking Make Builder...bsp
|
|||
|
|
18:44:30 **** Build of project bsp ****
|
|||
|
|
make -k all
|
|||
|
|
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
Compiling standalone
|
|||
|
|
microblaze_sleep.c:74:9: note: #pragma message: For the sleep routines, assembly instructions are used
|
|||
|
|
#pragma message ("For the sleep routines, assembly instructions are used")
|
|||
|
|
^~~~~~~
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
Compiling iic
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
Compiling uartlite
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
Compiling bram
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
Compiling cpu
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
Compiling intc
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
Finished building libraries
|
|||
|
|
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'
|
|||
|
|
|
|||
|
|
18:44:32 Build Finished (took 1s.875ms)
|
|||
|
|
|
|||
|
|
Building '/app'
|
|||
|
|
18:44:32 **** Build of configuration Debug for project app ****
|
|||
|
|
make all
|
|||
|
|
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
|
|||
|
|
Building file: ../src/helloworld.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c"
|
|||
|
|
../src/helloworld.c: In function 'runManualTest':
|
|||
|
|
../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration]
|
|||
|
|
pmReadInfo();
|
|||
|
|
^~~~~~~~~~
|
|||
|
|
../src/helloworld.c: In function 'main':
|
|||
|
|
../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration]
|
|||
|
|
Status = IicInit(&IicInstance);
|
|||
|
|
^~~~~~~
|
|||
|
|
../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration]
|
|||
|
|
Status = SetupInterruptSystem(&IicInstance);
|
|||
|
|
^~~~~~~~~~~~~~~~~~~~
|
|||
|
|
XIntc_InterruptHandler
|
|||
|
|
../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration]
|
|||
|
|
Status = IicInitPost(&IicInstance);
|
|||
|
|
^~~~~~~~~~~
|
|||
|
|
../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration]
|
|||
|
|
config_SI5324();
|
|||
|
|
^~~~~~~~~~~~~
|
|||
|
|
Finished building: ../src/helloworld.c
|
|||
|
|
|
|||
|
|
Building file: ../src/platform.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c"
|
|||
|
|
Finished building: ../src/platform.c
|
|||
|
|
|
|||
|
|
Building target: app.elf
|
|||
|
|
Invoking: MicroBlaze gcc linker
|
|||
|
|
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf" ./src/helloworld.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
|
|||
|
|
./src/helloworld.o: In function `runManualTest':
|
|||
|
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:103: undefined reference to `pmReadInfo'
|
|||
|
|
./src/helloworld.o: In function `main':
|
|||
|
|
makefile:36: recipe for target 'app.elf' failed
|
|||
|
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:125: undefined reference to `IicInit'
|
|||
|
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:143: undefined reference to `IicInitPost'
|
|||
|
|
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
|
|||
|
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/../src/helloworld.c:149: undefined reference to `config_SI5324'
|
|||
|
|
collect2: error: ld returned 1 exit status
|
|||
|
|
make[2]: *** [app.elf] Error 1
|
|||
|
|
|
|||
|
|
18:44:33 Build Finished (took 508ms)
|
|||
|
|
|
|||
|
|
18:44:33 **** Build of configuration Release for project app ****
|
|||
|
|
make all
|
|||
|
|
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'
|
|||
|
|
Building file: ../src/helloworld.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c"
|
|||
|
|
../src/helloworld.c: In function 'runManualTest':
|
|||
|
|
../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration]
|
|||
|
|
pmReadInfo();
|
|||
|
|
^~~~~~~~~~
|
|||
|
|
../src/helloworld.c: In function 'main':
|
|||
|
|
../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration]
|
|||
|
|
Status = IicInit(&IicInstance);
|
|||
|
|
^~~~~~~
|
|||
|
|
../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration]
|
|||
|
|
Status = SetupInterruptSystem(&IicInstance);
|
|||
|
|
^~~~~~~~~~~~~~~~~~~~
|
|||
|
|
XIntc_InterruptHandler
|
|||
|
|
../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration]
|
|||
|
|
Status = IicInitPost(&IicInstance);
|
|||
|
|
^~~~~~~~~~~
|
|||
|
|
../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration]
|
|||
|
|
config_SI5324();
|
|||
|
|
^~~~~~~~~~~~~
|
|||
|
|
Finished building: ../src/helloworld.c
|
|||
|
|
|
|||
|
|
Building file: ../src/iic_config.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_config.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_config.d" -MT"src/iic_config.o" -o "src/iic_config.o" "../src/iic_config.c"
|
|||
|
|
../src/iic_config.c: In function 'IicReadData3':
|
|||
|
|
../src/iic_config.c:439:10: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types]
|
|||
|
|
addrPtr = &addr;
|
|||
|
|
^
|
|||
|
|
../src/iic_config.c:397:5: warning: unused variable 'IicOptions' [-Wunused-variable]
|
|||
|
|
u8 IicOptions;
|
|||
|
|
^~~~~~~~~~
|
|||
|
|
Finished building: ../src/iic_config.c
|
|||
|
|
|
|||
|
|
Building file: ../src/iic_pm.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_pm.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_pm.d" -MT"src/iic_pm.o" -o "src/iic_pm.o" "../src/iic_pm.c"
|
|||
|
|
Finished building: ../src/iic_pm.c
|
|||
|
|
|
|||
|
|
Building file: ../src/iic_si5324.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_si5324.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_si5324.d" -MT"src/iic_si5324.o" -o "src/iic_si5324.o" "../src/iic_si5324.c"
|
|||
|
|
Finished building: ../src/iic_si5324.c
|
|||
|
|
|
|||
|
|
Building file: ../src/platform.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c"
|
|||
|
|
Finished building: ../src/platform.c
|
|||
|
|
|
|||
|
|
Building target: app.elf
|
|||
|
|
Invoking: MicroBlaze gcc linker
|
|||
|
|
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf" ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
|
|||
|
|
Finished building target: app.elf
|
|||
|
|
|
|||
|
|
Invoking: MicroBlaze Print Size
|
|||
|
|
mb-size app.elf |tee "app.elf.size"
|
|||
|
|
text data bss dec hex filename
|
|||
|
|
18364 468 3376 22208 56c0 app.elf
|
|||
|
|
Finished building: app.elf.size
|
|||
|
|
|
|||
|
|
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'
|
|||
|
|
|
|||
|
|
18:44:34 Build Finished (took 608ms)
|
|||
|
|
|
|||
|
|
Invoking scanner config builder on project
|
|||
|
|
Building '/hw_platform'
|
|||
|
|
Eclipse:
|
|||
|
|
GTK+ Version Check
|
|||
|
|
Eclipse: Cannot open display:
|
|||
|
|
Building All Projects...
|
|||
|
|
Building workspace
|
|||
|
|
Building '/bsp'
|
|||
|
|
Invoking Make Builder...bsp
|
|||
|
|
18:44:38 **** Build of project bsp ****
|
|||
|
|
make -k all
|
|||
|
|
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src/profile'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
Running Make include in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
Compiling standalone
|
|||
|
|
microblaze_sleep.c:74:9: note: #pragma message: For the sleep routines, assembly instructions are used
|
|||
|
|
#pragma message ("For the sleep routines, assembly instructions are used")
|
|||
|
|
^~~~~~~
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/standalone_v6_7/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
Compiling iic
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/iic_v3_4/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
Compiling uartlite
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/uartlite_v3_2/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
Compiling bram
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/bram_v4_2/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
Compiling cpu
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/cpu_v2_7/src'
|
|||
|
|
Running Make libs in control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src
|
|||
|
|
make -C control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v10.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra"
|
|||
|
|
make[3]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
Compiling intc
|
|||
|
|
make[4]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
make[4]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
make[3]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/libsrc/intc_v3_7/src'
|
|||
|
|
Finished building libraries
|
|||
|
|
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/bsp'
|
|||
|
|
|
|||
|
|
18:44:40 Build Finished (took 1s.875ms)
|
|||
|
|
|
|||
|
|
Building '/app'
|
|||
|
|
18:44:40 **** Clean-only build of configuration Debug for project app ****
|
|||
|
|
make clean
|
|||
|
|
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
|
|||
|
|
rm -rf ./src/helloworld.o ./src/platform.o ./src/helloworld.d ./src/platform.d app.elf.size app.elf
|
|||
|
|
|
|||
|
|
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
|
|||
|
|
|
|||
|
|
18:44:40 Build Finished (took 406ms)
|
|||
|
|
|
|||
|
|
18:44:40 **** Build of configuration Debug for project app ****
|
|||
|
|
make all
|
|||
|
|
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
|
|||
|
|
Building file: ../src/helloworld.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c"
|
|||
|
|
../src/helloworld.c: In function 'runManualTest':
|
|||
|
|
../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration]
|
|||
|
|
pmReadInfo();
|
|||
|
|
^~~~~~~~~~
|
|||
|
|
../src/helloworld.c: In function 'main':
|
|||
|
|
../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration]
|
|||
|
|
Status = IicInit(&IicInstance);
|
|||
|
|
^~~~~~~
|
|||
|
|
../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration]
|
|||
|
|
Status = SetupInterruptSystem(&IicInstance);
|
|||
|
|
^~~~~~~~~~~~~~~~~~~~
|
|||
|
|
XIntc_InterruptHandler
|
|||
|
|
../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration]
|
|||
|
|
Status = IicInitPost(&IicInstance);
|
|||
|
|
^~~~~~~~~~~
|
|||
|
|
../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration]
|
|||
|
|
config_SI5324();
|
|||
|
|
^~~~~~~~~~~~~
|
|||
|
|
Finished building: ../src/helloworld.c
|
|||
|
|
|
|||
|
|
Building file: ../src/iic_config.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/iic_config.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_config.d" -MT"src/iic_config.o" -o "src/iic_config.o" "../src/iic_config.c"
|
|||
|
|
../src/iic_config.c: In function 'IicReadData3':
|
|||
|
|
../src/iic_config.c:439:10: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types]
|
|||
|
|
addrPtr = &addr;
|
|||
|
|
^
|
|||
|
|
../src/iic_config.c:397:5: warning: unused variable 'IicOptions' [-Wunused-variable]
|
|||
|
|
u8 IicOptions;
|
|||
|
|
^~~~~~~~~~
|
|||
|
|
Finished building: ../src/iic_config.c
|
|||
|
|
|
|||
|
|
Building file: ../src/iic_pm.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/iic_pm.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_pm.d" -MT"src/iic_pm.o" -o "src/iic_pm.o" "../src/iic_pm.c"
|
|||
|
|
Finished building: ../src/iic_pm.c
|
|||
|
|
|
|||
|
|
Building file: ../src/iic_si5324.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/iic_si5324.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_si5324.d" -MT"src/iic_si5324.o" -o "src/iic_si5324.o" "../src/iic_si5324.c"
|
|||
|
|
Finished building: ../src/iic_si5324.c
|
|||
|
|
|
|||
|
|
Building file: ../src/platform.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c"
|
|||
|
|
Finished building: ../src/platform.c
|
|||
|
|
|
|||
|
|
Building target: app.elf
|
|||
|
|
Invoking: MicroBlaze gcc linker
|
|||
|
|
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf" ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
|
|||
|
|
Finished building target: app.elf
|
|||
|
|
|
|||
|
|
Invoking: MicroBlaze Print Size
|
|||
|
|
mb-size app.elf |tee "app.elf.size"
|
|||
|
|
text data bss dec hex filename
|
|||
|
|
20340 468 3376 24184 5e78 app.elf
|
|||
|
|
Finished building: app.elf.size
|
|||
|
|
|
|||
|
|
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug'
|
|||
|
|
|
|||
|
|
18:44:41 Build Finished (took 609ms)
|
|||
|
|
|
|||
|
|
18:44:41 **** Clean-only build of configuration Release for project app ****
|
|||
|
|
make clean
|
|||
|
|
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'
|
|||
|
|
rm -rf ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o ./src/helloworld.d ./src/iic_config.d ./src/iic_pm.d ./src/iic_si5324.d ./src/platform.d app.elf.size app.elf
|
|||
|
|
|
|||
|
|
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'
|
|||
|
|
|
|||
|
|
18:44:41 Build Finished (took 406ms)
|
|||
|
|
|
|||
|
|
18:44:42 **** Build of configuration Release for project app ****
|
|||
|
|
make all
|
|||
|
|
make[2]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'
|
|||
|
|
Building file: ../src/helloworld.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c"
|
|||
|
|
../src/helloworld.c: In function 'runManualTest':
|
|||
|
|
../src/helloworld.c:103:5: warning: implicit declaration of function 'pmReadInfo' [-Wimplicit-function-declaration]
|
|||
|
|
pmReadInfo();
|
|||
|
|
^~~~~~~~~~
|
|||
|
|
../src/helloworld.c: In function 'main':
|
|||
|
|
../src/helloworld.c:125:11: warning: implicit declaration of function 'IicInit' [-Wimplicit-function-declaration]
|
|||
|
|
Status = IicInit(&IicInstance);
|
|||
|
|
^~~~~~~
|
|||
|
|
../src/helloworld.c:134:11: warning: implicit declaration of function 'SetupInterruptSystem'; did you mean 'XIntc_InterruptHandler'? [-Wimplicit-function-declaration]
|
|||
|
|
Status = SetupInterruptSystem(&IicInstance);
|
|||
|
|
^~~~~~~~~~~~~~~~~~~~
|
|||
|
|
XIntc_InterruptHandler
|
|||
|
|
../src/helloworld.c:143:11: warning: implicit declaration of function 'IicInitPost' [-Wimplicit-function-declaration]
|
|||
|
|
Status = IicInitPost(&IicInstance);
|
|||
|
|
^~~~~~~~~~~
|
|||
|
|
../src/helloworld.c:149:2: warning: implicit declaration of function 'config_SI5324' [-Wimplicit-function-declaration]
|
|||
|
|
config_SI5324();
|
|||
|
|
^~~~~~~~~~~~~
|
|||
|
|
Finished building: ../src/helloworld.c
|
|||
|
|
|
|||
|
|
Building file: ../src/iic_config.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_config.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_config.d" -MT"src/iic_config.o" -o "src/iic_config.o" "../src/iic_config.c"
|
|||
|
|
../src/iic_config.c: In function 'IicReadData3':
|
|||
|
|
../src/iic_config.c:439:10: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types]
|
|||
|
|
addrPtr = &addr;
|
|||
|
|
^
|
|||
|
|
../src/iic_config.c:397:5: warning: unused variable 'IicOptions' [-Wunused-variable]
|
|||
|
|
u8 IicOptions;
|
|||
|
|
^~~~~~~~~~
|
|||
|
|
Finished building: ../src/iic_config.c
|
|||
|
|
|
|||
|
|
Building file: ../src/iic_pm.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_pm.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_pm.d" -MT"src/iic_pm.o" -o "src/iic_pm.o" "../src/iic_pm.c"
|
|||
|
|
Finished building: ../src/iic_pm.c
|
|||
|
|
|
|||
|
|
Building file: ../src/iic_si5324.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/iic_si5324.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/iic_si5324.d" -MT"src/iic_si5324.o" -o "src/iic_si5324.o" "../src/iic_si5324.c"
|
|||
|
|
Finished building: ../src/iic_si5324.c
|
|||
|
|
|
|||
|
|
Building file: ../src/platform.c
|
|||
|
|
Invoking: MicroBlaze gcc compiler
|
|||
|
|
mb-gcc -Wall -O2 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c"
|
|||
|
|
Finished building: ../src/platform.c
|
|||
|
|
|
|||
|
|
Building target: app.elf
|
|||
|
|
Invoking: MicroBlaze gcc linker
|
|||
|
|
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/control_sub_i_nf_mbsys_mbsys_microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "app.elf" ./src/helloworld.o ./src/iic_config.o ./src/iic_pm.o ./src/iic_si5324.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
|
|||
|
|
Finished building target: app.elf
|
|||
|
|
|
|||
|
|
Invoking: MicroBlaze Print Size
|
|||
|
|
mb-size app.elf |tee "app.elf.size"
|
|||
|
|
text data bss dec hex filename
|
|||
|
|
18364 468 3376 22208 56c0 app.elf
|
|||
|
|
Finished building: app.elf.size
|
|||
|
|
|
|||
|
|
make[2]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Release'
|
|||
|
|
|
|||
|
|
18:44:42 Build Finished (took 610ms)
|
|||
|
|
|
|||
|
|
Invoking scanner config builder on project
|
|||
|
|
Building '/hw_platform'
|
|||
|
|
Eclipse:
|
|||
|
|
GTK+ Version Check
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded'
|
|||
|
|
make -C hw load_elf
|
|||
|
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
if test -d project; then\
|
|||
|
|
echo "export simple_sume_switch project to SDK"; \
|
|||
|
|
vivado -mode tcl -source tcl/load_elf.tcl -tclargs simple_sume_switch;\
|
|||
|
|
else \
|
|||
|
|
echo "Project simple_sume_switch does not exist.";\
|
|||
|
|
echo "Please run \"make project\" to create and build the project first";\
|
|||
|
|
fi;\
|
|||
|
|
|
|||
|
|
export simple_sume_switch project to SDK
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source tcl/load_elf.tcl
|
|||
|
|
# set design [lindex $argv 0]
|
|||
|
|
# set ws "SDK_Workspace"
|
|||
|
|
# puts "\nOpening $design XPR project\n"
|
|||
|
|
|
|||
|
|
Opening simple_sume_switch XPR project
|
|||
|
|
|
|||
|
|
# open_project project/$design.xpr
|
|||
|
|
Scanning sources...
|
|||
|
|
Finished scanning sources
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
|
|||
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
|||
|
|
WARNING: [IP_Flow 19-3664] IP 'bd_7ad4_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-5853-nsg-System/coregen/bd_7ad4_xpcs_0_1/elaborate/configure_gt.tcl'. Please regenerate to continue.
|
|||
|
|
WARNING: [IP_Flow 19-3664] IP 'bd_a1aa_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-5853-nsg-System/coregen/bd_a1aa_xpcs_0_2/elaborate/configure_gt.tcl'. Please regenerate to continue.
|
|||
|
|
open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1364.727 ; gain = 184.500 ; free physical = 12359 ; free virtual = 15944
|
|||
|
|
# set bd_file [get_files -regexp -nocase {.*sub*.bd}]
|
|||
|
|
# set elf_file ../sw/embedded/$ws/$design/app/Debug/app.elf
|
|||
|
|
# puts "\nOpening $design BD project\n"
|
|||
|
|
|
|||
|
|
Opening simple_sume_switch BD project
|
|||
|
|
|
|||
|
|
# open_bd_design $bd_file
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_iic:2.0 - axi_iic_0
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_uartlite:2.0 - axi_uartlite_0
|
|||
|
|
Adding cell -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_1
|
|||
|
|
Adding cell -- xilinx.com:ip:mdm:3.2 - mdm_1
|
|||
|
|
Adding cell -- xilinx.com:ip:microblaze:10.0 - microblaze_0
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_intc:4.1 - microblaze_0_axi_intc
|
|||
|
|
Adding cell -- xilinx.com:ip:xlconcat:2.1 - microblaze_0_xlconcat
|
|||
|
|
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_clk_wiz_1_100M
|
|||
|
|
Adding cell -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - dlmb_bram_if_cntlr
|
|||
|
|
Adding cell -- xilinx.com:ip:lmb_v10:3.0 - dlmb_v10
|
|||
|
|
Adding cell -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - ilmb_bram_if_cntlr
|
|||
|
|
Adding cell -- xilinx.com:ip:lmb_v10:3.0 - ilmb_v10
|
|||
|
|
Adding cell -- xilinx.com:ip:blk_mem_gen:8.4 - lmb_bram
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
|
|||
|
|
Adding cell -- xilinx.com:ip:util_vector_logic:2.0 - pcie_reset_inv
|
|||
|
|
Adding cell -- xilinx.com:ip:axis_dwidth_converter:1.1 - axis_dwidth_dma_tx
|
|||
|
|
Adding cell -- xilinx.com:ip:axis_dwidth_converter:1.1 - axis_dwidth_dma_rx
|
|||
|
|
Adding cell -- xilinx.com:ip:axis_data_fifo:1.1 - axis_fifo_10g_rx
|
|||
|
|
Adding cell -- xilinx.com:ip:axis_data_fifo:1.1 - axis_fifo_10g_tx
|
|||
|
|
Adding cell -- NetFPGA:NetFPGA:nf_riffa_dma:1.0 - nf_riffa_dma_1
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_clock_converter:2.1 - axi_clock_converter_0
|
|||
|
|
Adding cell -- xilinx.com:ip:pcie3_7x:4.3 - pcie3_7x_1
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m08_data_fifo
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m07_data_fifo
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m06_data_fifo
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m05_data_fifo
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m04_data_fifo
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m03_data_fifo
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m02_data_fifo
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m01_data_fifo
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m00_data_fifo
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - s00_data_fifo
|
|||
|
|
Adding cell -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
|
|||
|
|
Successfully read diagram <control_sub> from BD file </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
|||
|
|
# if {[llength [get_files app.elf]]} {
|
|||
|
|
# puts "ELF File [get_files app.elf] is already associated"
|
|||
|
|
# exit
|
|||
|
|
# } else {
|
|||
|
|
# add_files -norecurse -force ${elf_file}
|
|||
|
|
# set_property SCOPED_TO_REF [current_bd_design] [get_files -all -of_objects [get_fileset sources_1] ${elf_file}]
|
|||
|
|
# set_property SCOPED_TO_CELLS nf_mbsys/mbsys/microblaze_0 [get_files -all -of_objects [get_fileset sources_1] ${elf_file}]
|
|||
|
|
# }
|
|||
|
|
WARNING: [Vivado 12-818] No files matched 'app.elf'
|
|||
|
|
# reset_run impl_1 -prev_step
|
|||
|
|
# launch_runs impl_1 -to_step write_bitstream
|
|||
|
|
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'identifier_ip'...
|
|||
|
|
[Sun Jul 28 18:45:00 2019] Launched impl_1...
|
|||
|
|
Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/runme.log
|
|||
|
|
# wait_on_run impl_1
|
|||
|
|
[Sun Jul 28 18:45:00 2019] Waiting for impl_1 to finish...
|
|||
|
|
|
|||
|
|
*** Running vivado
|
|||
|
|
with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace
|
|||
|
|
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source top.tcl -notrace
|
|||
|
|
Command: link_design -top top -part xc7vx690tffg1761-3
|
|||
|
|
Design is defaulting to srcset: sources_1
|
|||
|
|
Design is defaulting to constrset: constrs_1
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0.dcp' for cell 'control_sub_i/dma_sub/axi_clock_converter_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_rx_0/control_sub_axis_dwidth_dma_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_rx'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_dwidth_dma_tx_0/control_sub_axis_dwidth_dma_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_dwidth_dma_tx'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.dcp' for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/control_sub_nf_riffa_dma_1_0.dcp' for cell 'control_sub_i/dma_sub/nf_riffa_dma_1'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/control_sub_pcie3_7x_1_0.dcp' for cell 'control_sub_i/dma_sub/pcie3_7x_1'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie_reset_inv_0/control_sub_pcie_reset_inv_0.dcp' for cell 'control_sub_i/dma_sub/pcie_reset_inv'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_0/control_sub_xbar_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/xbar'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m00_data_fifo_0/control_sub_m00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m00_couplers/m00_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m01_data_fifo_0/control_sub_m01_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m01_couplers/m01_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m02_data_fifo_0/control_sub_m02_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m02_couplers/m02_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m03_data_fifo_0/control_sub_m03_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m03_couplers/m03_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m04_data_fifo_0/control_sub_m04_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m04_couplers/m04_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m05_data_fifo_0/control_sub_m05_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m05_couplers/m05_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m06_data_fifo_0/control_sub_m06_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m06_couplers/m06_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m07_data_fifo_0/control_sub_m07_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m07_couplers/m07_data_fifo'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_m08_data_fifo_0/control_sub_m08_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/m08_couplers/m08_data_fifo'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_s00_data_fifo_0/control_sub_s00_data_fifo_0.dcp' for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/s00_data_fifo'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_iic_0'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.dcp' for cell 'control_sub_i/nf_mbsys/axi_uartlite_0'
|
|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.dcp' for cell 'control_sub_i/nf_mbsys/clk_wiz_1'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1'
|
|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_xlconcat_0/control_sub_microblaze_0_xlconcat_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_xlconcat'
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_xbar_1/control_sub_xbar_1.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_periph/xbar'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_bram_if_cntlr_0/control_sub_dlmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_bram_if_cntlr_0/control_sub_ilmb_bram_if_cntlr_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr'
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|||
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10'
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INFO: [Project 1-454] Reading design checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_lmb_bram_0/control_sub_lmb_bram_0.dcp' for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/lmb_bram'
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INFO: [Netlist 29-17] Analyzing 4601 Unisim elements for replacement
|
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|||
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INFO: [Project 1-479] Netlist was created with Vivado 2018.2
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INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
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INFO: [Project 1-570] Preparing netlist for logic optimization
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_iic_0_0/control_sub_axi_iic_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_iic_0/U0'
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|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
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|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0_board.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
|
|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_uartlite_0_0/control_sub_axi_uartlite_0_0.xdc] for cell 'control_sub_i/nf_mbsys/axi_uartlite_0/U0'
|
|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_board.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
|
|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
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|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0'
|
|||
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INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc:50]
|
|||
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|
get_clocks: Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 3282.309 ; gain = 924.016 ; free physical = 10163 ; free virtual = 13165
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_mdm_1_0/control_sub_mdm_1_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/mdm_1/U0'
|
|||
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/control_sub_microblaze_0_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0/U0'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0_board.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_rst_clk_wiz_1_100M_0/control_sub_rst_clk_wiz_1_100M_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/rst_clk_wiz_1_100M/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_dlmb_v10_0/control_sub_dlmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_v10/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_ilmb_v10_0/control_sub_ilmb_v10_0.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_v10/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst'
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INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc:124]
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_pcie3_7x_1_0/source/control_sub_pcie3_7x_1_0-PCIE_X0Y1.xdc] for cell 'control_sub_i/dma_sub/pcie3_7x_1/inst'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_0/synth/bd_7ad4_xmac_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xmac/inst'
|
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_0/synth/bd_a1aa_xmac_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xmac/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_board.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
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INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc:57]
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip_board.xdc] for cell 'proc_sys_reset_i/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/proc_sys_reset_ip/proc_sys_reset_ip.xdc] for cell 'proc_sys_reset_i/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/lib/hw/std/constraints/generic_bit.xdc]
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc]
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
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WARNING: [Constraints 18-619] A clock with name 'xphy_refclk_p' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:92]
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WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:114]
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WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_block_i/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:115]
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WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:116]
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WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:117]
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WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:118]
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WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:119]
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WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/RXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:120]
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WARNING: [Constraints 18-619] A clock with name 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i/TXOUTCLK' already exists, overwriting the previous clock with the same name. [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:121]
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INFO: [Timing 38-2] Deriving generated clocks [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc:149]
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc]
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_clk_wiz_1_0/control_sub_clk_wiz_1_0_late.xdc] for cell 'control_sub_i/nf_mbsys/clk_wiz_1/inst'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
|
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|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_axi_intc_0/control_sub_microblaze_0_axi_intc_0_clocks.xdc] for cell 'control_sub_i/nf_mbsys/mbsys/microblaze_0_axi_intc/U0'
|
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0/control_sub_axis_fifo_10g_rx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0/control_sub_axis_fifo_10g_tx_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst'
|
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0'
|
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0'
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Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
|
|||
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_nf_riffa_dma_1_0/ip_proj/nf_riffa_dma.srcs/sources_1/ip/axis_fifo_2clk_32d_4u/axis_fifo_2clk_32d_4u_clocks.xdc] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_axi_clock_converter_0_0/control_sub_axi_clock_converter_0_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_auto_cc_0/control_sub_auto_cc_0_clocks.xdc] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_nonshared/bd_0/ip/ip_1/synth/bd_7ad4_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_status/fifo_generator_status_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0'
|
|||
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|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
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Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
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|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/fifo_generator_1_9/fifo_generator_1_9_clocks.xdc] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axi_10g_ethernet_shared/bd_0/ip/ip_1/synth/bd_a1aa_xpcs_0_clocks.xdc] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst'
|
|||
|
|
Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
|
Finished Parsing XDC File [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/clk_wiz_ip/clk_wiz_ip_late.xdc] for cell 'axi_clocking_i/clk_wiz_i/inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
INFO: [Vivado 12-3272] Current instance is the top level cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
INFO: [Common 17-14] Message 'Vivado 12-3272' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
INFO: [Common 17-14] Message 'XPM_CDC_GRAY: TCL 1000' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_interconnect_0/s00_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axi_clock_converter_0/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/aw_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same.
|
|||
|
|
Instance: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr
|
|||
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|||
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|||
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|||
|
|
[/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5]
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_async_clock_and_reset.inst_xpm_cdc_sync_rst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
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|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
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|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
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|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
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|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xvxcv5ctaicypzrsuzoa92bpsxv_1486/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst'
|
|||
|
|
Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
|
|||
|
|
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst'
|
|||
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|||
|
|
Generating merged BMM file for the design top 'top'...
|
|||
|
|
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/ip/control_sub_microblaze_0_0/data/mb_bootloop_le.elf
|
|||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|||
|
|
A total of 808 instances were transformed.
|
|||
|
|
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
|
|||
|
|
LUT6_2 => LUT6_2 (LUT5, LUT6): 80 instances
|
|||
|
|
RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 20 instances
|
|||
|
|
RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
|
|||
|
|
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 367 instances
|
|||
|
|
RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances
|
|||
|
|
RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 245 instances
|
|||
|
|
RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 60 instances
|
|||
|
|
|
|||
|
|
148 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
link_design completed successfully
|
|||
|
|
link_design: Time (s): cpu = 00:01:57 ; elapsed = 00:02:35 . Memory (MB): peak = 4282.207 ; gain = 2957.805 ; free physical = 10254 ; free virtual = 13258
|
|||
|
|
Command: opt_design
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
Running DRC as a precondition to command opt_design
|
|||
|
|
|
|||
|
|
Starting DRC Task
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
INFO: [Project 1-461] DRC finished with 0 Errors
|
|||
|
|
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10250 ; free virtual = 13254
|
|||
|
|
|
|||
|
|
Starting Cache Timing Information Task
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
Ending Cache Timing Information Task | Checksum: 198abdbdc
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:14 ; elapsed = 00:00:05 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10063 ; free virtual = 13067
|
|||
|
|
|
|||
|
|
Starting Logic Optimization Task
|
|||
|
|
|
|||
|
|
Phase 1 Retarget
|
|||
|
|
INFO: [Opt 31-138] Pushed 24 inverter(s) to 93 load pin(s).
|
|||
|
|
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
|||
|
|
Phase 1 Retarget | Checksum: 182ab964f
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10243 ; free virtual = 13247
|
|||
|
|
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
|||
|
|
|
|||
|
|
Phase 2 Constant propagation
|
|||
|
|
INFO: [Opt 31-138] Pushed 17 inverter(s) to 49 load pin(s).
|
|||
|
|
Phase 2 Constant propagation | Checksum: 1654929bf
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:26 ; elapsed = 00:00:18 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10243 ; free virtual = 13247
|
|||
|
|
INFO: [Opt 31-389] Phase Constant propagation created 1234 cells and removed 2976 cells
|
|||
|
|
|
|||
|
|
Phase 3 Sweep
|
|||
|
|
Phase 3 Sweep | Checksum: 1ac460825
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:33 ; elapsed = 00:01:25 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10247 ; free virtual = 13251
|
|||
|
|
INFO: [Opt 31-389] Phase Sweep created 9 cells and removed 31795 cells
|
|||
|
|
|
|||
|
|
Phase 4 BUFG optimization
|
|||
|
|
Phase 4 BUFG optimization | Checksum: 19b194d70
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:35 ; elapsed = 00:01:27 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10246 ; free virtual = 13250
|
|||
|
|
INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 2 cells.
|
|||
|
|
|
|||
|
|
Phase 5 Shift Register Optimization
|
|||
|
|
Phase 5 Shift Register Optimization | Checksum: 17315a67a
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:41 ; elapsed = 00:01:33 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10250 ; free virtual = 13255
|
|||
|
|
INFO: [Opt 31-389] Phase Shift Register Optimization created 1 cells and removed 0 cells
|
|||
|
|
|
|||
|
|
Phase 6 Post Processing Netlist
|
|||
|
|
Phase 6 Post Processing Netlist | Checksum: 18e7a450b
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:44 ; elapsed = 00:01:36 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10249 ; free virtual = 13254
|
|||
|
|
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 20 cells
|
|||
|
|
|
|||
|
|
Starting Connectivity Check Task
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.31 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10249 ; free virtual = 13254
|
|||
|
|
Ending Logic Optimization Task | Checksum: 1c7fc2267
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:45 ; elapsed = 00:01:37 . Memory (MB): peak = 4282.207 ; gain = 0.000 ; free physical = 10251 ; free virtual = 13255
|
|||
|
|
|
|||
|
|
Starting Power Optimization Task
|
|||
|
|
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
|||
|
|
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.163 | TNS=0.000 |
|
|||
|
|
Running Vector-less Activity Propagation...
|
|||
|
|
|
|||
|
|
Finished Running Vector-less Activity Propagation
|
|||
|
|
|
|||
|
|
|
|||
|
|
Starting PowerOpt Patch Enables Task
|
|||
|
|
INFO: [Pwropt 34-162] WRITE_MODE attribute of 1 BRAM(s) out of a total of 486 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
|||
|
|
INFO: [Pwropt 34-201] Structural ODC has moved 18 WE to EN ports
|
|||
|
|
Number of BRAM Ports augmented: 110 newly gated: 100 Total Ports: 972
|
|||
|
|
Ending PowerOpt Patch Enables Task | Checksum: 98fba02d
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9983 ; free virtual = 12991
|
|||
|
|
Ending Power Optimization Task | Checksum: 98fba02d
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:24 ; elapsed = 00:00:57 . Memory (MB): peak = 5080.711 ; gain = 798.504 ; free physical = 10167 ; free virtual = 13175
|
|||
|
|
|
|||
|
|
Starting Final Cleanup Task
|
|||
|
|
|
|||
|
|
Starting Logic Optimization Task
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
Ending Logic Optimization Task | Checksum: 11bfdf046
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10174 ; free virtual = 13183
|
|||
|
|
Ending Final Cleanup Task | Checksum: 11bfdf046
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10174 ; free virtual = 13183
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
171 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
opt_design completed successfully
|
|||
|
|
opt_design: Time (s): cpu = 00:04:52 ; elapsed = 00:02:55 . Memory (MB): peak = 5080.711 ; gain = 798.504 ; free physical = 10174 ; free virtual = 13183
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Writing placer database...
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Write XDEF Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.11 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10150 ; free virtual = 13166
|
|||
|
|
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_opt.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:46 ; elapsed = 00:00:40 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10129 ; free virtual = 13174
|
|||
|
|
INFO: [runtcl-4] Executing : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
|
|||
|
|
Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_opted.rpt.
|
|||
|
|
report_drc completed successfully
|
|||
|
|
report_drc: Time (s): cpu = 00:00:20 ; elapsed = 00:00:10 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10103 ; free virtual = 13149
|
|||
|
|
Command: place_design -directive Explore
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
|||
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
Running DRC as a precondition to command place_design
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
|
|||
|
|
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/ENBWREN (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[0] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[1] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1 has an input control pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/queue_reg_1/WEBWE[2] (net: nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/converter_rx/nf_converter/input_fifo/fifo/wr_en) which is driven by a register (axi_clocking_i/clk_wiz_i/inst/seq_reg1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings
|
|||
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
|
|||
|
|
Starting Placer Task
|
|||
|
|
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.
|
|||
|
|
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
|
|||
|
|
|
|||
|
|
Phase 1 Placer Initialization
|
|||
|
|
|
|||
|
|
Phase 1.1 Placer Initialization Netlist Sorting
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10101 ; free virtual = 13147
|
|||
|
|
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9ff384e5
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.27 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10100 ; free virtual = 13147
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.20 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 10094 ; free virtual = 13141
|
|||
|
|
|
|||
|
|
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
|
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
|
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
|
WARNING: [Place 30-568] A LUT 'control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
|
WARNING: [Place 30-139] Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
|||
|
|
|
|||
|
|
control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23
|
|||
|
|
control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
|
|||
|
|
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: bac26f65
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:57 ; elapsed = 00:00:30 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9889 ; free virtual = 12940
|
|||
|
|
|
|||
|
|
Phase 1.3 Build Placer Netlist Model
|
|||
|
|
Phase 1.3 Build Placer Netlist Model | Checksum: 19b30d1ca
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:01 ; elapsed = 00:00:56 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9594 ; free virtual = 12645
|
|||
|
|
|
|||
|
|
Phase 1.4 Constrain Clocks/Macros
|
|||
|
|
Phase 1.4 Constrain Clocks/Macros | Checksum: 19b30d1ca
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:02 ; elapsed = 00:00:57 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9594 ; free virtual = 12645
|
|||
|
|
Phase 1 Placer Initialization | Checksum: 19b30d1ca
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:02 ; elapsed = 00:00:57 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9593 ; free virtual = 12644
|
|||
|
|
|
|||
|
|
Phase 2 Global Placement
|
|||
|
|
|
|||
|
|
Phase 2.1 Floorplanning
|
|||
|
|
Phase 2.1 Floorplanning | Checksum: c6d613c2
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:35 ; elapsed = 00:01:08 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9490 ; free virtual = 12541
|
|||
|
|
|
|||
|
|
Phase 2.2 Physical Synthesis In Placer
|
|||
|
|
WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins.
|
|||
|
|
INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization.
|
|||
|
|
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_reset_i/cpllreset. Replicated 13 times.
|
|||
|
|
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/SS[0]. Replicated 11 times.
|
|||
|
|
WARNING: [Physopt 32-894] Found a constraint with the -through option on pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/w_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins.
|
|||
|
|
INFO: [Physopt 32-232] Optimized 2 nets. Created 24 new instances.
|
|||
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 24 new cells, deleted 0 existing cell and moved 0 existing cell
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.29 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9407 ; free virtual = 12460
|
|||
|
|
INFO: [Physopt 32-64] No nets found for fanout-optimization.
|
|||
|
|
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
|||
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_2[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__3 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_0_i_1__3_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_0_i_1__3 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_0[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__1 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/D[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_3__3 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3_i_1 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/wea[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/Addr1_i[1] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst_i_4__0 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/gen_wr_b.gen_word_narrow.mem_reg_0_1[0] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Update_inst/realmain_v4_networks_0_t_Randmod4_inst/xpm_memory_tdpram_inst_i_1__2 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/Addr3_i[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst_i_2__0 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].metadata_fifo/fifo/metadata_wr_en[4] could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].metadata_fifo/fifo/queue_reg_0_i_1__8 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst_i_2_n_0 could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst_i_2 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/Addr1_i[3] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst_i_2__1 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/Addr2_i[2] could not be optimized because driver nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst_i_3__2 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_3_i_1__0_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_3_i_1__0 could not be replicated
|
|||
|
|
INFO: [Physopt 32-117] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_23_i_1_n_0 could not be optimized because driver nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[4].output_fifo/fifo/queue_reg_23_i_1 could not be replicated
|
|||
|
|
INFO: [Physopt 32-68] No nets found for critical-cell optimization.
|
|||
|
|
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
|||
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.20 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9414 ; free virtual = 12467
|
|||
|
|
|
|||
|
|
Summary of Physical Synthesis Optimizations
|
|||
|
|
============================================
|
|||
|
|
|
|||
|
|
|
|||
|
|
-----------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
|||
|
|
-----------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Very High Fanout | 24 | 0 | 2 | 0 | 1 | 00:00:02 |
|
|||
|
|
| Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| Total | 24 | 0 | 2 | 0 | 3 | 00:00:03 |
|
|||
|
|
-----------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
|
|||
|
|
Phase 2.2 Physical Synthesis In Placer | Checksum: a1c4c65b
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:07:10 ; elapsed = 00:02:59 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9406 ; free virtual = 12459
|
|||
|
|
Phase 2 Global Placement | Checksum: 18f96503a
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:07:19 ; elapsed = 00:03:03 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9477 ; free virtual = 12531
|
|||
|
|
|
|||
|
|
Phase 3 Detail Placement
|
|||
|
|
|
|||
|
|
Phase 3.1 Commit Multi Column Macros
|
|||
|
|
Phase 3.1 Commit Multi Column Macros | Checksum: 18f96503a
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:07:20 ; elapsed = 00:03:04 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9476 ; free virtual = 12529
|
|||
|
|
|
|||
|
|
Phase 3.2 Commit Most Macros & LUTRAMs
|
|||
|
|
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1a2742584
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:08:20 ; elapsed = 00:03:24 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9446 ; free virtual = 12500
|
|||
|
|
|
|||
|
|
Phase 3.3 Area Swap Optimization
|
|||
|
|
Phase 3.3 Area Swap Optimization | Checksum: 17ba149d3
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:08:22 ; elapsed = 00:03:26 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9445 ; free virtual = 12499
|
|||
|
|
|
|||
|
|
Phase 3.4 Pipeline Register Optimization
|
|||
|
|
Phase 3.4 Pipeline Register Optimization | Checksum: 118e960d4
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:08:23 ; elapsed = 00:03:26 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9445 ; free virtual = 12499
|
|||
|
|
|
|||
|
|
Phase 3.5 Timing Path Optimizer
|
|||
|
|
Phase 3.5 Timing Path Optimizer | Checksum: 118e960d4
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:08:23 ; elapsed = 00:03:26 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9445 ; free virtual = 12499
|
|||
|
|
|
|||
|
|
Phase 3.6 Fast Optimization
|
|||
|
|
Phase 3.6 Fast Optimization | Checksum: 1707d8e40
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:08:25 ; elapsed = 00:03:28 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9446 ; free virtual = 12500
|
|||
|
|
|
|||
|
|
Phase 3.7 Small Shape Detail Placement
|
|||
|
|
Phase 3.7 Small Shape Detail Placement | Checksum: 13da19a18
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:09 ; elapsed = 00:04:08 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9298 ; free virtual = 12351
|
|||
|
|
|
|||
|
|
Phase 3.8 Re-assign LUT pins
|
|||
|
|
Phase 3.8 Re-assign LUT pins | Checksum: 193238061
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:13 ; elapsed = 00:04:12 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9304 ; free virtual = 12358
|
|||
|
|
|
|||
|
|
Phase 3.9 Pipeline Register Optimization
|
|||
|
|
Phase 3.9 Pipeline Register Optimization | Checksum: d40b202e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:14 ; elapsed = 00:04:14 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9303 ; free virtual = 12357
|
|||
|
|
Phase 3 Detail Placement | Checksum: d40b202e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:15 ; elapsed = 00:04:14 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9304 ; free virtual = 12357
|
|||
|
|
|
|||
|
|
Phase 4 Post Placement Optimization and Clean-Up
|
|||
|
|
|
|||
|
|
Phase 4.1 Post Commit Optimization
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
|
|||
|
|
Phase 4.1.1 Post Placement Optimization
|
|||
|
|
Post Placement Optimization Initialization | Checksum: c8296051
|
|||
|
|
|
|||
|
|
Phase 4.1.1.1 BUFG Insertion
|
|||
|
|
INFO: [Place 46-33] Processed net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[2].output_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-33] Processed net nf_datapath_0/input_arbiter_v1_0/inst/in_arb_queues[3].in_arb_fifo/fifo/SR[0], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-33] Processed net nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-33] Processed net nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-33] Processed net nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-33] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_rst/sync1_r[5], BUFG insertion was skipped due to placement/routing conflicts.
|
|||
|
|
INFO: [Place 46-31] BUFG insertion identified 6 candidate nets, 0 success, 6 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
|
|||
|
|
Phase 4.1.1.1 BUFG Insertion | Checksum: c8296051
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:10:18 ; elapsed = 00:04:32 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9422 ; free virtual = 12475
|
|||
|
|
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.096. For the most accurate timing information please run report_timing.
|
|||
|
|
Phase 4.1.1 Post Placement Optimization | Checksum: 10b11ac44
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:20 ; elapsed = 00:06:49 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9396 ; free virtual = 12449
|
|||
|
|
Phase 4.1 Post Commit Optimization | Checksum: 10b11ac44
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:20 ; elapsed = 00:06:50 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9396 ; free virtual = 12449
|
|||
|
|
|
|||
|
|
Phase 4.2 Post Placement Cleanup
|
|||
|
|
Phase 4.2 Post Placement Cleanup | Checksum: 10b11ac44
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:22 ; elapsed = 00:06:51 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9411 ; free virtual = 12465
|
|||
|
|
|
|||
|
|
Phase 4.3 Placer Reporting
|
|||
|
|
Phase 4.3 Placer Reporting | Checksum: 10b11ac44
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:23 ; elapsed = 00:06:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9412 ; free virtual = 12466
|
|||
|
|
|
|||
|
|
Phase 4.4 Final Placement Cleanup
|
|||
|
|
Phase 4.4 Final Placement Cleanup | Checksum: ca7172b5
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:24 ; elapsed = 00:06:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9412 ; free virtual = 12466
|
|||
|
|
Phase 4 Post Placement Optimization and Clean-Up | Checksum: ca7172b5
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:25 ; elapsed = 00:06:53 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9412 ; free virtual = 12465
|
|||
|
|
Ending Placer Task | Checksum: c3a2ca39
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:25 ; elapsed = 00:06:53 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9651 ; free virtual = 12705
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
224 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
place_design completed successfully
|
|||
|
|
place_design: Time (s): cpu = 00:13:38 ; elapsed = 00:07:04 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9652 ; free virtual = 12705
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Writing placer database...
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Write XDEF Complete: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9347 ; free virtual = 12638
|
|||
|
|
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_placed.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:53 ; elapsed = 00:00:42 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9572 ; free virtual = 12689
|
|||
|
|
INFO: [runtcl-4] Executing : report_io -file top_io_placed.rpt
|
|||
|
|
report_io: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.34 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9531 ; free virtual = 12648
|
|||
|
|
INFO: [runtcl-4] Executing : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb
|
|||
|
|
report_utilization: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9568 ; free virtual = 12685
|
|||
|
|
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_control_sets_placed.rpt
|
|||
|
|
report_control_sets: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.81 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9565 ; free virtual = 12684
|
|||
|
|
Command: phys_opt_design -directive ExploreWithHoldFix
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: ExploreWithHoldFix
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9527 ; free virtual = 12646
|
|||
|
|
|
|||
|
|
Starting Physical Synthesis Task
|
|||
|
|
|
|||
|
|
Phase 1 Physical Synthesis Initialization
|
|||
|
|
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.096 | TNS=0.000 |
|
|||
|
|
Phase 1 Physical Synthesis Initialization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:10 ; elapsed = 00:00:20 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9452 ; free virtual = 12571
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.096 | TNS=0.000 |
|
|||
|
|
|
|||
|
|
Phase 2 Fanout Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Fanout Optimization was not performed.
|
|||
|
|
Phase 2 Fanout Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 3 Placement Based Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Placement Based Optimization was not performed.
|
|||
|
|
Phase 3 Placement Based Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 4 MultiInst Placement Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. MultiInst Placement Optimization was not performed.
|
|||
|
|
Phase 4 MultiInst Placement Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 5 Rewire
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Rewire was not performed.
|
|||
|
|
Phase 5 Rewire | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 6 Critical Cell Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Critical Cell Optimization was not performed.
|
|||
|
|
Phase 6 Critical Cell Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 7 Fanout Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Fanout Optimization was not performed.
|
|||
|
|
Phase 7 Fanout Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 8 Placement Based Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Placement Based Optimization was not performed.
|
|||
|
|
Phase 8 Placement Based Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 9 MultiInst Placement Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. MultiInst Placement Optimization was not performed.
|
|||
|
|
Phase 9 MultiInst Placement Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 10 Rewire
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Rewire was not performed.
|
|||
|
|
Phase 10 Rewire | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 11 Critical Cell Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Critical Cell Optimization was not performed.
|
|||
|
|
Phase 11 Critical Cell Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 12 Slr Crossing Optimization
|
|||
|
|
Phase 12 Slr Crossing Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 13 Fanout Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Fanout Optimization was not performed.
|
|||
|
|
Phase 13 Fanout Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 14 Placement Based Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Placement Based Optimization was not performed.
|
|||
|
|
Phase 14 Placement Based Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 15 MultiInst Placement Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. MultiInst Placement Optimization was not performed.
|
|||
|
|
Phase 15 MultiInst Placement Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 16 Rewire
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Rewire was not performed.
|
|||
|
|
Phase 16 Rewire | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 17 Critical Cell Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Critical Cell Optimization was not performed.
|
|||
|
|
Phase 17 Critical Cell Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 18 DSP Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
|||
|
|
Phase 18 DSP Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 19 BRAM Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
|||
|
|
Phase 19 BRAM Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 20 URAM Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
|
|||
|
|
Phase 20 URAM Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 21 Shift Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
|||
|
|
Phase 21 Shift Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 22 DSP Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
|||
|
|
Phase 22 DSP Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 23 BRAM Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
|||
|
|
Phase 23 BRAM Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 24 URAM Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
|
|||
|
|
Phase 24 URAM Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 25 Shift Register Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
|||
|
|
Phase 25 Shift Register Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 26 Critical Pin Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Critical Pin Optimization was not performed.
|
|||
|
|
Phase 26 Critical Pin Optimization | Checksum: 1bc8d96d6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:11 ; elapsed = 00:00:21 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9443 ; free virtual = 12562
|
|||
|
|
|
|||
|
|
Phase 27 Very High Fanout Optimization
|
|||
|
|
INFO: [Physopt 32-76] Pass 1. Identified 71 candidate nets for fanout optimization.
|
|||
|
|
INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/rRst was not replicated.
|
|||
|
|
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
|
|||
|
|
INFO: [Physopt 32-572] Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/rRst was not replicated.
|
|||
|
|
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/wr_en. Replicated 1 times.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/valid_6. Replicated 1 times.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_1/valid_6. Replicated 1 times.
|
|||
|
|
INFO: [Physopt 32-81] Processed net control_sub_i/dma_sub/pcie3_7x_1/inst/user_reset. Replicated 2 times.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/valid_6. Replicated 1 times.
|
|||
|
|
INFO: [Physopt 32-572] Net nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_RESET_clk_line/clk_line_rst_high was not replicated.
|
|||
|
|
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_datapath_0/input_arbiter_v1_0/inst/in_arb_queues[3].in_arb_fifo/fifo/SR[0]. Replicated 8 times.
|
|||
|
|
INFO: [Physopt 32-572] Net nf_datapath_0/bram_output_queues_1/inst/sss_output_queues[2].output_fifo/fifo/SR[0] was not replicated.
|
|||
|
|
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
|
|||
|
|
INFO: [Physopt 32-81] Processed net nf_10g_interface_0/inst/nf_10g_interface_shared_cpu_regs_inst/id_reg1. Replicated 1 times.
|
|||
|
|
INFO: [Physopt 32-232] Optimized 7 nets. Created 15 new instances.
|
|||
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 7 nets or cells. Created 15 new cells, deleted 0 existing cell and moved 0 existing cell
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.096 | TNS=0.000 |
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.33 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9438 ; free virtual = 12558
|
|||
|
|
Phase 27 Very High Fanout Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:21 ; elapsed = 00:00:51 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9438 ; free virtual = 12558
|
|||
|
|
|
|||
|
|
Phase 28 Placement Based Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Placement Based Optimization was not performed.
|
|||
|
|
Phase 28 Placement Based Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:21 ; elapsed = 00:00:51 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9438 ; free virtual = 12558
|
|||
|
|
|
|||
|
|
Phase 29 MultiInst Placement Optimization
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. MultiInst Placement Optimization was not performed.
|
|||
|
|
Phase 29 MultiInst Placement Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:21 ; elapsed = 00:00:51 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9438 ; free virtual = 12558
|
|||
|
|
|
|||
|
|
Phase 30 Critical Path Optimization
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.096 | TNS=0.000 |
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.096 | TNS=0.000 |
|
|||
|
|
Phase 30 Critical Path Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:24 ; elapsed = 00:00:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9439 ; free virtual = 12558
|
|||
|
|
|
|||
|
|
Phase 31 BRAM Enable Optimization
|
|||
|
|
Phase 31 BRAM Enable Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:25 ; elapsed = 00:00:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9439 ; free virtual = 12558
|
|||
|
|
|
|||
|
|
Phase 32 Hold Fix Optimization
|
|||
|
|
INFO: [Physopt 32-668] Estimated Timing Summary | WNS=0.096 | TNS=0.000 | WHS=-0.404 | THS=-369.561 |
|
|||
|
|
INFO: [Physopt 32-45] Identified 36 candidate nets for hold slack optimization.
|
|||
|
|
INFO: [Physopt 32-234] Optimized 36 nets. Inserted 0 new ZHOLD_DELAYs. Calibrated 0 existing ZHOLD_DELAYs. Inserted 36 buffers.
|
|||
|
|
|
|||
|
|
INFO: [Physopt 32-668] Estimated Timing Summary | WNS=0.096 | TNS=0.000 | WHS=-0.250 | THS=-358.993 |
|
|||
|
|
Phase 32 Hold Fix Optimization | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:59 ; elapsed = 00:00:59 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9392 ; free virtual = 12511
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.28 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9399 ; free virtual = 12519
|
|||
|
|
INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=0.096 | TNS=0.000 | WHS=-0.250 | THS=-358.993 |
|
|||
|
|
|
|||
|
|
Summary of Physical Synthesis Optimizations
|
|||
|
|
============================================
|
|||
|
|
|
|||
|
|
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Fanout | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Placement Based | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| MultiInst Placement | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Rewire | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Critical Cell | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Slr Crossing | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| BRAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| URAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Shift Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Critical Pin | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Very High Fanout | 0.000 | 0.000 | 15 | 0 | 7 | 4 | 1 | 00:00:29 |
|
|||
|
|
| BRAM Enable | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| Critical Path | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| Total | 0.000 | 0.000 | 15 | 0 | 7 | 4 | 4 | 00:00:30 |
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
|
|||
|
|
Summary of Hold Fix Optimizations
|
|||
|
|
=================================
|
|||
|
|
|
|||
|
|
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Optimization | WHS Gain (ns) | THS Gain (ns) | Added LUTs | Added FFs | Optimized Nets | Dont Touch | Iterations | Elapsed |
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| LUT1 and ZHOLD Insertion | 0.154 | 10.568 | 36 | 0 | 36 | 4 | 1 | 00:00:03 |
|
|||
|
|
| Total | 0.154 | 10.568 | 36 | 0 | 36 | 4 | 1 | 00:00:03 |
|
|||
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
|
|||
|
|
Ending Physical Synthesis Task | Checksum: 10787f6b9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:00 ; elapsed = 00:01:00 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9399 ; free virtual = 12518
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
283 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
phys_opt_design completed successfully
|
|||
|
|
phys_opt_design: Time (s): cpu = 00:04:11 ; elapsed = 00:01:16 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9508 ; free virtual = 12627
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Writing placer database...
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Write XDEF Complete: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9246 ; free virtual = 12598
|
|||
|
|
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_physopt.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:55 ; elapsed = 00:00:43 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9468 ; free virtual = 12649
|
|||
|
|
Command: route_design
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
|||
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
Running DRC as a precondition to command route_design
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
WARNING: [DRC PLCK-18] Clock Placer Checks: Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region.
|
|||
|
|
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
|||
|
|
|
|||
|
|
control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i (GTHE2_CHANNEL.TXOUTCLK) is locked to GTHE2_CHANNEL_X1Y23
|
|||
|
|
control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
|
|||
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
|
|||
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
|
|||
|
|
|
|||
|
|
Starting Routing Task
|
|||
|
|
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
|
|||
|
|
Checksum: PlaceDB: b96faddb ConstDB: 0 ShapeSum: accbbc0c RouteDB: 0
|
|||
|
|
|
|||
|
|
Phase 1 Build RT Design
|
|||
|
|
Phase 1 Build RT Design | Checksum: 10d97bed8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:28 ; elapsed = 00:00:47 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9056 ; free virtual = 12238
|
|||
|
|
Post Restoration Checksum: NetGraph: 6da0886e NumContArr: 9ff7366a Constraints: 0 Timing: 0
|
|||
|
|
|
|||
|
|
Phase 2 Router Initialization
|
|||
|
|
|
|||
|
|
Phase 2.1 Create Timer
|
|||
|
|
Phase 2.1 Create Timer | Checksum: 10d97bed8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:33 ; elapsed = 00:00:51 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9059 ; free virtual = 12241
|
|||
|
|
|
|||
|
|
Phase 2.2 Fix Topology Constraints
|
|||
|
|
Phase 2.2 Fix Topology Constraints | Checksum: 10d97bed8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:34 ; elapsed = 00:00:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8990 ; free virtual = 12173
|
|||
|
|
|
|||
|
|
Phase 2.3 Pre Route Cleanup
|
|||
|
|
Phase 2.3 Pre Route Cleanup | Checksum: 10d97bed8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:34 ; elapsed = 00:00:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8990 ; free virtual = 12173
|
|||
|
|
Number of Nodes with overlaps = 0
|
|||
|
|
|
|||
|
|
Phase 2.4 Update Timing
|
|||
|
|
Phase 2.4 Update Timing | Checksum: 19018a1ee
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:54 ; elapsed = 00:01:20 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8926 ; free virtual = 12109
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.227 | TNS=0.000 | WHS=-0.432 | THS=-10847.808|
|
|||
|
|
|
|||
|
|
|
|||
|
|
Phase 2.5 Update Timing for Bus Skew
|
|||
|
|
|
|||
|
|
Phase 2.5.1 Update Timing
|
|||
|
|
Phase 2.5.1 Update Timing | Checksum: 1199e0fe2
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:49 ; elapsed = 00:01:32 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8891 ; free virtual = 12075
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.227 | TNS=0.000 | WHS=N/A | THS=N/A |
|
|||
|
|
|
|||
|
|
Phase 2.5 Update Timing for Bus Skew | Checksum: 1803077f9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:49 ; elapsed = 00:01:33 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8884 ; free virtual = 12068
|
|||
|
|
Phase 2 Router Initialization | Checksum: 19a795a20
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:50 ; elapsed = 00:01:33 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8884 ; free virtual = 12068
|
|||
|
|
|
|||
|
|
Phase 3 Initial Routing
|
|||
|
|
Phase 3 Initial Routing | Checksum: 13cafeaba
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:06:33 ; elapsed = 00:02:17 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8850 ; free virtual = 12034
|
|||
|
|
|
|||
|
|
Phase 4 Rip-up And Reroute
|
|||
|
|
|
|||
|
|
Phase 4.1 Global Iteration 0
|
|||
|
|
Number of Nodes with overlaps = 12175
|
|||
|
|
Number of Nodes with overlaps = 1084
|
|||
|
|
Number of Nodes with overlaps = 216
|
|||
|
|
Number of Nodes with overlaps = 60
|
|||
|
|
Number of Nodes with overlaps = 14
|
|||
|
|
Number of Nodes with overlaps = 2
|
|||
|
|
Number of Nodes with overlaps = 0
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.113 | TNS=0.000 | WHS=N/A | THS=N/A |
|
|||
|
|
|
|||
|
|
Phase 4.1 Global Iteration 0 | Checksum: 152d3fe99
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:10:51 ; elapsed = 00:03:30 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8861 ; free virtual = 12045
|
|||
|
|
Phase 4 Rip-up And Reroute | Checksum: 152d3fe99
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:10:51 ; elapsed = 00:03:30 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8861 ; free virtual = 12045
|
|||
|
|
|
|||
|
|
Phase 5 Delay and Skew Optimization
|
|||
|
|
|
|||
|
|
Phase 5.1 Delay CleanUp
|
|||
|
|
|
|||
|
|
Phase 5.1.1 Update Timing
|
|||
|
|
Phase 5.1.1 Update Timing | Checksum: c1e010b3
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:04 ; elapsed = 00:03:34 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8855 ; free virtual = 12039
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.186 | TNS=0.000 | WHS=N/A | THS=N/A |
|
|||
|
|
|
|||
|
|
Phase 5.1 Delay CleanUp | Checksum: 18c220186
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:05 ; elapsed = 00:03:34 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8860 ; free virtual = 12044
|
|||
|
|
|
|||
|
|
Phase 5.2 Clock Skew Optimization
|
|||
|
|
Phase 5.2 Clock Skew Optimization | Checksum: 18c220186
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:05 ; elapsed = 00:03:34 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8861 ; free virtual = 12045
|
|||
|
|
Phase 5 Delay and Skew Optimization | Checksum: 18c220186
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:05 ; elapsed = 00:03:35 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8861 ; free virtual = 12045
|
|||
|
|
|
|||
|
|
Phase 6 Post Hold Fix
|
|||
|
|
|
|||
|
|
Phase 6.1 Hold Fix Iter
|
|||
|
|
|
|||
|
|
Phase 6.1.1 Update Timing
|
|||
|
|
Phase 6.1.1 Update Timing | Checksum: 1a58fcf4a
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:20 ; elapsed = 00:03:39 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8862 ; free virtual = 12046
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.186 | TNS=0.000 | WHS=-0.180 | THS=-0.522 |
|
|||
|
|
|
|||
|
|
Phase 6.1 Hold Fix Iter | Checksum: 1c1ba59e3
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:22 ; elapsed = 00:03:39 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8842 ; free virtual = 12026
|
|||
|
|
Phase 6 Post Hold Fix | Checksum: 12f533860
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:23 ; elapsed = 00:03:40 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8842 ; free virtual = 12026
|
|||
|
|
|
|||
|
|
Phase 7 Route finalize
|
|||
|
|
|
|||
|
|
Router Utilization Summary
|
|||
|
|
Global Vertical Routing Utilization = 5.86655 %
|
|||
|
|
Global Horizontal Routing Utilization = 6.67007 %
|
|||
|
|
Routable Net Status*
|
|||
|
|
*Does not include unroutable nets such as driverless and loadless.
|
|||
|
|
Run report_route_status for detailed report.
|
|||
|
|
Number of Failed Nets = 0
|
|||
|
|
Number of Unrouted Nets = 0
|
|||
|
|
Number of Partially Routed Nets = 0
|
|||
|
|
Number of Node Overlaps = 0
|
|||
|
|
|
|||
|
|
Phase 7 Route finalize | Checksum: 1ec49cbbe
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:24 ; elapsed = 00:03:40 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8837 ; free virtual = 12021
|
|||
|
|
|
|||
|
|
Phase 8 Verifying routed nets
|
|||
|
|
|
|||
|
|
Verification completed successfully
|
|||
|
|
Phase 8 Verifying routed nets | Checksum: 1ec49cbbe
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:25 ; elapsed = 00:03:41 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8835 ; free virtual = 12019
|
|||
|
|
|
|||
|
|
Phase 9 Depositing Routes
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin nf_10g_interface_0/inst/nf_10g_interface_shared_i/axi_10g_ethernet_i/inst/xpcs/inst/ten_gig_eth_pcs_pma_gt_common_block/gthe2_common_0_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y9/GTNORTHREFCLK0
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y23/GTREFCLK1
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y5/GTREFCLK1
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y22/GTREFCLK1
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y21/GTREFCLK1
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y20/GTREFCLK1
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK0
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gth_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y4/GTSOUTHREFCLK0
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK0
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK0
|
|||
|
|
INFO: [Route 35-467] Router swapped GT pin control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/gth_channel.gthe2_channel_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK0
|
|||
|
|
Phase 9 Depositing Routes | Checksum: 1515d35bd
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:32 ; elapsed = 00:03:48 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8845 ; free virtual = 12029
|
|||
|
|
|
|||
|
|
Phase 10 Post Router Timing
|
|||
|
|
|
|||
|
|
Phase 10.1 Update Timing
|
|||
|
|
Phase 10.1 Update Timing | Checksum: 16170ac28
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:47 ; elapsed = 00:03:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8853 ; free virtual = 12037
|
|||
|
|
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.186 | TNS=0.000 | WHS=0.014 | THS=0.000 |
|
|||
|
|
|
|||
|
|
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
|||
|
|
Phase 10 Post Router Timing | Checksum: 16170ac28
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:47 ; elapsed = 00:03:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8853 ; free virtual = 12037
|
|||
|
|
INFO: [Route 35-16] Router Completed Successfully
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:47 ; elapsed = 00:03:52 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9011 ; free virtual = 12195
|
|||
|
|
|
|||
|
|
Routing Is Done.
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
313 Infos, 161 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
route_design completed successfully
|
|||
|
|
route_design: Time (s): cpu = 00:12:05 ; elapsed = 00:04:05 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 9011 ; free virtual = 12195
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Writing placer database...
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Write XDEF Complete: Time (s): cpu = 00:00:18 ; elapsed = 00:00:07 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8654 ; free virtual = 12132
|
|||
|
|
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_routed.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:57 ; elapsed = 00:00:44 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8920 ; free virtual = 12180
|
|||
|
|
INFO: [runtcl-4] Executing : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
|
|||
|
|
Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
INFO: [Coretcl 2-168] The results of DRC are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_drc_routed.rpt.
|
|||
|
|
report_drc completed successfully
|
|||
|
|
report_drc: Time (s): cpu = 00:00:39 ; elapsed = 00:00:13 . Memory (MB): peak = 5080.711 ; gain = 0.000 ; free physical = 8835 ; free virtual = 12095
|
|||
|
|
INFO: [runtcl-4] Executing : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
|
|||
|
|
Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [DRC 23-133] Running Methodology with 8 threads
|
|||
|
|
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_methodology_drc_routed.rpt.
|
|||
|
|
report_methodology completed successfully
|
|||
|
|
report_methodology: Time (s): cpu = 00:02:45 ; elapsed = 00:00:35 . Memory (MB): peak = 5178.754 ; gain = 98.043 ; free physical = 8059 ; free virtual = 11320
|
|||
|
|
INFO: [runtcl-4] Executing : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
|
|||
|
|
Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
Running Vector-less Activity Propagation...
|
|||
|
|
|
|||
|
|
Finished Running Vector-less Activity Propagation
|
|||
|
|
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
|
|||
|
|
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
|
|||
|
|
325 Infos, 162 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
report_power completed successfully
|
|||
|
|
report_power: Time (s): cpu = 00:01:14 ; elapsed = 00:00:31 . Memory (MB): peak = 5404.172 ; gain = 225.418 ; free physical = 7922 ; free virtual = 11199
|
|||
|
|
INFO: [runtcl-4] Executing : report_route_status -file top_route_status.rpt -pb top_route_status.pb
|
|||
|
|
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx
|
|||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
|
|||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
|||
|
|
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
|
|||
|
|
report_timing_summary: Time (s): cpu = 00:00:29 ; elapsed = 00:00:07 . Memory (MB): peak = 5425.145 ; gain = 20.973 ; free physical = 7864 ; free virtual = 11146
|
|||
|
|
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_incremental_reuse_routed.rpt
|
|||
|
|
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
|
|||
|
|
INFO: [runtcl-4] Executing : report_clock_utilization -file top_clock_utilization_routed.rpt
|
|||
|
|
report_clock_utilization: Time (s): cpu = 00:00:52 ; elapsed = 00:00:52 . Memory (MB): peak = 5425.145 ; gain = 0.000 ; free physical = 7860 ; free virtual = 11143
|
|||
|
|
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx
|
|||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
|
|||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
|||
|
|
Command: phys_opt_design -directive AggressiveExplore
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 99.3% nets are fully routed)
|
|||
|
|
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AggressiveExplore
|
|||
|
|
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
|
|||
|
|
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
341 Infos, 163 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
phys_opt_design completed successfully
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Writing placer database...
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Write XDEF Complete: Time (s): cpu = 00:00:17 ; elapsed = 00:00:07 . Memory (MB): peak = 5432.551 ; gain = 7.402 ; free physical = 7469 ; free virtual = 11048
|
|||
|
|
INFO: [Common 17-1381] The checkpoint '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/top_postroute_physopt.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:55 ; elapsed = 00:00:43 . Memory (MB): peak = 5432.551 ; gain = 7.402 ; free physical = 7748 ; free virtual = 11108
|
|||
|
|
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -warn_on_violation -file top_timing_summary_postroute_physopted.rpt -pb top_timing_summary_postroute_physopted.pb -rpx top_timing_summary_postroute_physopted.rpx
|
|||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
|
|||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
|||
|
|
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
|
|||
|
|
report_timing_summary: Time (s): cpu = 00:00:16 ; elapsed = 00:00:05 . Memory (MB): peak = 5464.551 ; gain = 32.000 ; free physical = 7739 ; free virtual = 11105
|
|||
|
|
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_postroute_physopted.rpt -pb top_bus_skew_postroute_physopted.pb -rpx top_bus_skew_postroute_physopted.rpx
|
|||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max, Timing Stage: Requireds.
|
|||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
Command: write_bitstream -force top.bit
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.
|
|||
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|
|||
|
|
Evaluation cores found in this design:
|
|||
|
|
IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features:
|
|||
|
|
IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
|
|||
|
|
IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
|
|||
|
|
IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
|
|||
|
|
IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features:
|
|||
|
|
IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
|
|||
|
|
IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
|
|||
|
|
IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
|
|||
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|
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|
|
Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
|
|||
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|
Running DRC as a precondition to command write_bitstream
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
|
|||
|
|
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
|
|||
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|||
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|||
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|
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|||
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|||
|
|
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
|||
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control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
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WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
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control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
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WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
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control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
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WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
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control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/axis_fifo_10g_tx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed).
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_25) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_26) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_27) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 51 Warnings, 103 Advisories
|
|||
|
|
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
|
|||
|
|
Loading data files...
|
|||
|
|
Loading site data...
|
|||
|
|
Loading route data...
|
|||
|
|
Processing options...
|
|||
|
|
Creating bitmap...
|
|||
|
|
Creating bitstream...
|
|||
|
|
Bitstream compression saved 136486912 bits.
|
|||
|
|
Writing bitstream ./top.bit...
|
|||
|
|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
498 Infos, 215 Warnings, 1 Critical Warnings and 0 Errors encountered.
|
|||
|
|
write_bitstream completed successfully
|
|||
|
|
write_bitstream: Time (s): cpu = 00:03:03 ; elapsed = 00:03:16 . Memory (MB): peak = 6174.973 ; gain = 710.422 ; free physical = 7700 ; free virtual = 11085
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 28 18:41:49 2019...
|
|||
|
|
|
|||
|
|
*** Running vivado
|
|||
|
|
with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace
|
|||
|
|
|
|||
|
|
|
|||
|
|
****** Vivado v2018.2 (64-bit)
|
|||
|
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|||
|
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
source top.tcl -notrace
|
|||
|
|
Command: open_checkpoint top_postroute_physopt.dcp
|
|||
|
|
|
|||
|
|
Starting open_checkpoint Task
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1176.738 ; gain = 0.000 ; free physical = 12175 ; free virtual = 15746
|
|||
|
|
INFO: [Netlist 29-17] Analyzing 4024 Unisim elements for replacement
|
|||
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|||
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
|
|||
|
|
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
|
|||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|||
|
|
INFO: [Timing 38-478] Restoring timing data from binary archive.
|
|||
|
|
INFO: [Timing 38-479] Binary timing data restore complete.
|
|||
|
|
INFO: [Project 1-856] Restoring constraints from binary archive.
|
|||
|
|
INFO: [Project 1-853] Binary constraint restore complete.
|
|||
|
|
Reading XDEF placement.
|
|||
|
|
Reading placer database...
|
|||
|
|
Reading XDEF routing.
|
|||
|
|
Read XDEF File: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3270.863 ; gain = 162.617 ; free physical = 10194 ; free virtual = 13766
|
|||
|
|
Restored from archive | CPU: 7.400000 secs | Memory: 174.191101 MB |
|
|||
|
|
Finished XDEF File Restore: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3270.863 ; gain = 162.617 ; free physical = 10194 ; free virtual = 13766
|
|||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|||
|
|
A total of 670 instances were transformed.
|
|||
|
|
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
|
|||
|
|
LUT6_2 => LUT6_2 (LUT5, LUT6): 79 instances
|
|||
|
|
RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 20 instances
|
|||
|
|
RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
|
|||
|
|
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 365 instances
|
|||
|
|
RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances
|
|||
|
|
RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 145 instances
|
|||
|
|
RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 24 instances
|
|||
|
|
SRLC16E => SRL16E: 1 instances
|
|||
|
|
|
|||
|
|
INFO: [Project 1-604] Checkpoint was created with Vivado v2018.2 (64-bit) build 2258646
|
|||
|
|
open_checkpoint: Time (s): cpu = 00:01:14 ; elapsed = 00:02:16 . Memory (MB): peak = 3270.863 ; gain = 2094.125 ; free physical = 10242 ; free virtual = 13813
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/realmain_v4_networks_0/realmain_v4_networks_0_t_Wrap_inst/realmain_v4_networks_0_t_IntTop_inst/realmain_v4_networks_0_t_Lookup_inst/realmain_v4_networks_0_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/wfqws46340wyslrwid2yow_1831/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/q7gvskyh9rdb9henjto295zvigo9_974/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/blb6zofu4m1iwfz7b9fn78j_619/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/xdgk72zc6lz2v1f6_638/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/izzp83m68hsu2ozh14472qcg_421/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/bg3rgtuwucqmjzmclir9q2k5ps_794/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xe63wyalaxqi3pjbu72rro2_1653/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/uswzetjhoap7d9wrf4i9dhm9lwzf_2235/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/u34kvw4geng8wp39esl2j727nx7c0_647/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/y06wki9vylrmylq2v_2571/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xw49r6188i46a9wjd0nkk1oksp_526/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
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|
INFO: [Memdata 28-167] Found XPM memory block nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/m150wixgtma9i0g8y0g7_645/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
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INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-208] The XPM instance: <nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <nf_datapath_0/nf_sume_sdnet_wrapper_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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Command: write_bitstream -force top.bit
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Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
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CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.
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Evaluation cores found in this design:
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IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features:
|
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IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
|
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IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
|
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IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
|
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IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features:
|
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IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
|
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IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
|
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IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
|
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Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
|
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Running DRC as a precondition to command write_bitstream
|
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INFO: [IP_Flow 19-234] Refreshing IP repositories
|
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INFO: [IP_Flow 19-1704] No user IP repositories specified
|
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
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INFO: [DRC 23-27] Running DRC with 8 threads
|
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WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
|
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WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
|
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WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
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WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
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WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
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WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
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WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
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control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
|
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WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
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|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
|
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WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
|
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WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
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|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed).
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_25) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_26) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_27) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 51 Warnings, 103 Advisories
|
|||
|
|
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/app.elf
|
|||
|
|
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
|
|||
|
|
Loading data files...
|
|||
|
|
Loading site data...
|
|||
|
|
Loading route data...
|
|||
|
|
Processing options...
|
|||
|
|
Creating bitmap...
|
|||
|
|
Creating bitstream...
|
|||
|
|
Bitstream compression saved 136027840 bits.
|
|||
|
|
Writing bitstream ./top.bit...
|
|||
|
|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
164 Infos, 51 Warnings, 1 Critical Warnings and 0 Errors encountered.
|
|||
|
|
write_bitstream completed successfully
|
|||
|
|
write_bitstream: Time (s): cpu = 00:03:15 ; elapsed = 00:03:20 . Memory (MB): peak = 4280.266 ; gain = 1001.398 ; free physical = 10023 ; free virtual = 13611
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 28 18:50:43 2019...
|
|||
|
|
[Sun Jul 28 18:50:43 2019] impl_1 finished
|
|||
|
|
wait_on_run: Time (s): cpu = 00:04:37 ; elapsed = 00:05:43 . Memory (MB): peak = 2176.348 ; gain = 0.000 ; free physical = 12312 ; free virtual = 15902
|
|||
|
|
# open_run impl_1
|
|||
|
|
INFO: [Netlist 29-17] Analyzing 4024 Unisim elements for replacement
|
|||
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|||
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
|
|||
|
|
INFO: [Device 21-403] Loading part xc7vx690tffg1761-3
|
|||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|||
|
|
INFO: [Timing 38-478] Restoring timing data from binary archive.
|
|||
|
|
INFO: [Timing 38-479] Binary timing data restore complete.
|
|||
|
|
INFO: [Project 1-856] Restoring constraints from binary archive.
|
|||
|
|
INFO: [Project 1-853] Binary constraint restore complete.
|
|||
|
|
Reading XDEF placement.
|
|||
|
|
Reading placer database...
|
|||
|
|
Reading XDEF routing.
|
|||
|
|
Read XDEF File: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3478.246 ; gain = 161.617 ; free physical = 10409 ; free virtual = 13996
|
|||
|
|
Restored from archive | CPU: 7.340000 secs | Memory: 174.191803 MB |
|
|||
|
|
Finished XDEF File Restore: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3478.246 ; gain = 161.617 ; free physical = 10409 ; free virtual = 13996
|
|||
|
|
Generating merged BMM file for the design top 'top'...
|
|||
|
|
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/app.elf
|
|||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|||
|
|
A total of 670 instances were transformed.
|
|||
|
|
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
|
|||
|
|
LUT6_2 => LUT6_2 (LUT5, LUT6): 79 instances
|
|||
|
|
RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 20 instances
|
|||
|
|
RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
|
|||
|
|
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 365 instances
|
|||
|
|
RAM32X1D => RAM32X1D (RAMD32, RAMD32): 2 instances
|
|||
|
|
RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 145 instances
|
|||
|
|
RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 24 instances
|
|||
|
|
SRLC16E => SRL16E: 1 instances
|
|||
|
|
|
|||
|
|
open_run: Time (s): cpu = 00:01:13 ; elapsed = 00:02:13 . Memory (MB): peak = 3478.246 ; gain = 1301.898 ; free physical = 10456 ; free virtual = 14043
|
|||
|
|
# write_bitstream -force ../bitfiles/$design.bit
|
|||
|
|
Command: write_bitstream -force ../bitfiles/simple_sume_switch.bit
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx690t'
|
|||
|
|
CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.
|
|||
|
|
|
|||
|
|
Evaluation cores found in this design:
|
|||
|
|
IP core 'axi_10g_ethernet_nonshared' (bd_7ad4) was generated with multiple features:
|
|||
|
|
IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
|
|||
|
|
IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
|
|||
|
|
IP core 'bd_7ad4_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
|
|||
|
|
IP core 'axi_10g_ethernet_shared' (bd_a1aa) was generated with multiple features:
|
|||
|
|
IP feature 'ten_gig_eth_mac@2016.04' was enabled using a bought license.
|
|||
|
|
IP feature 'ten_gig_eth_pcs_pma_basekr@2015.04' was enabled using a design_linking license.
|
|||
|
|
IP core 'bd_a1aa_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
|
|||
|
|
|
|||
|
|
Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
|
|||
|
|
Running DRC as a precondition to command write_bitstream
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 8 threads
|
|||
|
|
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
|
|||
|
|
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
|
|||
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|||
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|||
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|||
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/wDirSet is a gated clock net sourced by a combinational pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2/O, cell control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|||
|
|
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
|
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
|
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/wrPtrFull/rDir_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/rxPort/mainFifo/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
|
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/wrPtrFull/rDir_i_1__2 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are:
|
|||
|
|
control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/asyncCompare/rDir_reg {FDCE}
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|||
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[1].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[2].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txc_engine_inst/txc_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[3].fifo_inst_/mem/E[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg/ENBWREN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/engine_layer_inst/tx_engine_ultrascale_inst/txr_engine_inst/txr_engine_inst/tx_data_pipeline_inst/txdf_inst/gen_regs_fifos[0].fifo_inst_/mem/rMemory_reg_0[0]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7 has an input control pin control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/queue_reg_7/ENARDEN (net: control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axis_attachment/axis_to_riffa_conv/rx_riffa_fifo/fifo/wr_en0) which is driven by a register (control_sub_i/dma_sub/axis_fifo_10g_rx/inst/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[10] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[5]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[11] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[6]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[12] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[7]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[13] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[8]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_tlp_tph_tbl_7vx_i/reg_cfg_tph_stt_read_data_valid_o_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo has an input control pin control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo/ADDRARDADDR[9] (net: control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/raddr0_i[4]) which is driven by a register (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_init_ctrl_7vx_i/FSM_onehot_reg_state_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC RTSTAT-10] No routable loads: 350 net(s) have no routable loads. The problem bus(es) and/or net(s) are nf_10g_interface_0/inst/nf_10g_interface_shared_i/fifo_generator_shared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_3/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/fifo_generator_nonshared_status_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_2/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_1/inst/nf_10g_interface_block_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/rx_fifo_intf/rx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/tag_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/r_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa_axi_lite_attachment/ar_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, nf_10g_interface_0/inst/nf_10g_interface_shared_i/xge_attachment/tx_fifo_intf/tx_info_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 70 listed).
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/req_fifo/U0/RAMB18E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_BRIDGER_for_realmain_v4_networks_0_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_19) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[0].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/nf_riffa_dma_1/inst/riffa/riffa_inst/channels[1].channel/channel/txPort/gate/fifo/mem/rRAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[0].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[1].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[2].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (control_sub_i/dma_sub/pcie3_7x_1/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk1.CPL_FIFO_16KB.U0/SPEED_250MHz.RAMB36E1[3].u_fifo) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/f2xqwifp1sq1wjip1qs5_1422/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/jwu7vwv11bfiar50ae_2490/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_15) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_16) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/nqj3a7on863ee2q57ufzkn6sb2_2042/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/vgsz2hwji6xt2tcnqha3_994/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/xnn8oc66i3dtvlfhp0bahskooll2x2_2380/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/avehixb9cn0lazkk9ssg_157/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/gbqfimspskm6hnlgzqqao1mt5w_1310/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/itav5rgzqhzrf7n00dmq9hj_2570/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/rqlk2vb5gdzd29aq4s0qdonhh2_1914/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/wboy95wr5obljm9n9nzzz5j30dc2v6h_2139/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_S_SYNCER_for_TopDeparser/xan657w55lznzq3hcpp22k9a_2275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/ht1zdw1pp2sdohld_2567/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/itbaw93kgsedybjcawtjyy1ivrr3ksj_977/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/jkyzocxmm0s4149oa1_1899/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_17) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/pvmmu0cz9e244pe3fiu49stpb6kwfc_144/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_18) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopDeparser/r0sf3f4b9u0hx8wiyii96zm26iev_2414/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/lf3x44qdk2z74a1s0gndyt27sldl_779/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for_TopParser/qqbmhkxazc87c1zb8wrds2z2dw55wc3n_868/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/ffbkdipo4aqln89eo1a_180/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/gp7dlwqm2bugfp4a69nq18to_18/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/S_SYNCER_for__OUT_/t3nvy4hx7fbwz0fzqej0kwod6wj_790/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_25) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_26) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_27) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_0/editor_inst/TupFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/DscFifo_inst/RAM/RAM_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/PktFifo_inst/RAM/RAM_reg_6) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_4) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/TopDeparser/TopDeparser_t_inst/stage_2/editor_inst/TupFifo_inst/RAM/RAM_reg_5) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 51 Warnings, 103 Advisories
|
|||
|
|
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
Generating merged BMM file for the design top 'top'...
|
|||
|
|
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/sw/embedded/SDK_Workspace/simple_sume_switch/app/Debug/app.elf
|
|||
|
|
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
|
|||
|
|
Loading data files...
|
|||
|
|
Loading site data...
|
|||
|
|
Loading route data...
|
|||
|
|
Processing options...
|
|||
|
|
Creating bitmap...
|
|||
|
|
Creating bitstream...
|
|||
|
|
Bitstream compression saved 136027840 bits.
|
|||
|
|
Writing bitstream ../bitfiles/simple_sume_switch.bit...
|
|||
|
|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
111 Infos, 51 Warnings, 1 Critical Warnings and 0 Errors encountered.
|
|||
|
|
write_bitstream completed successfully
|
|||
|
|
write_bitstream: Time (s): cpu = 00:03:12 ; elapsed = 00:03:17 . Memory (MB): peak = 4459.961 ; gain = 981.715 ; free physical = 10262 ; free virtual = 13861
|
|||
|
|
# exit
|
|||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Jul 28 18:56:14 2019...
|
|||
|
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
|||
|
|
+ date
|
|||
|
|
Son Jul 28 18:56:14 CEST 2019
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles
|
|||
|
|
+ mv simple_sume_switch.bit minip4.bit
|
|||
|
|
+ cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.sh ./
|
|||
|
|
+ date
|
|||
|
|
Son Jul 28 18:56:14 CEST 2019
|
|||
|
|
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles/
|
|||
|
|
+ pwd -P
|
|||
|
|
+ chmod u+x /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles/program_switch.sh
|
|||
|
|
+ pwd -P
|
|||
|
|
+ sudo bash -c . /home/nico/master-thesis/netpfga/bashinit && /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles/program_switch.sh
|
|||
|
|
++ which vivado
|
|||
|
|
+ xilinx_tool_path=/opt/Xilinx/Vivado/2018.2/bin/vivado
|
|||
|
|
+ bitimage=minip4.bit
|
|||
|
|
+ configWrites=config_writes.sh
|
|||
|
|
+ '[' -z minip4.bit ']'
|
|||
|
|
+ '[' -z config_writes.sh ']'
|
|||
|
|
+ '[' /opt/Xilinx/Vivado/2018.2/bin/vivado == '' ']'
|
|||
|
|
+ rmmod sume_riffa
|
|||
|
|
+ xsct /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl -tclargs minip4.bit
|
|||
|
|
rlwrap: warning: your $TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
|
|||
|
|
RUN loading image file.
|
|||
|
|
minip4.bit
|
|||
|
|
attempting to launch hw_server
|
|||
|
|
|
|||
|
|
****** Xilinx hw_server v2018.2
|
|||
|
|
**** Build date : Jun 14 2018-20:18:37
|
|||
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
|
|||
|
|
INFO: hw_server application started
|
|||
|
|
INFO: Use Ctrl-C to exit hw_server application
|
|||
|
|
|
|||
|
|
INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121
|
|||
|
|
|
|||
|
|
initializing
0% 0MB 0.0MB/s ??:?? ETA
9% 1MB 2.0MB/s ??:?? ETA
17% 1MB 1.8MB/s ??:?? ETA
25% 2MB 1.8MB/s ??:?? ETA
33% 3MB 1.8MB/s ??:?? ETA
41% 4MB 1.7MB/s ??:?? ETA
49% 5MB 1.7MB/s 00:03 ETA
56% 6MB 1.7MB/s 00:02 ETA
64% 7MB 1.7MB/s 00:02 ETA
72% 8MB 1.7MB/s 00:01 ETA
81% 9MB 1.7MB/s 00:01 ETA
88% 9MB 1.7MB/s 00:00 ETA
96% 10MB 1.7MB/s 00:00 ETA
100% 11MB 1.7MB/s 00:06
|
|||
|
|
+ bash /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/pci_rescan_run.sh
|
|||
|
|
|
|||
|
|
Completed rescan PCIe information !
|
|||
|
|
|
|||
|
|
+ rmmod sume_riffa
|
|||
|
|
rmmod: ERROR: Module sume_riffa is not currently loaded
|
|||
|
|
+ modprobe sume_riffa
|
|||
|
|
+ ifconfig nf0 up
|
|||
|
|
nf0: ERROR while getting interface flags: No such device
|
|||
|
|
+ ifconfig nf1 up
|
|||
|
|
nf1: ERROR while getting interface flags: No such device
|
|||
|
|
+ ifconfig nf2 up
|
|||
|
|
nf2: ERROR while getting interface flags: No such device
|
|||
|
|
+ ifconfig nf3 up
|
|||
|
|
nf3: ERROR while getting interface flags: No such device
|
|||
|
|
+ bash config_writes.sh
|