Merge branch 'master' of gitlab.ethz.ch:nicosc/master-thesis
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nico
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doc/plan.org
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doc/plan.org
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@ -2174,6 +2174,97 @@ new dic: OrderedDict()
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****** TODO try10: find out, why nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt has too less content
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****** TODO try10: find out, why nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt has too less content
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******* DONE find out what generates config_writes.txt
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Seems to be step 5:
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#+BEGIN_CENTER
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[14:22] rainbow:SimpleSumeSwitch% pwd
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch
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[14:23] rainbow:SimpleSumeSwitch% ls -lh config_writes.txt
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-rw-rw-r-- 1 nico nico 140 May 25 14:21 config_writes.txt
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[14:23] rainbow:SimpleSumeSwitch% date
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Sat 25 May 2019 02:23:41 PM CEST
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[14:23] rainbow:SimpleSumeSwitch%
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#+END_CENTER
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******* TODO Debug vivado_sim.bash -> run w/ x11 output, also vivado_sim_waveform.bash
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Open GUI, pressing "play" button, getting different / new errors
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#+BEGIN_CENTER
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[SW] CAM_Init() - done
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[SW] CAM_EnableDevice() - start
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SV_write_control()- start
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SV_write_control()- done
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SV_read_control()- start
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SV_read_control()- done
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SV_write_control()- start
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SV_write_control()- done
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[SW] CAM_EnableDevice() - done
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[2420698] INFO: finished packet stimulus file
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[2735572] ERROR: tuple mismatch for packet 1
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expected < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
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actual < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000010000 >
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$finish called at time : 2735572 ps : File
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"/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v"
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Line 120
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#+END_CENTER
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Error message created in
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v
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Same error on shell only version:
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#+BEGIN_CENTER
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projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv
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[SW] CAM_Init() - start
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[SW] CAM_Init() - done
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[SW] CAM_EnableDevice() - start
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SV_write_control()- start
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SV_write_control()- done
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SV_read_control()- start
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SV_read_control()- done
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SV_write_control()- start
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SV_write_control()- done
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[SW] CAM_EnableDevice() - done
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[2420698] INFO: finished packet stimulus file
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[2735572] ERROR: tuple mismatch for packet 1
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expected < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
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actual < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000010000 >
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$finish called at time : 2735572 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" Line 120
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exit
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INFO: [Common 17-206] Exiting xsim at Sat May 25 14:38:05 2019...
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[14:38] rainbow:SimpleSumeSwitch% echo $?
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0
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[14:38] rainbow:SimpleSumeSwitch%
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#+END_CENTER
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Analysing Makefile in testdata + scripts
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******** get_testdata.py: generates some pcap with some packets
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Need to find out
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import sss_sdnet_tuples
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sss_sdnet_tuples.clear_tuple_files()
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Result of this script is src.pcap and dst.pcap.
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Is the lookup table related to the devices?
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NUM_KEYS = 4
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lookup_table = {
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0: 0x00000001,
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1: 0x00000010,
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2: 0x00000100,
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3: 0x00001000
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}
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Where are in/out ports?!
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Modifying / adjusting P4 code to mirror input packets
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******** switch_calc_headers creates some headers
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some specific packet, uses bind_layers
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***** run step 11: checking design -- skipped
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***** run step 11: checking design -- skipped
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***** TODO run step 12: ok
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***** TODO run step 12: ok
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@ -2305,6 +2396,15 @@ sume_riffa 28672 0
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#+END_CENTER
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#+END_CENTER
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***** 2019-05-26, netfpga integration
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#+BEGIN_CENTER
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[10:56] rainbow:projects% mv minip4 ~/master-thesis/netpfga/
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[10:56] rainbow:projects% ln -s ~/master-thesis/netpfga/minip4
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[10:56] rainbow:projects%
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#+END_CENTER
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**** DONE Understand a bit of xilinx/netfpga/vivado ~ somewhat
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**** DONE Understand a bit of xilinx/netfpga/vivado ~ somewhat
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- https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug900-vivado-logic-simulation.pdf
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- https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug900-vivado-logic-simulation.pdf
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The xvhdl and xvlog commands parse VHDL and Verilog files, respectively. Descriptions
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The xvhdl and xvlog commands parse VHDL and Verilog files, respectively. Descriptions
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