Begin from the beginning: reset to port1 only
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Nico Schottelius
parent
5f4930ae43
commit
1059e8d0e0
6 changed files with 99 additions and 10 deletions
81
doc/plan.org
81
doc/plan.org
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@ -5769,7 +5769,8 @@ p4c --target bmv2 --arch v1model --std p4-16 "../p4src/checksum_diff.p4" -o "/ho
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pcap/tcp-udp-delta-from-v6-2019-07-21-0853-h3.pcap | Bin 0 -> 2544 bytes
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#+END_CENTER
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*** TODO 2019-07-21: Porting to netfpga: found relevant EMPTY FILE CHECK / config writes
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*** DONE 2019-07-21: Porting to netfpga: found relevant EMPTY FILE CHECK / config writes
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CLOSED: [2019-07-22 Mon 22:28]
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**** DONE try1: Initial log
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CLOSED: [2019-07-21 Sun 14:03]
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If
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@ -6058,6 +6059,7 @@ make: *** [sim] Error 1
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make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
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#+END_CENTER
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#+BEGIN_CENTER
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@ -6074,7 +6076,79 @@ def config_tables():
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#+BEGIN_CENTER
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~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py
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#+END_CENTER
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*** 2019-07-22: trying to "fix" the config_writes.py
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#+BEGIN_CENTER
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nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default$ cat config_writes.py
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from NFTest import *
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NUM_WRITES = 0
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def config_tables():
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nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default$ echo " pass" >> config_writes.py
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nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default$ cat config_writes.py
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from NFTest import *
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NUM_WRITES = 0
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def config_tables():
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pass
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nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default$
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#+END_CENTER
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*** DONE 2019-07-23: check: switch_calc compiles
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CLOSED: [2019-07-23 Tue 08:59]
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*** TODO 2019-07-23: merge/migrate code into switch calc until it breaks
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*** the config writes madness
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- step9 (sume simulation, the longest step) in the process calls
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"config_writes.py"
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- config_writes.py fails with a syntax error, as it is incomplete
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python code
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- config_writes.py and config_writes.sh are generated by
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gen_config_writes.py
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- gen_config_writes.py reads config_writes.txt
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- config_writes.txt is created in step 5 (sdnet simulation)
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- step 5 consists of running xsc, xelab and xsim
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- xsim (re-)generates config_writes.txt according to a watch ls -l
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on the file: ${XILINX_VIVADO}/bin/xsim --runall
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SimpleSumeSwitch_tb#work.glbl
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- it seems (by grep -r) that ./Testbench/SimpleSumeSwitch_tb.sv is
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responsible for writing config_writes.txt
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- It seems that the "task" "SV_write_control" inside that file is
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responsible for writing the content, which in turn uses
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axi4_lite_master_write_request_control
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**** More notes for the config writes madness
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xsc and xelab are described in
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https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=2ahUKEwiGqfiAmcjjAhXEC-wKHW3_C78QFjABegQIBBAC&url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fsw_manuals%2Fxilinx2014_4%2Fug900-vivado-logic-simulation.pdf&usg=AOvVaw1jgWuqcjeph5qOplb4eJMq
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The xsc compiler helps create a shared library (.a on Windows or .so on Linux) from one
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or more C files. You use xelab to bind the shared library generated by xsc into the rest of
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your design. You can create a shared library using a one- or two-step process:
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- the only file that matches the string "config_writes" in the
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nf_sume_sdnet_ip/SimpleSumeSwitch subdirectory is
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./Testbench/SimpleSumeSwitch_tb.sv
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- code inside SimpleSumeSwitch_tb.sv:
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#+BEGIN_CENTER
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task SV_write_control(
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input integer addr,
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input integer data
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);
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int file;
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file = $fopen("config_writes.txt", "a");
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$display("SV_write_control()- start");
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$fwrite(file, "<addr, data>: (%h, %h)\n", addr, data);
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axi4_lite_master_write_request_control(addr,data);
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$display("SV_write_control()- done");
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$fclose(file);
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endtask
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#+END_CENTER
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*** TODO Further notes P4/master thesis
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- Cannot easily run P4 on notebook - changes to the system very
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@ -6094,6 +6168,11 @@ control_sub_m02_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-proj
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nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ less /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log: No such file or directory
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- Wrong warnings: using 2018.2, getting warnings about things
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removed in 2015.3
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WARNING: command 'get_user_parameter' will be removed in the 2015.3
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release, use 'get_user_parameters' instead
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- A script/makefile generates a python script that generates a shell
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script and later then a python script. If there is a mistake in
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generating the first python script (syntax ok, but content is
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@ -6,17 +6,21 @@ set -x
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echo "First source all variables and THEN run this script"
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read something
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LOG=~/master-thesis/netpfga/log/compile-$(date +%F-%H%M%S)
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exec > "$LOG"
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exec 2>&1
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# Step 1..3: create code
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# Step 4:
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date
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cd $P4_PROJECT_DIR && make
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# Step 5
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# Step 5: sdnet simulation
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date
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cd $P4_PROJECT_DIR/nf_sume_sdnet_ip/SimpleSumeSwitch && ./vivado_sim.bash 2>&1 | tee LOG
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cd $P4_PROJECT_DIR/nf_sume_sdnet_ip/SimpleSumeSwitch && ./vivado_sim.bash
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expected_line=$(grep ^expected LOG | sed -e 's/.*= <//' -e 's/.*= (//')
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actual_line=$(grep ^actual LOG | sed -e 's/.*= <//' -e 's/.*= (//')
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expected_line=$(grep ^expected "$LOG" | sed -e 's/.*= <//' -e 's/.*= (//')
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actual_line=$(grep ^actual "$LOG" | sed -e 's/.*= <//' -e 's/.*= (//')
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# if [ -z "$expected_line" ]; then
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# echo "Empty packet grep -- probably broken - aborting"
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@ -40,7 +44,9 @@ cd $P4_PROJECT_DIR && make uninstall_sdnet && make install_sdnet
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date
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cd $NF_DESIGN_DIR/test/sim_switch_default && make
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# Step 9
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# -------- FIX config_writes.py here: add " pass" or overwrite whole script
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# Step 9: Run the SUME simulation
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date
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cd $SUME_FOLDER && ./tools/scripts/nf_test.py sim --major switch --minor default
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@ -28,7 +28,8 @@ control MyDeparser(packet_out packet, in headers hdr) {
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************** I N G R E S S P R O C E S S I N G *******************
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*************************************************************************/
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control MyIngress(inout headers hdr,
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control MyIngress(
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inout headers hdr,
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inout metadata meta,
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inout standard_metadata_t standard_metadata) {
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@ -98,8 +98,8 @@ control TopPipe(inout Parsed_packet p,
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}
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size = 64;
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// default_action = swap_eth_addresses; // test_mirror(): in gen_testdata.py
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// default_action = send_to_port1; // test_port1()
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default_action = send_to_all_ports; // test_allports():
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default_action = send_to_port1; // test_port1()
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// default_action = send_to_all_ports; // test_allports():
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}
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apply {
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@ -53,6 +53,7 @@ parser TopParser(packet_in packet,
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inout sume_metadata_t standard_metadata) {
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#include "parsers.p4"
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digest_data.unused = 0; /* avoid compiler warning */
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}
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/********************************************************************************
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@ -65,6 +66,8 @@ control TopPipe(inout headers hdr,
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#include "netpfga.p4"
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apply {
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dummy_table_for_netpfga.apply();
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}
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@ -1 +1 @@
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minip4_solution-nat64.p4
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minip4_solution-mirror.p4
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