Begin from the beginning: reset to port1 only

doc/plan.org

@@ -5769,7 +5769,8 @@ p4c --target bmv2 --arch v1model --std p4-16 "../p4src/checksum_diff.p4" -o "/ho
  pcap/tcp-udp-delta-from-v6-2019-07-21-0853-h3.pcap | Bin 0 -> 2544 bytes
 #+END_CENTER
 
-*** TODO 2019-07-21: Porting to netfpga: found relevant EMPTY FILE CHECK / config writes
+*** DONE 2019-07-21: Porting to netfpga: found relevant EMPTY FILE CHECK / config writes
+    CLOSED: [2019-07-22 Mon 22:28]
 **** DONE try1: Initial log
      CLOSED: [2019-07-21 Sun 14:03]
  If
@@ -6058,6 +6059,7 @@ make: *** [sim] Error 1
 make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
 
 
+
 #+END_CENTER
 
 #+BEGIN_CENTER
@@ -6074,7 +6076,79 @@ def config_tables():
 #+BEGIN_CENTER
  ~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py
 #+END_CENTER
+*** 2019-07-22: trying to "fix" the config_writes.py
+#+BEGIN_CENTER
+nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default$ cat config_writes.py
 
+from NFTest import *
+
+NUM_WRITES = 0
+
+def config_tables():
+nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default$ echo "    pass" >> config_writes.py
+nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default$ cat config_writes.py
+
+from NFTest import *
+
+NUM_WRITES = 0
+
+def config_tables():
+    pass
+nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default$
+
+#+END_CENTER
+*** DONE 2019-07-23: check: switch_calc compiles
+    CLOSED: [2019-07-23 Tue 08:59]
+*** TODO 2019-07-23: merge/migrate code into switch calc until it breaks
+*** the config writes madness
+    - step9 (sume simulation, the longest step) in the process calls
+      "config_writes.py"
+    - config_writes.py fails with a syntax error, as it is incomplete
+      python code
+    - config_writes.py and config_writes.sh are generated by
+      gen_config_writes.py
+    - gen_config_writes.py reads config_writes.txt
+    - config_writes.txt is created in step 5 (sdnet simulation)
+    - step 5 consists of running xsc, xelab and xsim
+    - xsim (re-)generates config_writes.txt according to a watch ls -l
+      on the file: ${XILINX_VIVADO}/bin/xsim --runall
+      SimpleSumeSwitch_tb#work.glbl
+    - it seems (by grep -r) that ./Testbench/SimpleSumeSwitch_tb.sv is
+      responsible for writing config_writes.txt
+    - It seems that the "task" "SV_write_control" inside that file is
+      responsible for writing the content, which in turn uses
+      axi4_lite_master_write_request_control
+
+
+**** More notes for the config writes madness
+      xsc and xelab are described in
+      https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=2ahUKEwiGqfiAmcjjAhXEC-wKHW3_C78QFjABegQIBBAC&url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fsw_manuals%2Fxilinx2014_4%2Fug900-vivado-logic-simulation.pdf&usg=AOvVaw1jgWuqcjeph5qOplb4eJMq
+
+      The xsc compiler helps create a shared library (.a on Windows or .so on Linux) from one
+    or more C files. You use xelab to bind the shared library generated by xsc into the rest of
+    your design. You can create a shared library using a one- or two-step process:
+
+    - the only file that matches the string "config_writes" in the
+      nf_sume_sdnet_ip/SimpleSumeSwitch subdirectory is
+      ./Testbench/SimpleSumeSwitch_tb.sv
+
+    - code inside SimpleSumeSwitch_tb.sv:
+
+#+BEGIN_CENTER
+task SV_write_control(
+    input  integer  addr,
+    input  integer  data
+);
+int file;
+file = $fopen("config_writes.txt", "a");
+$display("SV_write_control()- start");
+$fwrite(file, "<addr, data>: (%h, %h)\n", addr, data);
+axi4_lite_master_write_request_control(addr,data);
+$display("SV_write_control()- done");
+$fclose(file);
+endtask
+
+#+END_CENTER
 
 *** TODO Further notes P4/master thesis
     - Cannot easily run P4 on notebook - changes to the system very
@@ -6094,6 +6168,11 @@ control_sub_m02_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-proj
 nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ less /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log
 /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log: No such file or directory
 
+    - Wrong warnings: using 2018.2, getting warnings about things
+      removed in 2015.3
+WARNING: command 'get_user_parameter' will be removed in the 2015.3
+release, use 'get_user_parameters' instead
+
     - A script/makefile generates a python script that generates a shell
       script and later then a python script. If there is a mistake in
       generating the first python script (syntax ok, but content is

netpfga/do-all-steps.sh

@@ -6,17 +6,21 @@ set -x
 echo "First source all variables and THEN run this script"
 read something
 
+LOG=~/master-thesis/netpfga/log/compile-$(date +%F-%H%M%S)
+exec > "$LOG"
+exec 2>&1
+
 # Step 1..3: create code
 # Step 4:
 date
 cd $P4_PROJECT_DIR && make
 
-# Step 5
+# Step 5: sdnet simulation
 date
-cd $P4_PROJECT_DIR/nf_sume_sdnet_ip/SimpleSumeSwitch && ./vivado_sim.bash 2>&1 | tee LOG
+cd $P4_PROJECT_DIR/nf_sume_sdnet_ip/SimpleSumeSwitch && ./vivado_sim.bash
 
-expected_line=$(grep ^expected LOG | sed -e 's/.*= <//' -e 's/.*= (//')
+expected_line=$(grep ^expected "$LOG" | sed -e 's/.*= <//' -e 's/.*= (//')
-actual_line=$(grep ^actual LOG     | sed -e 's/.*= <//' -e 's/.*= (//')
+actual_line=$(grep ^actual "$LOG"     | sed -e 's/.*= <//' -e 's/.*= (//')
 
 # if [ -z "$expected_line" ]; then
 #     echo "Empty packet grep -- probably broken - aborting"
@@ -40,7 +44,9 @@ cd $P4_PROJECT_DIR && make uninstall_sdnet && make install_sdnet
 date
 cd $NF_DESIGN_DIR/test/sim_switch_default && make
 
-# Step 9
+# -------- FIX config_writes.py here: add "    pass" or overwrite whole script
+
+# Step 9: Run the SUME simulation
 date
 cd $SUME_FOLDER && ./tools/scripts/nf_test.py sim --major switch --minor default
 

p4src/checksum_diff.p4

@@ -28,7 +28,8 @@ control MyDeparser(packet_out packet, in headers hdr) {
 **************  I N G R E S S   P R O C E S S I N G   *******************
 *************************************************************************/
 
-control MyIngress(inout headers hdr,
+control MyIngress(
+    inout headers hdr,
     inout metadata meta,
     inout standard_metadata_t standard_metadata) {
 

p4src/minip4_solution-mirror.p4

@@ -98,8 +98,8 @@ control TopPipe(inout Parsed_packet p,
         }
         size = 64;
 //        default_action = swap_eth_addresses; // test_mirror(): in gen_testdata.py
-//        default_action = send_to_port1; // test_port1()
+        default_action = send_to_port1; // test_port1()
-        default_action = send_to_all_ports; // test_allports():
+//        default_action = send_to_all_ports; // test_allports():
     }
 
     apply {

p4src/minip4_solution-nat64.p4

@@ -53,6 +53,7 @@ parser TopParser(packet_in packet,
                  inout sume_metadata_t standard_metadata) {
 
     #include "parsers.p4"
+    digest_data.unused = 0; /* avoid compiler warning */
 }
 
 /********************************************************************************
@@ -65,6 +66,8 @@ control TopPipe(inout headers hdr,
 
     #include "netpfga.p4"
 
+
+
     apply {
         dummy_table_for_netpfga.apply();
     }

p4src/minip4_solution.p4

@@ -1 +1 @@
-minip4_solution-nat64.p4
+minip4_solution-mirror.p4