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Re-add table entries in commands.txt

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Nico Schottelius 2019-07-27 21:35:47 +02:00
parent 802a0ea131
commit 1ae0294a39
5 changed files with 430 additions and 23 deletions
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doc/plan.org
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@ -6787,7 +6787,8 @@ action delta_udp_from_v6_to_v4()
#+END_CENTER
*** TODO 2019-07-25: BUG overwrite: calling v4_networks.apply(); twice is impossible in different branches
*** DONE 2019-07-25: BUG overwrite: calling v4_networks.apply(); twice is impossible in different branches
CLOSED: [2019-07-27 Sat 14:48]
#+BEGIN_CENTER
make -C src/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
@ -6806,8 +6807,407 @@ Makefile:34: recipe for target 'all' failed
#+END_CENTER
*** TODO 2019-07-25: LIMIT: cannot use actions with arguments as default parameters
*** DONE 2019-07-25: LIMIT: cannot use actions with arguments as default parameters
CLOSED: [2019-07-27 Sat 14:48]
*** DONE 2019-07-27: loading driver, checking interfaces: interfaces are not there
CLOSED: [2019-07-27 Sat 14:53]
#+BEGIN_CENTER
+ sudo modprobe -r sume_riffa
modprobe: FATAL: Module sume_riffa not found.
+ true
+ make clean
make -C /lib/modules/4.15.0-55-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0 clean
make[1]: Entering directory '/usr/src/linux-headers-4.15.0-55-generic'
CLEAN /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0/.tmp_versions
CLEAN /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0/Module.symvers
make[1]: Leaving directory '/usr/src/linux-headers-4.15.0-55-generic'
+ make all
make -C /lib/modules/4.15.0-55-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0 modules
make[1]: Entering directory '/usr/src/linux-headers-4.15.0-55-generic'
CC [M] /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0/sume_riffa.o
Building modules, stage 2.
MODPOST 1 modules
CC /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0/sume_riffa.mod.o
LD [M] /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0/sume_riffa.ko
make[1]: Leaving directory '/usr/src/linux-headers-4.15.0-55-generic'
+ sudo make install
make -C /lib/modules/4.15.0-55-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0 modules
make[1]: Entering directory '/usr/src/linux-headers-4.15.0-55-generic'
Building modules, stage 2.
MODPOST 1 modules
make[1]: Leaving directory '/usr/src/linux-headers-4.15.0-55-generic'
install -o root -g root -m 0755 -d /lib/modules/4.15.0-55-generic/extra/sume_riffa/
install -o root -g root -m 0755 sume_riffa.ko /lib/modules/4.15.0-55-generic/extra/sume_riffa/
depmod -a 4.15.0-55-generic
+ sudo modprobe sume_riffa
+ lsmod
+ grep sume_riffa
sume_riffa 28672 0
nico@nsg-System:~/master-thesis/netpfga$
#+END_CENTER
*** DONE 2019-07-27: reflash the card: ok
CLOSED: [2019-07-27 Sat 14:54]
*** DONE 2019-07-27: check interfaces after (re-)reboot: ok!
CLOSED: [2019-07-27 Sat 14:57]
#+BEGIN_CENTER
nico@nsg-System:~/master-thesis/netpfga$ ./bind-mount.sh
+ rm -f /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src
+ rm -f /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
rm: cannot remove '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4': Is a directory
+ mkdir -p /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/
+ sudo mount --bind /home/nico/master-thesis/netpfga/minip4/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/
+ mkdir -p /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src
+ sudo mount --bind /home/nico/master-thesis/p4src/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src
nico@nsg-System:~/master-thesis/netpfga$ ./build-load-drivers.sh
+ cd /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0
+ sudo modprobe -r sume_riffa
+ make clean
make -C /lib/modules/4.15.0-55-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0 clean
make[1]: Entering directory '/usr/src/linux-headers-4.15.0-55-generic'
CLEAN /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0/.tmp_versions
CLEAN /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0/Module.symvers
make[1]: Leaving directory '/usr/src/linux-headers-4.15.0-55-generic'
+ make all
make -C /lib/modules/4.15.0-55-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0 modules
make[1]: Entering directory '/usr/src/linux-headers-4.15.0-55-generic'
CC [M] /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0/sume_riffa.o
Building modules, stage 2.
MODPOST 1 modules
CC /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0/sume_riffa.mod.o
LD [M] /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0/sume_riffa.ko
make[1]: Leaving directory '/usr/src/linux-headers-4.15.0-55-generic'
+ sudo make install
make -C /lib/modules/4.15.0-55-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0 modules
make[1]: Entering directory '/usr/src/linux-headers-4.15.0-55-generic'
Building modules, stage 2.
MODPOST 1 modules
make[1]: Leaving directory '/usr/src/linux-headers-4.15.0-55-generic'
install -o root -g root -m 0755 -d /lib/modules/4.15.0-55-generic/extra/sume_riffa/
install -o root -g root -m 0755 sume_riffa.ko /lib/modules/4.15.0-55-generic/extra/sume_riffa/
depmod -a 4.15.0-55-generic
+ sudo modprobe sume_riffa
+ lsmod
+ grep sume_riffa
sume_riffa 28672 0
nico@nsg-System:~/master-thesis/netpfga$
6: nf0: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 02:53:55:4d:45:00 brd ff:ff:ff:ff:ff:ff
7: nf1: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 02:53:55:4d:45:01 brd ff:ff:ff:ff:ff:ff
8: nf2: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 02:53:55:4d:45:02 brd ff:ff:ff:ff:ff:ff
9: nf3: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 02:53:55:4d:45:03 brd ff:ff:ff:ff:ff:ff
nico@nsg-System:~/master-thesis/netpfga$
#+END_CENTER
*** 2019-07-27
*** TODO 2019-07-27: test output ports / connection to 2nd computer / dst_addr / exact
- action: TopPipe.realmain.set_egress_port
- IPv6 address: 42540766411362381960998550477184434178
- Table: realmain_v6_networks_0
#+BEGIN_CENTER
>>> int(ipaddress.IPv6Address("2001:db8:42::2"))
42540766411362381960998550477184434178
>> table_cam_add_entry v6_networks set_egress_port 42540766411362381960998550477184434178 => 1
ERROR: v6_networks is not a recognized CAM table name
>> table_cam_add_entry realmain_v6_networks set_egress_port 42540766411362381960998550477184434178 => 1
ERROR: realmain_v6_networks is not a recognized CAM table name
>> table_cam_add_entry realmain_v6_networks_0 set_egress_port 42540766411362381960998550477184434178 => 1
ERROR: TopPipe.set_egress_port is not a recognized action for table realmain_v6_networks_0
>> table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434178 => 1
ERROR: not enough fields provided to complete _hexify()
#+END_CENTER
*** TODO 2019-07-27: find out where the _hexify() error comes from
- no raise() in the code -> just sys.exit...
- using table_tcam_write_entry
- 6 arguments are parsed:
(table_name, address, keys, masks, action_name, action_data) = parse_table_tcam_add_entry(line)
p4_tables_api.table_tcam_write_entry(table_name, address, keys, masks, action_name, action_data)
- arguments passed: 4
realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434178 => 1
#+BEGIN_CENTER
nico@nsg-System:~$ grep -r "not enough fields provided to complete _hexify()" -r ~/
/home/nico/P4-NetFPGA-live-clean/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py: print >> sys.stderr, "ERROR: not enough fields provided to complete _hexify()"
Binary file /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.pyc matches
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py: print >> sys.stderr, "ERROR: not enough fields provided to complete _hexify()"
def _hexify(self, field_vals, fields):
field_sizes = [size for name, size in fields if ('padding' not in name and 'hit' not in name)]
if (len(field_vals) != len(field_sizes)):
print >> sys.stderr, "ERROR: not enough fields provided to complete _hexify()"
sys.exit(1)
# convert field_vals to int
field_vals = map(convert_to_int, field_vals)
# combine field_vals using field sizes
ret = 0
for val, bits in zip(field_vals, field_sizes):
mask = 2**bits -1
ret = (ret << bits) + (val & mask)
return ret
nico@nsg-System:~$ find ~/ -name p4_tables_api\*
/home/nico/P4-NetFPGA-live-clean/contrib-projects/sume-sdnet-switch/templates/CLI_template/p4_tables_api.py
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/sw/CLI/p4_tables_api.py
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI/p4_tables_api.pyc
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI/p4_tables_api.py
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/int/sw/CLI/p4_tables_api.py
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/CLI_template/p4_tables_api.py
/home/nico/master-thesis/netpfga/minip4/sw/CLI/p4_tables_api.pyc
/home/nico/master-thesis/netpfga/minip4/sw/CLI/p4_tables_api.py
nico@nsg-System:~$
./projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py: def hexify_value(self, action_name, action_data):
>> table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434178 => 1
dbg: realmain_v6_networks_0 ['42540766411362381960998550477184434178'] realmain.set_egress_port ['1']
key
value
fields = [(u'hit', 1), (u'action_run', 3), (u'out_port', 8), (u'out_port', 8), (u'mac_addr', 48), (u'task', 16), (u'table_id', 16)]
action_name = TopPipe.realmain.set_egress_port
field_vals = [1, '1']
ERROR: not enough fields provided to complete _hexify()
nico@nsg-System:~/master-thesis/netpfga/minip4/sw/CLI$
>> table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434178 => 1 1 0 0 0
dbg: realmain_v6_networks_0 ['42540766411362381960998550477184434178'] realmain.set_egress_port ['1', '1', '0', '0', '0']
key
value
fields = [(u'hit', 1), (u'action_run', 3), (u'out_port', 8), (u'out_port', 8), (u'mac_addr', 48), (u'task', 16), (u'table_id', 16)]
action_name = TopPipe.realmain.set_egress_port
field_vals = [1, '1', '1', '0', '0', '0']
CAM_Init_ValidateContext() - done
WROTE 0x44020350 = 0x0002
WROTE 0x44020354 = 0x0000
WROTE 0x44020358 = 0x420000
WROTE 0x4402035c = 0x20010db8
WROTE 0x44020380 = 0x0000
WROTE 0x44020384 = 0x0000
WROTE 0x44020388 = 0x1010000
WROTE 0x4402038c = 0x0001
READ 0x44020344 = 0x0001
WROTE 0x44020340 = 0x0001
READ 0x44020344 = 0x0001
READ 0x44020344 = 0x0001
success
>>
#+END_CENTER
*** DONE 2019-07-27: adding neighboar entry
CLOSED: [2019-07-27 Sat 21:17]
#+BEGIN_CENTER
nico@ESPRIMO-P956:~$ sudo ip -6 neighbor add 2001:db8:42::3 lladdr 02:53:55:4d:45:00 dev enp2s0f1
nico@ESPRIMO-P956:~$ ip -6 neigh list
fe80::66a0:e7ff:fe42:2ec1 dev enp0s31f6 lladdr 64:a0:e7:42:2e:c1 router REACHABLE
2001:db8:42::3 dev enp2s0f1 lladdr 02:53:55:4d:45:00 PERMANENT
fe80::faf2:1eff:fe41:449d dev enp2s0f1 lladdr f8:f2:1e:41:44:9d STALE
2001:db8:42::2 dev enp2s0f1 FAILED
2001:db8:42::43 dev enp2s0f1 lladdr f8:f2:1e:41:44:9d STALE
2001:67c:10ec:2a49:8000::1 dev enp0s31f6 lladdr 64:a0:e7:42:2e:c1 router STALE
nico@ESPRIMO-P956:~$
#+END_CENTER
*** TODO 2019-07-27: also write output port for ::3
#+BEGIN_CENTER
>> table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434179 => 1 1 0 0 0
dbg: realmain_v6_networks_0 ['42540766411362381960998550477184434179'] realmain.set_egress_port ['1', '1', '0', '0', '0']
key
value
fields = [(u'hit', 1), (u'action_run', 3), (u'out_port', 8), (u'out_port', 8), (u'mac_addr', 48), (u'task', 16), (u'table_id', 16)]
action_name = TopPipe.realmain.set_egress_port
field_vals = [1, '1', '1', '0', '0', '0']
CAM_Init_ValidateContext() - done
WROTE 0x44020350 = 0x0003
WROTE 0x44020354 = 0x0000
WROTE 0x44020358 = 0x420000
WROTE 0x4402035c = 0x20010db8
WROTE 0x44020380 = 0x0000
WROTE 0x44020384 = 0x0000
WROTE 0x44020388 = 0x1010000
WROTE 0x4402038c = 0x0001
READ 0x44020344 = 0x0001
WROTE 0x44020340 = 0x0001
READ 0x44020344 = 0x0001
READ 0x44020344 = 0x0001
success
>>
#+END_CENTER
*** DONE 2019-07-27: deleting table entry does not work due to another bug in the code
CLOSED: [2019-07-27 Sat 21:28]
#+BEGIN_CENTER
>> table_cam_delete_entry realmain_v6_networks_0 42540766411362381960998550477184434179
ERROR: failed to convert 42540766411362381960998550477184434179 of type <type 'long'> to an integer
nico@nsg-System:~/master-thesis/netpfga/minip4/sw/CLI$
./projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py: print >> sys.stderr, "ERROR: failed to convert {} of type {} to an integer".format(val, type(val))
except ValueError as e:
print >> sys.stderr, "ERROR: failed to convert {} of type {} to an integer".format(val, type(val))
#+END_CENTER
*** DONE 2019-07-27: fix broken python code for deleting table entry: p4_px_tables.py on nsg
CLOSED: [2019-07-27 Sat 21:28]
*** TODO 2019-07-27: find out, why more parameters are required for table_cam_add_entry
*** TODO 2019-07-27: receiving any packet from the card
#+BEGIN_CENTER
nico@ESPRIMO-P956:~$ sudo ip l s enp2s0f0 up
nico@ESPRIMO-P956:~$ sudo ip l s enp2s0f1 up
12: enp2s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000
link/ether f8:f2:1e:09:62:d0 brd ff:ff:ff:ff:ff:ff
13: enp2s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000
link/ether f8:f2:1e:09:62:d1 brd ff:ff:ff:ff:ff:ff
inet6 2001:db8:42::42/64 scope global
valid_lft forever preferred_lft forever
inet6 fe80::faf2:1eff:fe09:62d1/64 scope link
valid_lft forever preferred_lft forever
nico@nsg-System:~/master-thesis/netpfga/minip4/sw/CLI$ ./P4_SWITCH_CLI.py
loading libsume..
loading libsume..
loading libcam..
The SimpleSumeSwitch interactive command line tool
type help to see all commands
>> help
Documented commands (type help <topic>):
========================================
help table_cam_delete_entry table_tcam_add_entry
list_cam_tables table_cam_get_size table_tcam_clean
list_lpm_tables table_cam_read_entry table_tcam_erase_entry
list_regs table_lpm_get_addr_size table_tcam_get_addr_size
list_tcam_tables table_lpm_load_dataset table_tcam_set_log_level
reg_read table_lpm_set_active_lookup_bank table_tcam_verify_entry
reg_write table_lpm_set_log_level
table_cam_add_entry table_lpm_verify_dataset
Undocumented commands:
======================
EOF
>>
>> help table_cam_add_entry
table_cam_add_entry <table_name> <action_name> <keys> => <action_data>
DESCRIPTION: Add an entry to the specified table
PARAMS:
<table_name> : name of the table to add an entry to
<action_name> : name of the action to use in the entry (must be listed in the table's actions list)
<keys> : space separated list of keys to use as the entry key (must correspond to table's keys in the order defined in the P4 program)
<action_data> : space separated list of values to provide as input to the action
#+END_CENTER
*** TODO 2019-07-27: try adding table entries / running ipv6/ipv4 nat code
#+BEGIN_CENTER
nico@nsg-System:~/master-thesis$ ls
u'type': u'bits'}],
u'response_fields': [{u'px_name': u'hit', u'size': 1, u'type': u'bits'},
{u'px_name': u'action_run',
u'size': 3,
u'type': u'bits'},
{u'fields': [{u'px_name': u'v6_src',
u'size': 128,
u'type': u'bits'},
{u'px_name': u'v4_dst',
u'size': 32,
u'type': u'bits'},
{u'px_name': u'nat64_prefix',
u'size': 128,
u'type': u'bits'}],
u'p4_action': u'TopPipe.realmain.nat64_static',
u'px_name': u'realmain_nat64_static',
u'type': u'struct'},
{u'fields': [{u'px_name': u'table_id',
u'size': 16,
u'type': u'bits'}],
u'p4_action': u'TopPipe.realmain.controller_debug_table_id',
u'px_name': u'realmain_controller_debug_table_id_5',
u'type': u'struct'}]}
----------------
realmain_nat46_0 :
----------------
{u'action_ids': {u'.NoAction': 4,
u'TopPipe.realmain.controller_debug': 1,
u'TopPipe.realmain.controller_debug_table_id': 3,
u'TopPipe.realmain.nat46_static': 2},
u'annotations': {u'Xilinx_ExternallyConnected': [u'0'],
u'Xilinx_LookupEngineType': [u'EM'],
u'name': [u'TopPipe.realmain.nat46']},
u'match_type': u'EM',
u'p4_name': u'realmain_nat46_0',
u'px_class': u'LookupEngine',
u'px_name': u'realmain_nat46_0',
u'px_type_name': u'realmain_nat46_0_t',
u'request_fields': [{u'p4_name': u'hdr.ipv4.dst_addr',
u'px_name': u'lookup_request_key_3',
u'size': 32,
u'type': u'bits'}],
u'response_fields': [{u'px_name': u'hit', u'size': 1, u'type': u'bits'},
{u'px_name': u'action_run',
u'size': 3,
u'type': u'bits'},
{u'fields': [{u'px_name': u'v6_src',
u'size': 128,
u'type': u'bits'},
{u'px_name': u'v4_dst',
u'size': 32,
u'type': u'bits'},
{u'px_name': u'nat64_prefix',
u'size': 128,
u'type': u'bits'}],
u'p4_action': u'TopPipe.realmain.nat46_static',
u'px_name': u'realmain_nat46_static',
u'type': u'struct'},
{u'fields': [{u'px_name': u'table_id',
u'size': 16,
u'type': u'bits'}],
u'p4_action': u'TopPipe.realmain.controller_debug_table_id',
u'px_name': u'realmain_controller_debug_table_id_6',
u'type': u'struct'}]}
>>
#+END_CENTER
*** DONE 2019-07-27: loading CLI cannot find correct json file -> bind mount missing
CLOSED: [2019-07-27 Sat 19:04]
#+BEGIN_CENTER
nico@nsg-System:~/master-thesis/netpfga/minip4/sw/CLI$ ./P4_SWITCH_CLI.py
loading libsume..
loading libsume..
Traceback (most recent call last):
File "./P4_SWITCH_CLI.py", line 36, in <module>
import p4_regs_api, p4_tables_api
File "/home/nico/master-thesis/netpfga/minip4/sw/CLI/p4_regs_api.py", line 71, in <module>
P4_EXTERNS = read_extern_defines()
File "/home/nico/master-thesis/netpfga/minip4/sw/CLI/p4_regs_api.py", line 55, in read_extern_defines
with open(EXTERN_DEFINES_FILE) as f:
IOError: [Errno 2] No such file or directory: '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI/SimpleSumeSwitch_extern_defines.json'
nico@nsg-System:~/master-thesis/netpfga/minip4/sw/CLI$
#+END_CENTER
** The NetPFGA saga
Problems encountered:
- The logfile for a compile run is 10k+ lines
@ -6897,6 +7297,8 @@ ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl
nico@nsg-System:~/master-thesis/netpfga$ ls /home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log
ls: cannot access '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log': No such file or directory
- not using raise() and hiding source of errors (_hexify)
** References / Follow up
*** RFC 791 IPv4 https://tools.ietf.org/html/rfc791
*** RFC 792 ICMP https://tools.ietf.org/html/rfc792

5
netpfga/minip4/sw/CLI/p4_tables_api.py
View File

@ -42,8 +42,7 @@ p4_px_tables.make_px_tables(SWITCH_INFO_FILE)
PX_CAM_TABLES = {}
PX_TCAM_TABLES = {}
PX_LPM_TABLES = {}
PX_LPM_
def split_px_tables():
for name, table in p4_px_tables.PX_TABLES.items():
if table.info['match_type'] == 'EM':
@ -281,5 +280,3 @@ def table_lpm_set_active_lookup_bank(table_name, bank):
def table_lpm_error_decode(error):
return liblpm.lpm_error_decode(error)

3
p4src/NO_NETPFGA_commands.txt
View File

@ -1,3 +0,0 @@
// only used on netpfga for dummy packet reply
table_cam_add_entry dummy_table_for_netpfga send_to_port1 0x082222222208 => 0x1

11
p4src/commands.txt
View File

@ -0,0 +1,11 @@
// only used on netpfga for dummy packet reply
//table_cam_add_entry dummy_table_for_netpfga send_to_port1 0x082222222208 => 0x1
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434179 => 1
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434180 => 2
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434181 => 3
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434182 => 4
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434183 => 5
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434184 => 6
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434185 => 7
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434186 => 8

2
p4src/minip4_solution.p4
View File

@ -154,7 +154,7 @@ control RealMain(
}
if(hdr.tcp.isValid()) {
delta_tcp_from_v4_to_v6
}
1 }
apply_v4networks = true;
apply_v6networks = false;
}