++results

doc/Conclusion.tex

@@ -10,12 +10,9 @@ Sum up what you have done and recapitulate your key findings.
 \section{\label{conclusion:softwarenat64}Software based NAT64}
 
 \section{\label{conclusion:general}General}
-Many misleading
-
 
 \section{\label{conclusion:bmv2}BMV2}
 
-
 \section{\label{conclusion:P4}P4}
 
 NDP parsing problem
@@ -175,173 +172,15 @@ idomatic problem: Security issue: not checking checksums before
 % ----------------------------------------------------------------------
 \section{\label{conclusion:netpfga}NetFGPA - all HERE}
 
-many dependencies
-lpm not supported!
-Netpfga live,
-
-Many workarounds
-
-packet size / annotation
-
 Needed to debug internal parsing errors
 
-
 debugging generated tcl code to debug impl1 error
 
-function syntax not supported, using defines instead
-
-match type exact - table must be at least 64 in size
-
-Damaged, enlarged packets
-
-\begin{verbatim}
-** The NetPFGA saga
-Problems encountered:
-- The logfile for a compile run is 10k+ lines
-- Many logged errors can actually be ignored (?) like:
-
-ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
-ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_DATA on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:219]
-ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_VALID on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:218]
-ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_DATA on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:185]
-ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_VALID on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:184]
-ERROR: [VRFC 10-2063] Module <S_RESETTER_line> not found while processing module instance <S_RESET_clk_line> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/Simp
-leSumeSwitch/SimpleSumeSwitch.v:332]
-ERROR: [VRFC 10-2063] Module <S_RESETTER_lookup> not found while processing module instance <S_RESET_clk_lookup> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/
-SimpleSumeSwitch/SimpleSumeSwitch.v:343]
-ERROR: [VRFC 10-2063] Module <S_RESETTER_control> not found while processing module instance <S_RESET_clk_control> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_i
-p/SimpleSumeSwitch/SimpleSumeSwitch.v:354]
-ERROR: [VRFC 10-2063] Module <TopParser_t> not found while processing module instance <TopParser> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitc
-h/SimpleSumeSwitch.v:436]
-ERROR: [VRFC 10-2063] Module <TopPipe_lvl_t> not found while processing module instance <TopPipe_lvl> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeS
-witch/SimpleSumeSwitch.v:474]
-ERROR: [VRFC 10-2063] Module <dummy_table_for_netpfga_t> not found while processing module instance <dummy_table_for_netpfga> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_s
-ume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:502]
-ERROR: [VRFC 10-2063] Module <TopPipe_lvl_0_t> not found while processing module instance <TopPipe_lvl_0> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleS
-umeSwitch/SimpleSumeSwitch.v:533]
-ERROR: [VRFC 10-2063] Module <TopDeparser_t> not found while processing module instance <TopDeparser> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeS
-witch/SimpleSumeSwitch.v:561]
-
-# launch_simulation -simset sim_1 -mode behavioral
-INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
-CRITICAL WARNING: [BD 41-1356] Address block </M04_AXI/Reg> is not mapped into </S00_AXI>. Please use Address Editor to either map or exclude it.
-CRITICAL WARNING: [BD 41-1356] Address block </M05_AXI/Reg> is not mapped into </S00_AXI>. Please use Address Editor to either map or exclude it.
-
-WARNING: [VRFC 10-756] identifier state is used before its declaration [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:93]
-WARNING: [VRFC 10-756] identifier ready_count is used before its declaration [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:94]
-
-
-
-INFO: [#UNDEF] Sorry, too many errors..
-ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
-INFO: [USF-XSim-99] Step results log file:'/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log'
-ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' file for more information.
-
-nico@nsg-System:~/master-thesis$ find . -name elaborate.log
-nico@nsg-System:~/master-thesis$ find ~ -name elaborate.log
-nico@nsg-System:~/master-thesis$
-
-- Scripts that "fail" (generate wrong data) do exit 0 ->
-  There is no easy / reliable error detection
-- Writing tables resulted in ioctl errors
-- Hardware test: unclear if first board was/is broken or not,
-  BUT: second board in different computer allows writing tables
-- Many scripts depend on each other in later stages, without clear
-  dependencies
-- There is basically no documentation for someone who "just wants to
-  compile from P4 to netpfga" or A LOT of documentation (if vivado,
-  vhld, sdnet documentation is counted)
-- Very high complexity in toolchain, scripts that are generated
-+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default
-+ make
-rm -f config_writes.py*
-rm -f *.pyc
-
-nico@nsg-System:~$ cat /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py
-
-from NFTest import *
-
-NUM_WRITES = 4
-
-def config_tables():
-    nftest_regwrite(0x44020050, 0x22222208)
-    nftest_regwrite(0x44020054, 0x00000822)
-    nftest_regwrite(0x44020080, 0x00000201)
-    nftest_regwrite(0x44020040, 0x00000001)
-nico@nsg-System:~$ cat /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.sh
-#!/bin/bash
-
-${SUME_SDNET}/sw/sume/rwaxi -a 0x44020050 -w 0x22222208
-${SUME_SDNET}/sw/sume/rwaxi -a 0x44020054 -w 0x00000822
-${SUME_SDNET}/sw/sume/rwaxi -a 0x44020080 -w 0x00000201
-${SUME_SDNET}/sw/sume/rwaxi -a 0x44020040 -w 0x00000001
-nico@nsg-System:~$
-
-
-- Misleading errors like
-ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' file for more information.
-nico@nsg-System:~/master-thesis/netpfga$ ls /home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log
-ls: cannot access '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log': No such file or directory
-
-- not using raise() and hiding source of errors (_hexify)
-
-- sometimes flashing fails:
-
-#+BEGIN_CENTER
-nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles$ sudo bash -c ". $HOME/master-thesis/netpfga/bashinit && $(pwd -P)/program_switch.sh"
-++ which vivado
-+ xilinx_tool_path=/opt/Xilinx/Vivado/2018.2/bin/vivado
-+ bitimage=minip4.bit
-+ configWrites=config_writes.sh
-+ '[' -z minip4.bit ']'
-+ '[' -z config_writes.sh ']'
-+ '[' /opt/Xilinx/Vivado/2018.2/bin/vivado == '' ']'
-+ rmmod sume_riffa
-+ xsct /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl -tclargs minip4.bit
-rlwrap: warning: your $TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems.
-RUN loading image file.
-minip4.bit
-100%   19MB   1.7MB/s  00:11
-fpga configuration failed. DONE PIN is not HIGH
-    invoked from within
-"::tcf::eval -progress ::xsdb::print_progress {::tcf::cache_enter tcfchan#0 {tcf_cache_eval {process_tcf_actions_cache_client ::tcfclient#0::arg}}}"
-    (procedure "::tcf::cache_eval_with_progress" line 2)
-    invoked from within
-"::tcf::cache_eval_with_progress [dict get $arg chan]  [list process_tcf_actions_cache_client $argvar] $progress"
-    (procedure "process_tcf_actions" line 1)
-    invoked from within
-"process_tcf_actions $arg ::xsdb::print_progress"
-    (procedure "fpga" line 430)
-    invoked from within
-"fpga -f $bitimage"
-    (file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl" line 33)
-
-+ bash /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/pci_rescan_run.sh
-Check programming FPGA or Reboot machine !
-+ rmmod sume_riffa
-rmmod: ERROR: Module sume_riffa is not currently loaded
-+ modprobe sume_riffa
-+ ifconfig nf0 up
-nf0: ERROR while getting interface flags: No such device
-+ ifconfig nf1 up
-nf1: ERROR while getting interface flags: No such device
-+ ifconfig nf2 up
-nf2: ERROR while getting interface flags: No such device
-+ ifconfig nf3 up
-nf3: ERROR while getting interface flags: No such device
-+ bash config_writes.sh
-nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles$
-
-#+END_CENTER
-
-\end{verbatim}
 
 \section{\label{conclusion:realworld}Real world applications}
 Can be deployed using the netpfga. Or Barefoot or Arista.
 
 
-
 \section{\label{conclusion:outlook}Outlook}
 
 %** Outlook.tex: What needs to be done further, what is planed

doc/Results.tex

@@ -265,6 +265,10 @@ and multiple times reflashing the bitstream to the NetFPGA usually
 restored the intended behaviour. However due to this ``crashes'', it
 was impossible to complete a full benchmark run that would last for
 more than one hour.
+
+Sometimes it was also required to reboot the host containing the
+NetFPGA card 3 times to enable successful flashing.\footnote{Typical
+output of the flashing process would be: ``fpga configuration failed. DONE PIN is not HIGH''}
 % ----------------------------------------------------------------------
 \subsection{\label{results:netpfga:performance}Performance}
 As expected, the NetFGPA card performed at near line speed and offers
@@ -326,10 +330,23 @@ error.\footnote{F.i. ``CRITICAL WARNING: [BD 41-737] Cannot set the
 parameter TRANSLATION\_MODE on /axi\_interconnect\_0. It is
 read-only.'' is a non critical warning.}
 Also contradicting
-output is generated\footnote{While using version 2018.2, the following
+output is generated.\footnote{While using version 2018.2, the following
 message was printed: ``WARNING: command 'get\_user\_parameter' will be removed in the 2015.3
 release, use 'get\_user\_parameters' instead''.}
 
+Programs or scripts that are called during the compile process do not
+necessarily exit non zero if they encountered a critical error. Thus
+finding the source of an error can be difficult due to the compile
+process continuing after critical errors occured. Not only programs
+that have critical errors exit ``successfully'', but also python
+scripts that encounter critical paths don't abort with raise(), but
+print an error message to stdout and don't abort with an error.
+
+The most often encountered critical compile error is
+``Run 'impl\_1' has not been launched. Unable to open''. This error
+indicates that something in the previous compile steps failed and can
+refer to incorrectly generated testdata to unsupported LPM tables.
+
 The NetFPGA kernel module provides access to virtual Linux
 devices (nf0...nf3). However tcpdump does not see any packets that are
 emitted from the switch. The only possibility to capture packets
@@ -344,6 +361,15 @@ NetPFGA mailing list, the NetFPGA only supports 1500 byte frames at
 the moment and additional work is required to implement support for
 bigger frames.
 
+Our P4 source code required contains Xilinx
+annotations\footnote{F.i. ``@Xilinx\_MaxPacketRegion(1024)''} that define
+the maximum packet size in bits. We observed two different errors on
+the output packet, if the incoming packets exceeds the specified size:
+\begin{itemize}
+\item The output packet is longer then the original packet.
+\item The output packet is corrupted.
+\end{itemize}
+
 While most of the P4 language is supported on the netpfga, some key
 techniques are missing or not supported.
 \begin{itemize}

doc/appendix.tex

@@ -1642,13 +1642,6 @@ cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-swit
 [15:31] rainbow:P4-NetFPGA%
 \end{verbatim}
 
-Most often occured error:
-\begin{verbatim}
- # open_run impl_1
- ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
- Vivado%
-\end{verbatim}
-
 \begin{verbatim}
 ERROR: [BD 41-171] The modes of the interface pins 'cfg_interrupt'(Slave) and 'pcie3_cfg_interrupt'(Slave) are incompatible. They cannot be connected.
 ERROR: [BD 5-3] Error: running connect_bd_intf_net.