++doc, use nf3

This commit is contained in:
Nico Schottelius 2019-06-03 21:56:45 +02:00
parent f347e35e71
commit 442ea1a7da
3 changed files with 27 additions and 18 deletions

View File

@ -1423,15 +1423,11 @@ Please make sure that it is installed and available in your $PATH:
** TODO Setup test VM [dual stack] for tayga:
** TODO Port to Hardware
*** DONE Get access to tofino: no, NDA issues
*** TODO Get NetFPGA running
*** DONE Get NetFPGA running
**** DONE Understand the simulations part -> not atm
**** DONE Install vivado
**** DONE Install SDNET
**** TODO Create either HDL or PX for supporting payload checksum
https://github.com/NetFPGA/P4-NetFPGA-public/issues/13
https://github.com/NetFPGA/P4-NetFPGA-public/issues/13#issuecomment-490431016
***** TODO Explore HDL
***** TODO Explore PX
**** DONE fix license issue
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
echo ok
@ -1799,7 +1795,7 @@ cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-swit
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
[15:31] rainbow:P4-NetFPGA%
***** TODO run step 10: compiling the bitstream [takes hours]
***** DONE run step 10: compiling the bitstream [takes hours]
****** command
#+BEGIN_CENTER
cd $NF_DESIGN_DIR && make
@ -1951,7 +1947,7 @@ INFO: [Common 17-206] Exiting Vivado at Sat May 25 11:52:01 2019...
#+END_CENTER
****** TODO try6: go back to clean netpfga-live, diff all sources
****** DONE try6: go back to clean netpfga-live, diff all sources
#+BEGIN_CENTER
@ -1979,8 +1975,7 @@ diff -ru /home/nico/P4-NetFPGA-live-clean/tools/settings.sh /home/nico/projects/
#+END_CENTER
****** TODO try7: restart from beginning in minip4 alongside try6
****** DONE try7: restart from beginning in minip4 alongside try6
- steps 1...8 ok
- step 9: fails to cp axi files
- step 9: before that a python error
@ -2181,7 +2176,6 @@ new dic: OrderedDict()
-> Problem seems to be that no addresses are left. Why?
****** DONE try10: find out, why nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt has too less content
******* DONE find out what generates config_writes.txt
Seems to be step 5:
@ -2273,7 +2267,7 @@ Modifying / adjusting P4 code to mirror input packets
******** switch_calc_headers creates some headers
some specific packet, uses bind_layers
****** TODO try11: fixing gen_testdata, adding p4 code for mirroring
****** DONE try11: fixing gen_testdata, adding p4 code for mirroring
Failure again at step 5:
#+BEGIN_CENTER
@ -2328,7 +2322,6 @@ INFO: [Common 17-206] Exiting xsim at Sun May 26 11:14:34 2019...
Started compiling the bitstream at around 1120
Ended at Sun 26 May 2019 01:09:05 PM CEST
***** run step 11: checking design -- skipped
***** DONE run step 12: ok
****** code
@ -2675,7 +2668,7 @@ root@rainbow:~/master-thesis/netpfga/minip4/simple_sume_switch/bitfiles#
#+END_CENTER
***** TODO Step 14: test the card / switch
***** DONE Step 14: test the card / switch
****** try1: adding ips, using tcpdump
******* testing enp16s0
#+BEGIN_CENTER
@ -2892,13 +2885,28 @@ command along with other options to effect HDL simulation
VHDL->[via xvhdl]-> HDL
Verilog->[via xvlog]->HDL
***** TODO Understand SimpleSumeSwitch
***** Understand SimpleSumeSwitch
SimpleSumeSwitch(
TopParser(),
TopPipe(),
TopDeparser()
) main;
**** TODO Understand the different switch models (?)
**** Understand the different switch models (?)
*** TODO Get ANY p4 program to successfully run on netpfga
**** sending data to switch port 1
***** figuring out which port 1
applyPkt(pkt, 'nf0', pktCnt)
expPkt(pkt, 'nf2')
# 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
# 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000010010000 >
*** TODO Create either HDL or PX for supporting payload checksum
https://github.com/NetFPGA/P4-NetFPGA-public/issues/13
https://github.com/NetFPGA/P4-NetFPGA-public/issues/13#issuecomment-490431016
**** TODO Explore HDL
**** TODO Explore PX
** NAT64/NAT46 Features in jool and tayga
*** TODO Static 1:1 NAT46: translate from IPv4 to IPv6 with a table
**** TODO TCP

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@ -12,11 +12,12 @@ read something
cd $P4_PROJECT_DIR && make
# Step 5
cd $P4_PROJECT_DIR/nf_sume_sdnet_ip/SimpleSumeSwitch && ./vivado_sim.bash >LOG 2>&1
cd $P4_PROJECT_DIR/nf_sume_sdnet_ip/SimpleSumeSwitch && ./vivado_sim.bash 2>&1 | tee LOG
expected_line=$(grep ^expected LOG | sed 's/.*= <//')
actual_line=$(grep ^actual LOG | sed 's/.*= <//')
if [ "$expected_line" != "$actual_line" ]; then
echo packet mismatch
exit 1

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@ -108,7 +108,7 @@ def test_port1():
pkt = Ether(dst=MAC2, src=MAC1)
pkt = pad_pkt(pkt, 64)
applyPkt(pkt, 'nf0', pktCnt)
expPkt(pkt, 'nf2')
expPkt(pkt, 'nf3')
# Test that packets are being mirrored
def test_mirror():