Merge branch 'master' of gitlab.ethz.ch:nicosc/master-thesis
This commit is contained in:
Nico Schottelius
commit
45ed7762b2
1 changed files with 147 additions and 1 deletions
148
doc/plan.org
148
doc/plan.org
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@ -5944,7 +5944,138 @@ Opening simple_sume_switch Implementation design
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ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
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ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
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Vivado%
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Vivado%
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#+END_CENTER
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#+END_CENTER
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**** TODO try8: use new script generating different sequences/objects in gen_testdata
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**** DONE try8: use new script generating different sequences/objects in gen_testdata
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CLOSED: [2019-07-21 Sun 19:00]
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output around gen_testdata:
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#+BEGIN_CENTER
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./gen_testdata.py
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Applying pkt on nf0 at 1:
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Applying pkt on nf1 at 2:
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Applying pkt on nf2 at 3:
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Applying pkt on nf3 at 4:
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nf0_applied times: [1]
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nf1_applied times: [2]
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nf2_applied times: [3]
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nf3_applied times: [4]
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nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ cat /home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt
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<addr, data>: (00000020, 00000001)
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<addr, data>: (00000020, 00000000)
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nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ ls -alh /home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt
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-rw-rw-r-- 1 nico nico 70 Jul 21 16:44 /home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt
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nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ date
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Son Jul 21 16:48:08 CEST 2019
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#+END_CENTER
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**** TODO try9: generated files missing
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#+BEGIN_CENTER
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
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WARNING: [IP_Flow 19-3664] IP 'bd_7ad4_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-14144-nsg-System/coregen/bd_7ad4_xpcs_0_1/elaborate/configure_gt.tcl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'bd_a1aa_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-14144-nsg-System/coregen/bd_a1aa_xpcs_0_2/elaborate/configure_gt.tcl'. Please regenerate to continue.
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#+END_CENTER
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One (maybe critical) error message on the way
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#+BEGIN_CENTER
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ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
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#+END_CENTER
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#+BEGIN_CENTER
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WARNING: [Synth 8-689] width (12) of port connection 'control_S_AXI_ARADDR' does not match port width (8) of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:199]
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ERROR: [Synth 8-448] named port connection 'tuple_out_sume_metadata_VALID' does not exist for instance 'SimpleSumeSwitch_inst' of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:218]
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ERROR: [Synth 8-448] named port connection 'tuple_out_sume_metadata_DATA' does not exist for instance 'SimpleSumeSwitch_inst' of module 'SimpleSumeSwitch' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:219]
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ERROR: [Synth 8-6156] failed synthesizing module 'nf_sume_sdnet' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:44]
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ERROR: [Synth 8-6156] failed synthesizing module 'nf_sume_sdnet_ip' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/synth/nf_sume_sdnet_ip.v:57]
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ERROR: [Synth 8-6156] failed synthesizing module 'nf_datapath' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/nf_datapath.v:44]
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ERROR: [Synth 8-6156] failed synthesizing module 'top' [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/hdl/top.v:43]
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#+END_CENTER
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Finding all errors/warnings:
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#+BEGIN_CENTER
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[19:05] line:log% grep -i -e error -e warn compile-2019-07-21-164256 | wc -l
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328
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[19:05] line:log% grep -i -e error compile-2019-07-21-164256 | wc -l
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68
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#+END_CENTER
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Log from beginning to end
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#+BEGIN_CENTER
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata
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orig dic: OrderedDict([(0, ('00000020', '00000001')), (1, ('00000020', '00000000'))])
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new dic: OrderedDict()
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WARNING: [IP_Flow 19-3656] If you move the project, the path for
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repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become
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invalid. A better location for the repository would be in a path
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adjacent to the project. (Current project location is
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'/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
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WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/wrapper/changeEndian.v'.
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WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.h'.
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WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp'.
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INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
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INFO: [IP_Flow 19-2187] The Product Guide file is missing.
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WARNING: command 'get_user_parameter' will be removed in the 2015.3
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release, use 'get_user_parameters' instead
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echo 16028002 >> rom_data.txt
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echo `/home/nico/projects/P4-NetFPGA/run_tag.sh` >> rom_data.txt
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grep: ../../../RELEASE_NOTES: No such file or directory
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echo 00000204 >> rom_data.txt
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## create_root_design ""
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CRITICAL WARNING: [BD 41-737] Cannot set the parameter TRANSLATION_MODE on /axi_interconnect_0. It is read-only.
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### set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
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update_compile_order: Time (s): cpu = 00:00:21 ; elapsed = 00:00:11 . Memory (MB): peak = 2029.402 ; gain = 8.012 ; free physical = 9120 ; free virtual = 14551
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loading libsume..
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Traceback (most recent call last):
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py", line 42, in <module>
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import config_writes
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py", line 7
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^
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IndentationError: expected an indented block
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while executing
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"exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py"
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invoked from within
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"set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]"
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(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 177)
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INFO: [Common 17-206] Exiting Vivado at Sun Jul 21 16:46:22 2019...
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Makefile:120: recipe for target 'sim' failed
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make: *** [sim] Error 1
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make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
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#+END_CENTER
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#+BEGIN_CENTER
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nico@nsg-System:~$ cat ~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py
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from NFTest import *
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NUM_WRITES = 0
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def config_tables():
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#+END_CENTER
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**** fact9: generated python script has a syntax error
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#+BEGIN_CENTER
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~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py
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#+END_CENTER
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*** TODO Further notes P4/master thesis
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*** TODO Further notes P4/master thesis
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- Cannot easily run P4 on notebook - changes to the system very
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- Cannot easily run P4 on notebook - changes to the system very
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invasive
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invasive
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@ -5963,6 +6094,21 @@ control_sub_m02_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-proj
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nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ less /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log
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nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ less /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log: No such file or directory
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log: No such file or directory
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- A script/makefile generates a python script that generates a shell
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script and later then a python script. If there is a mistake in
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generating the first python script (syntax ok, but content is
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not correct) then a much later stage of the compile process will
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fail due to a syntax error in the third generated
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script. However that syntax error is not fatal in the build
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process and thus can only be seen with careful analysis of the
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logfile, which is around 700 KiB or 10k lines per compile
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process and contains 328 lines matching "error" and
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"warning".
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Most of the error and warning messages seem to be non-critical
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(even if saying they are). Then there are a variety of INFO
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messages that actually constitute ERROR messages, but are not
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flagged as such nor do they cause the build process to abort.
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** The NetPFGA saga
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** The NetPFGA saga
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Problems encountered:
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Problems encountered:
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