nico/master-thesis
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

rename dir

Browse source 
Signed-off-by: Nico Schottelius <nico@nico-notebook.schottelius.org>
This commit is contained in:
Nico Schottelius 2019-08-21 11:39:09 +02:00
commit 50971dc10c
197 changed files with 0 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

95
netfpga/minip4/simple_sume_switch/sw/embedded/Makefile Normal file
View file

@ -0,0 +1,95 @@
#
# Copyright (c) 2015 University of Cambridge
# Modified by Salvator Galea
# All rights reserved.
#
# File:
# Makefile
#
# Project:
# reference projects
#
#
# Description:
# This makefile is used to generate and compile SDK project for reference projects.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# Vivado Launch Script
################################################################################
WS = SDK_Workspace
PROJ = ${NF_PROJECT_NAME}
.PHONY: distclean clean project compile download
all:
@echo ""
@echo "NetFPGA-SUME Reference Project SW Makefile"
@echo ""
@echo "make TARGETS"
@echo "------------------------------------------------------"
@echo "project: Create software project"
@echo "compile: Compile specified project"
@echo "download: Download and run specified project via xmd"
@echo ""
@echo "clean: Remove specified project"
@echo "distclean: Remove all generated projects"
@echo ""
project:
@if [ -d ./${WS} ]; then rm -rf ./${WS}; fi
mkdir ./${WS}
xsdk -batch -source ./tcl/${PROJ}_xsdk.tcl
# Compile Command needs to run twice to get sw compiled correctly in DEBUG mode
compile:
@if [ -d ./${WS} ]; then \
cp -a ./src/. ./${WS}/${PROJ}/app/src/; \
xsdk -wait -eclipseargs -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -build all -data ./${WS}/${PROJ} -vmargs -Dorg.eclipse.cdt.core.console=org.eclipse.cdt.core.systemConsole; \
xsdk -wait -eclipseargs -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -build all -data ./${WS}/${PROJ} -vmargs -Dorg.eclipse.cdt.core.console=org.eclipse.cdt.core.systemConsole; \
else \
echo "SDK_Workspace not found"; \
fi
download:
@if [ -d ./../bitfiles ]; then \
xmd -tcl ./tcl/download.tcl `find ./../bitfiles -name "*.bit"`; \
else \
echo "Bitfile folder not found"; \
fi
clean:
rm -rf ./${WS}
rm -rf *.log
rm -rf *.jou
distclean:
rm -rf `find . -name "${WS}"`
rm -rf `find . -name "*.log"`
rm -rf `find . -name "*.jou"`

678
netfpga/minip4/simple_sume_switch/sw/embedded/reg_defines.h Normal file
View file

@ -0,0 +1,678 @@
//-
// Copyright (c) 2015 University of Cambridge
// All rights reserved.
//
// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
// under National Science Foundation under Grant No. CNS-0855268,
// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
// as part of the DARPA MRC research programme.
//
// @NETFPGA_LICENSE_HEADER_START@
//
// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. NetFPGA licenses this
// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.netfpga-cic.org
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @NETFPGA_LICENSE_HEADER_END@
/////////////////////////////////////////////////////////////////////////////////
// This is an automatically generated header definitions file
/////////////////////////////////////////////////////////////////////////////////
//######################################################
//# Definitions for MICROBLAZE_AXI_IIC
//######################################################
#define SUME_MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
#define SUME_MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
#define SUME_MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_UARTLITE
//######################################################
#define SUME_MICROBLAZE_UARTLITE_BASEADDR 0x40600000
#define SUME_MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
#define SUME_MICROBLAZE_UARTLITE_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_DLMB_BRAM
//######################################################
#define SUME_MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
#define SUME_MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
#define SUME_MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_ILMB_BRAM
//######################################################
#define SUME_MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
#define SUME_MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
#define SUME_MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_AXI_INTC
//######################################################
#define SUME_MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
#define SUME_MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
#define SUME_MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
//######################################################
//# Definitions for INPUT_ARBITER
//######################################################
#define SUME_INPUT_ARBITER_BASEADDR 0x44010000
#define SUME_INPUT_ARBITER_HIGHADDR 0x44010FFF
#define SUME_INPUT_ARBITER_SIZEADDR 0x1000
#define SUME_INPUT_ARBITER_0_ID 0x44010000
#define SUME_INPUT_ARBITER_0_ID_DEFAULT 0x0000DA01
#define SUME_INPUT_ARBITER_0_ID_WIDTH 32
#define SUME_INPUT_ARBITER_0_VERSION 0x44010004
#define SUME_INPUT_ARBITER_0_VERSION_DEFAULT 0x1
#define SUME_INPUT_ARBITER_0_VERSION_WIDTH 32
#define SUME_INPUT_ARBITER_0_RESET 0x44010008
#define SUME_INPUT_ARBITER_0_RESET_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_RESET_WIDTH 16
#define SUME_INPUT_ARBITER_0_FLIP 0x4401000c
#define SUME_INPUT_ARBITER_0_FLIP_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_FLIP_WIDTH 32
#define SUME_INPUT_ARBITER_0_DEBUG 0x44010010
#define SUME_INPUT_ARBITER_0_DEBUG_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_DEBUG_WIDTH 32
#define SUME_INPUT_ARBITER_0_PKTIN 0x44010014
#define SUME_INPUT_ARBITER_0_PKTIN_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_PKTIN_WIDTH 32
#define SUME_INPUT_ARBITER_0_PKTOUT 0x44010018
#define SUME_INPUT_ARBITER_0_PKTOUT_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_PKTOUT_WIDTH 32
//######################################################
//# Definitions for OUTPUT_QUEUES
//######################################################
#define SUME_OUTPUT_QUEUES_BASEADDR 0x44030000
#define SUME_OUTPUT_QUEUES_HIGHADDR 0x44030FFF
#define SUME_OUTPUT_QUEUES_SIZEADDR 0x1000
#define SUME_OUTPUT_QUEUES_0_ID 0x44030000
#define SUME_OUTPUT_QUEUES_0_ID_DEFAULT 0x0000DA03
#define SUME_OUTPUT_QUEUES_0_ID_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_VERSION 0x44030004
#define SUME_OUTPUT_QUEUES_0_VERSION_DEFAULT 0x1
#define SUME_OUTPUT_QUEUES_0_VERSION_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_RESET 0x44030008
#define SUME_OUTPUT_QUEUES_0_RESET_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_RESET_WIDTH 16
#define SUME_OUTPUT_QUEUES_0_FLIP 0x4403000c
#define SUME_OUTPUT_QUEUES_0_FLIP_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_FLIP_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_DEBUG 0x44030010
#define SUME_OUTPUT_QUEUES_0_DEBUG_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_DEBUG_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTIN 0x44030014
#define SUME_OUTPUT_QUEUES_0_PKTIN_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTIN_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTOUT 0x44030018
#define SUME_OUTPUT_QUEUES_0_PKTOUT_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTOUT_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0 0x4403001c
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0 0x44030020
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0 0x44030024
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0 0x44030028
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0 0x4403002c
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0 0x44030030
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0 0x44030034
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1 0x44030038
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1 0x4403003c
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1 0x44030040
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1 0x44030044
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1 0x44030048
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1 0x4403004c
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1 0x44030050
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2 0x44030054
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2 0x44030058
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2 0x4403005c
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2 0x44030060
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2 0x44030064
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2 0x44030068
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2 0x4403006c
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3 0x44030070
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3 0x44030074
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3 0x44030078
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3 0x4403007c
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3 0x44030080
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3 0x44030084
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3 0x44030088
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4 0x4403008c
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4 0x44030090
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4 0x44030094
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4 0x44030098
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4 0x4403009c
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4 0x440300a0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4 0x440300a4
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_WIDTH 32
//######################################################
//# Definitions for OUTPUT_PORT_LOOKUP
//######################################################
#define SUME_OUTPUT_PORT_LOOKUP_BASEADDR 0x44020000
#define SUME_OUTPUT_PORT_LOOKUP_HIGHADDR 0x44020FFF
#define SUME_OUTPUT_PORT_LOOKUP_SIZEADDR 0x1000
#define SUME_OUTPUT_PORT_LOOKUP_0_ID 0x44020000
#define SUME_OUTPUT_PORT_LOOKUP_0_ID_DEFAULT 0x0001DA02
#define SUME_OUTPUT_PORT_LOOKUP_0_ID_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION 0x44020004
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_DEFAULT 0x1
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET 0x44020008
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_WIDTH 16
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP 0x4402000c
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG 0x44020010
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN 0x44020014
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT 0x44020018
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT 0x4402001c
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS 0x44020020
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE0
//######################################################
#define SUME_NF_10G_INTERFACE0_BASEADDR 0x44040000
#define SUME_NF_10G_INTERFACE0_HIGHADDR 0x44040FFF
#define SUME_NF_10G_INTERFACE0_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_SHARED_0_ID 0x44040000
#define SUME_NF_10G_INTERFACE_SHARED_0_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_SHARED_0_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION 0x44040004
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET 0x44040008
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP 0x4404000c
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG 0x44040010
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID 0x44040014
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN 0x44040018
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT 0x4404001c
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR 0x44040020
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS 0x44040024
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0 0x44040028
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1 0x4404002c
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2 0x44040030
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3 0x44040034
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4 0x44040038
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5 0x4404003c
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6 0x44040040
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7 0x44040044
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8 0x44040048
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9 0x4404004c
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10 0x44040050
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11 0x44040054
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12 0x44040058
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13 0x4404005c
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE1
//######################################################
#define SUME_NF_10G_INTERFACE1_BASEADDR 0x44050000
#define SUME_NF_10G_INTERFACE1_HIGHADDR 0x44050FFF
#define SUME_NF_10G_INTERFACE1_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_1_ID 0x44050000
#define SUME_NF_10G_INTERFACE_1_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_1_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_VERSION 0x44050004
#define SUME_NF_10G_INTERFACE_1_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_1_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_RESET 0x44050008
#define SUME_NF_10G_INTERFACE_1_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_1_FLIP 0x4405000c
#define SUME_NF_10G_INTERFACE_1_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_DEBUG 0x44050010
#define SUME_NF_10G_INTERFACE_1_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_INTERFACEID 0x44050014
#define SUME_NF_10G_INTERFACE_1_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PKTIN 0x44050018
#define SUME_NF_10G_INTERFACE_1_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PKTOUT 0x4405001c
#define SUME_NF_10G_INTERFACE_1_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR 0x44050020
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS 0x44050024
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0 0x44050028
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1 0x4405002c
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2 0x44050030
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3 0x44050034
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4 0x44050038
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5 0x4405003c
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6 0x44050040
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7 0x44050044
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8 0x44050048
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9 0x4405004c
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10 0x44050050
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11 0x44050054
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12 0x44050058
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13 0x4405005c
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE2
//######################################################
#define SUME_NF_10G_INTERFACE2_BASEADDR 0x44060000
#define SUME_NF_10G_INTERFACE2_HIGHADDR 0x44060FFF
#define SUME_NF_10G_INTERFACE2_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_2_ID 0x44060000
#define SUME_NF_10G_INTERFACE_2_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_2_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_VERSION 0x44060004
#define SUME_NF_10G_INTERFACE_2_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_2_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_RESET 0x44060008
#define SUME_NF_10G_INTERFACE_2_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_2_FLIP 0x4406000c
#define SUME_NF_10G_INTERFACE_2_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_DEBUG 0x44060010
#define SUME_NF_10G_INTERFACE_2_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_INTERFACEID 0x44060014
#define SUME_NF_10G_INTERFACE_2_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PKTIN 0x44060018
#define SUME_NF_10G_INTERFACE_2_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PKTOUT 0x4406001c
#define SUME_NF_10G_INTERFACE_2_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR 0x44060020
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS 0x44060024
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0 0x44060028
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1 0x4406002c
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2 0x44060030
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3 0x44060034
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4 0x44060038
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5 0x4406003c
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6 0x44060040
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7 0x44060044
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8 0x44060048
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9 0x4406004c
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10 0x44060050
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11 0x44060054
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12 0x44060058
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13 0x4406005c
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE3
//######################################################
#define SUME_NF_10G_INTERFACE3_BASEADDR 0x44070000
#define SUME_NF_10G_INTERFACE3_HIGHADDR 0x44070FFF
#define SUME_NF_10G_INTERFACE3_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_3_ID 0x44070000
#define SUME_NF_10G_INTERFACE_3_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_3_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_VERSION 0x44070004
#define SUME_NF_10G_INTERFACE_3_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_3_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_RESET 0x44070008
#define SUME_NF_10G_INTERFACE_3_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_3_FLIP 0x4407000c
#define SUME_NF_10G_INTERFACE_3_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_DEBUG 0x44070010
#define SUME_NF_10G_INTERFACE_3_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_INTERFACEID 0x44070014
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PKTIN 0x44070018
#define SUME_NF_10G_INTERFACE_3_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PKTOUT 0x4407001c
#define SUME_NF_10G_INTERFACE_3_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR 0x44070020
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS 0x44070024
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0 0x44070028
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1 0x4407002c
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2 0x44070030
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3 0x44070034
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4 0x44070038
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5 0x4407003c
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6 0x44070040
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7 0x44070044
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8 0x44070048
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9 0x4407004c
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10 0x44070050
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11 0x44070054
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12 0x44070058
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13 0x4407005c
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_RIFFA_DMA
//######################################################
#define SUME_NF_RIFFA_DMA_BASEADDR 0x44080000
#define SUME_NF_RIFFA_DMA_HIGHADDR 0x44080FFF
#define SUME_NF_RIFFA_DMA_SIZEADDR 0x1000
#define SUME_NF_RIFFA_DMA_0_ID 0x44080000
#define SUME_NF_RIFFA_DMA_0_ID_DEFAULT 0x00001FFA
#define SUME_NF_RIFFA_DMA_0_ID_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_VERSION 0x44080004
#define SUME_NF_RIFFA_DMA_0_VERSION_DEFAULT 0x1
#define SUME_NF_RIFFA_DMA_0_VERSION_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RESET 0x44080008
#define SUME_NF_RIFFA_DMA_0_RESET_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RESET_WIDTH 16
#define SUME_NF_RIFFA_DMA_0_FLIP 0x4408000c
#define SUME_NF_RIFFA_DMA_0_FLIP_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_FLIP_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_DEBUG 0x44080010
#define SUME_NF_RIFFA_DMA_0_DEBUG_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_DEBUG_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RQPKT 0x44080014
#define SUME_NF_RIFFA_DMA_0_RQPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RQPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RCPKT 0x44080018
#define SUME_NF_RIFFA_DMA_0_RCPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RCPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_CQPKT 0x4408001c
#define SUME_NF_RIFFA_DMA_0_CQPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_CQPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_CCPKT 0x44080020
#define SUME_NF_RIFFA_DMA_0_CCPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_CCPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_XGETXPKT 0x44080024
#define SUME_NF_RIFFA_DMA_0_XGETXPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_XGETXPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_XGERXPKT 0x44080028
#define SUME_NF_RIFFA_DMA_0_XGERXPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_XGERXPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIERQ 0x4408002c
#define SUME_NF_RIFFA_DMA_0_PCIERQ_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIERQ_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEPHY 0x44080030
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG 0x44080034
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2 0x44080038
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEERROR 0x4408003c
#define SUME_NF_RIFFA_DMA_0_PCIEERROR_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEERROR_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMISC 0x44080040
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIETPH 0x44080044
#define SUME_NF_RIFFA_DMA_0_PCIETPH_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIETPH_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC1 0x44080048
#define SUME_NF_RIFFA_DMA_0_PCIEFC1_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC1_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC2 0x4408004c
#define SUME_NF_RIFFA_DMA_0_PCIEFC2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC3 0x44080050
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT 0x44080054
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA 0x44080058
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT 0x4408005c
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS 0x44080060
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2 0x44080064
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2 0x44080068
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_WIDTH 32

235
netfpga/minip4/simple_sume_switch/sw/embedded/src/helloworld.c Normal file
View file

@ -0,0 +1,235 @@
/*
* Copyright (c) 2015 Digilent Inc.
* Copyright (c) 2015 Tinghui Wang (Steve)
* All rights reserved.
*
* File:
* sw/embedded/src/helloworld.c
*
* Project:
* Reference project
*
* Author:
* Tinghui Wang (Steve)
*
* Description:
* Reference project main function.
*
* @NETFPGA_LICENSE_HEADER_START@
*
* Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. NetFPGA licenses this
* file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.netfpga-cic.org
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* @NETFPGA_LICENSE_HEADER_END@
*
*/
#include <stdio.h>
#include "platform.h"
#include "xparameters.h"
#include "string.h"
#include "xiic.h"
#include "xintc.h"
#include "xil_types.h"
#include "platform.h"
#include "mb_interface.h"
#include "xuartlite_l.h"
#define IIC_DEVICE_ID XPAR_IIC_0_DEVICE_ID
#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
#define IIC_INTR_ID XPAR_INTC_0_IIC_0_VEC_ID
XIic IicInstance; /* The instance of the IIC device. */
XIntc InterruptController; /* The instance of the Interrupt Controller. */
/*
* printTestResult
*
* Print "Passed/Failed" for some test category based on the auto test return value
*/
void printTestResult (char* testName, XStatus result) {
int dotLen = 40 - strlen(testName);
int i;
xil_printf("%s", testName);
for(i = 0; i < dotLen; i++) {
xil_printf(".");
}
if(result == XST_SUCCESS) {
xil_printf("Passed\r\n");
} else {
xil_printf("Failed\r\n");
}
return;
}
/*
* runAutoTest
*
* Test all the interface supported by the project automatically
*/
void runAutoTest(void) {
}
/*
* runManualTest
*
* Provide a menu for user to test each interface manually
*/
void runManualTest(void) {
xil_printf("\r\n");
while(1) {
xil_printf("---- NetFPGA-SUME Manual Test Menu ----\r\n");
xil_printf("p: Read Power Info\r\n");
xil_printf("b: Back to Main Menu\r\n");
xil_printf("Select: ");
char cmd = XUartLite_RecvByte(XPAR_UARTLITE_0_BASEADDR);
xil_printf("%c\r\n", cmd);
switch (cmd) {
case 'p':
pmReadInfo();
break;
case 'b':
return;
default:
break;
}
xil_printf("\r\n");
}
}
int main()
{
int Status;
init_platform();
xil_printf("NetFPGA-SUME SI5324 Configuration\r\n");
/*
* Setup Iic Instance
*/
Status = IicInit(&IicInstance);
if (Status != XST_SUCCESS) {
xil_printf("I2C Initialization FAILED\n\r");
return XST_FAILURE;
}
/*
* Setup the Interrupt System.
*/
Status = SetupInterruptSystem(&IicInstance);
if (Status != XST_SUCCESS) {
xil_printf("SetupInterruptSystem FAILED\n\r");
return XST_FAILURE;
}
/*
* Enable Iic Bus
*/
Status = IicInitPost(&IicInstance);
if (Status != XST_SUCCESS) {
xil_printf("I2C Initialization FAILED\n\r");
return XST_FAILURE;
}
config_SI5324();
while(1) {
xil_printf("============ NetFPGA-SUME ============\n\r");
xil_printf("m: Manual Test \r\n");
xil_printf("Select: ");
char cmd = XUartLite_RecvByte(XPAR_UARTLITE_0_BASEADDR);
xil_printf("%c\r\n", cmd);
switch (cmd) {
case 'm':
runManualTest();
break;
default:
break;
}
xil_printf("\r\n");
}
return 0;
}
/*****************************************************************************/
/**
* This function setups the interrupt system so interrupts can occur for the
* IIC device. The function is application-specific since the actual system may
* or may not have an interrupt controller. The IIC device could be directly
* connected to a processor without an interrupt controller. The user should
* modify this function to fit the application.
*
* @param IicInstPtr contains a pointer to the instance of the IIC device
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
int SetupInterruptSystem(XIic * IicInstPtr)
{
int Status;
if (InterruptController.IsStarted == XIL_COMPONENT_IS_STARTED) {
return XST_SUCCESS;
}
/*
* Initialize the interrupt controller driver so that it's ready to use.
*/
Status = XIntc_Initialize(&InterruptController, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XIntc_Connect(&InterruptController, IIC_INTR_ID,
(XInterruptHandler) XIic_InterruptHandler,
IicInstPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Start the interrupt controller so interrupts are enabled for all
* devices that cause interrupts.
*/
Status = XIntc_Start(&InterruptController, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupts for the IIC device.
*/
XIntc_Enable(&InterruptController, IIC_INTR_ID);
/*
* Enable the Microblaze Interrupts.
*/
microblaze_enable_interrupts();
return XST_SUCCESS;
}

603
netfpga/minip4/simple_sume_switch/sw/embedded/src/iic_config.c Normal file
View file

@ -0,0 +1,603 @@
/*
* Copyright (c) 2015 Digilent Inc.
* Copyright (c) 2015 Tinghui Wang (Steve)
* All rights reserved.
*
* File:
* sw/embedded/src/iic_config.c
*
* Project:
* Reference project
*
* Author:
* Tinghui Wang (Steve)
*
* Description:
* Read/Write functions with timeout ability for IIC communication used by
* acceptance_test project.
*
* @NETFPGA_LICENSE_HEADER_START@
*
* Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. NetFPGA licenses this
* file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.netfpga-cic.org
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* @NETFPGA_LICENSE_HEADER_END@
*
*/
#include "iic_config.h"
#include "xiic.h"
#include "xintc.h"
#include "xstatus.h"
#include "xil_types.h"
#include "xparameters.h"
#include "math.h"
/*
* Flags for IIC Transmit/Receive
*/
int TransmitComplete = 0;
int ReceiveComplete = 0;
extern XIic IicInstance;
/*
* Initialize Iic Structure
*/
int IicInit(XIic *IicInstPtr) {
XIic_Config *IicConfigPtr;
int Status;
/*
* Initialize the IIC device Instance.
*/
IicConfigPtr = XIic_LookupConfig(XPAR_IIC_0_DEVICE_ID);
if (IicConfigPtr == NULL) {
return XST_FAILURE;
}
/*
* Initialize Iic Instance with Config Ptr
*/
Status = XIic_CfgInitialize(IicInstPtr, IicConfigPtr, IicConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Error: XIic_Initialize FAILED\n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*
* Iic Send Handler
* Reset Transmit Flag to 0 after Transmit is done
*/
static void IicSendHandler(XIic *IicInstPtr) {
TransmitComplete = 0;
}
/*
* Iic Receive Handler
* Reset Receive Flag to 0 after Transmit is done
*/
static void IicRecvHandler(XIic *IicInstPtr) {
ReceiveComplete = 0;
}
/*
* Iic Status Handler
* Do nothing
*/
static void IicStatusHandler(XIic *IicInstPtr) {
return;
}
/*
* Iic Post Initialization Procedure
* Need to be called after Interrupt system is configured.
*/
int IicInitPost(XIic *IicInstPtr) {
// Setup Handlers for transmit and reception
XIic_SetSendHandler(IicInstPtr, IicInstPtr, (XIic_Handler) IicSendHandler);
XIic_SetRecvHandler(IicInstPtr, IicInstPtr, (XIic_Handler) IicRecvHandler);
XIic_SetStatusHandler(IicInstPtr, IicInstPtr, (XIic_StatusHandler) IicStatusHandler);
// Release reset on the PCA9548 IIC Switch
XIic_SetGpOutput(IicInstPtr, 0xFF);
XIic_SetGpOutput(IicInstPtr, 0x00);
return XST_SUCCESS;
}
/*
* *********************************************************
* IicReadData with address added as an input parameter - Repeated Start
* *********************************************************
*/
int IicReadData(u8 IicAddr, u8 addr, u8 *BufferPtr, u16 ByteCount)
{
int Status;
u8 IicOptions;
u32 IicTimeoutCounter = 0;
/*
* Set Receive Flag
*/
ReceiveComplete = 1;
IicOptions = XIic_GetOptions(&IicInstance);
XIic_SetOptions(&IicInstance, IicOptions | XII_REPEATED_START_OPTION);
/*
* Start Iic Device
*/
Status = XIic_Start(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Start failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Set Iic Address
*/
Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE, IicAddr);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Set Address failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Write addr to the device
*/
// Mark the Transmit Flag
TransmitComplete = 1;
IicInstance.Stats.TxErrors = 0;
/*
* Send the Data
*/
Status = XIic_MasterSend(&IicInstance, &addr, 1);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Master Send failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Wait till the transmission is completed
*/
while((TransmitComplete) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Clear Repeated Start option
*/
XIic_SetOptions(&IicInstance, IicOptions);
/*
* Handle Tx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Write Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Receive Data
*/
Status = XIic_MasterRecv(&IicInstance, BufferPtr, ByteCount);
if(Status != XST_SUCCESS) {
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Master Recv Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
}
/*
* Wait until all the data is received
*/
IicTimeoutCounter = 0;
while(((ReceiveComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Handle Rx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Recv Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Stop Iic
*/
Status = XIic_Stop(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Stop Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*
* *********************************************************
* IicReadData with address added as an input parameter - Stop
* *********************************************************
*/
int IicReadData2(u8 IicAddr, u8 addr, u8 *BufferPtr, u16 ByteCount)
{
int Status;
u32 IicTimeoutCounter = 0;
/*
* Set Receive Flag
*/
ReceiveComplete = 1;
/*
* Start Iic Device
*/
Status = XIic_Start(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Start failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Set Iic Address
*/
Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE, IicAddr);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Set Address failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Write addr to the device
*/
// Mark the Transmit Flag
TransmitComplete = 1;
IicInstance.Stats.TxErrors = 0;
/*
* Send the Data
*/
Status = XIic_MasterSend(&IicInstance, &addr, 1);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Master Send failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Wait till the transmission is completed
*/
while(((TransmitComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Handle Tx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Write Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData2: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Receive Data
*/
Status = XIic_MasterRecv(&IicInstance, BufferPtr, ByteCount);
if(Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Master Recv Failed with status %x\r\n", Status);
#endif
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
/*
* Wait until all the data is received
*/
IicTimeoutCounter = 0;
while(((ReceiveComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Handle Rx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Recv Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData2: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Stop Iic
*/
Status = XIic_Stop(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Stop Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*
* *********************************************************
* IicReadData3 with address added as an input parameter - two bytes address
* *********************************************************
*/
int IicReadData3(u8 IicAddr, u16 addr, u8 *BufferPtr, u16 ByteCount)
{
int Status;
u8 IicOptions;
u32 IicTimeoutCounter = 0;
/*
* Set Receive Flag
*/
ReceiveComplete = 1;
/*
* Start Iic Device
*/
Status = XIic_Start(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Start failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Set Iic Address
*/
Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE, IicAddr);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Set Address failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Write addr to the device
*/
// Mark the Transmit Flag
TransmitComplete = 1;
IicInstance.Stats.TxErrors = 0;
/*
* Send the Data
*/
u8 addrReorder[2];
u8 *addrPtr;
addrPtr = &addr;
addrReorder[0] = addrPtr[1];
addrReorder[1] = addrPtr[0];
Status = XIic_MasterSend(&IicInstance, addrReorder, 2);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Master Send failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Wait till the transmission is completed
*/
while(((TransmitComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Handle Tx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Write Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData3: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Receive Data
*/
Status = XIic_MasterRecv(&IicInstance, BufferPtr, ByteCount);
if(Status != XST_SUCCESS) {
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Master Recv Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
}
/*
* Wait until all the data is received
*/
IicTimeoutCounter = 0;
while(((ReceiveComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Handle Rx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Recv Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData3: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Stop Iic
*/
Status = XIic_Stop(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Stop Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*
* *********************************************************
* IicWriteData with address added as an input parameter
* *********************************************************
*/
int IicWriteData(u8 IicAddr, u8 *BufferPtr, u16 ByteCount)
{
int Status;
u32 IicTimeoutCounter = 0;
// Mark the Transmit Flag
TransmitComplete = 1;
IicInstance.Stats.TxErrors = 0;
/*
* Start Iic Device
*/
Status = XIic_Start(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicWriteData: IIC Start Device Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Set Iic Address
*/
Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE, IicAddr);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicWriteData: IIC Set Address Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Send the Data
*/
Status = XIic_MasterSend(&IicInstance, BufferPtr, ByteCount);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicWriteData: IIC Master Send failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Wait till the transmission is completed
*/
while(((TransmitComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter++;
}
if (IicTimeoutCounter > IIC_TIMEOUT) {
TransmitComplete = 0;
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicWriteData: IIC Write Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicWriteData: IIC stop failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Stop Iic Device
*/
Status = XIic_Stop(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicWriteData: IIC Stop failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
return XST_SUCCESS;
}

80
netfpga/minip4/simple_sume_switch/sw/embedded/src/iic_config.h Normal file
View file

@ -0,0 +1,80 @@
/*
* Copyright (c) 2015 Digilent Inc.
* Copyright (c) 2015 Tinghui Wang (Steve)
* All rights reserved.
*
* File:
* sw/embedded/src/iic_config.h
*
* Project:
* Reference project
*
* Author:
* Tinghui Wang (Steve)
*
* Description:
* Iic related definition used by Iic communication with NetFPGA-SUME board
*
* @NETFPGA_LICENSE_HEADER_START@
*
* Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. NetFPGA licenses this
* file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.netfpga-cic.org
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* @NETFPGA_LICENSE_HEADER_END@
*
*/
#ifndef IIC_CONFIG_H
#define IIC_CONFIG_H
#include "xil_types.h"
// PCA9548 8-port IIC Switch
#define IIC_SWITCH_ADDRESS 0x74
// Connected to IIC Buses
// Bus 0
#define IIC_BUS_SFP1 0x01
#define IIC_SFP1_ADDRESS 0x50
// Bus 1
#define IIC_BUS_SFP2 0x02
#define IIC_SFP2_ADDRESS 0x50
// Bus 2
#define IIC_BUS_SFP3 0x04
#define IIC_SFP3_ADDRESS 0x50
// Bus 3
#define IIC_BUS_SFP4 0x08
#define IIC_SFP4_ADDRESS 0x50
// Bus 4
#define IIC_BUS_DDR3 0x10
#define IIC_SI5324_ADDRESS 0x68
#define IIC_DDR3A_ADDRESS 0x01
#define IIC_DDR3B_ADDRESS 0x02
// Bus 5
#define IIC_BUS_FMC 0x20
#define IIC_FMC_CPLD 0x58
#define IIC_FMC_CDCM 0x54
#define IIC_FMC_EEPROM 0x50
// Bus 6
#define IIC_BUS_PCON 0x40
// Bus 7
#define IIC_BUS_PMOD 0x80
#define IIC_TIMEOUT 1000000UL
int IicReadData(u8 IicAddr, u8 addr, u8 *BufferPtr, u16 ByteCount);
int IicReadData2(u8 IicAddr, u8 addr, u8 *BufferPtr, u16 ByteCount);
int IicReadData3(u8 IicAddr, u16 addr, u8 *BufferPtr, u16 ByteCount);
int IicWriteData(u8 IicAddr, u8 *BufferPtr, u16 ByteCount);
#endif

209
netfpga/minip4/simple_sume_switch/sw/embedded/src/iic_pm.c Normal file
View file

@ -0,0 +1,209 @@
/*
* Copyright (c) 2015 Digilent Inc.
* Copyright (c) 2015 Tinghui Wang (Steve)
* All rights reserved.
*
* File:
* sw/embedded/src/iic_pm.c
*
* Project:
* Reference project
*
* Author:
* Tinghui Wang (Steve)
*
* Description:
* Iic codes to read power information about NetFPGA-SUME boards through
* PMBus.
*
* @NETFPGA_LICENSE_HEADER_START@
*
* Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. NetFPGA licenses this
* file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.netfpga-cic.org
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* @NETFPGA_LICENSE_HEADER_END@
*
*/
#include "iic_config.h"
#include "xstatus.h"
#include <stdio.h>
#define PM_CMD_LOAD_PAGE 0x00
#define PM_CMD_POUT 0x96
#define PM_CMD_VOUT 0x8B
#define PM_CMD_IOUT 0x8C
struct pm_info {
char* railName;
u8 i2cAddress;
u8 pageIndex;
u16 voltage;
u16 current;
u16 power;
};
struct pm_info pm[8] = {
{
.railName = "VCC1V0",
.i2cAddress = 0x5C,
.pageIndex = 0,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "VCC1V5",
.i2cAddress = 0x5D,
.pageIndex = 2,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "VCC1V8",
.i2cAddress = 0x5C,
.pageIndex = 1,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "VCC2V0",
.i2cAddress = 0x5C,
.pageIndex = 2,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "VCC3V3",
.i2cAddress = 0x5D,
.pageIndex = 1,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "MGTAVCC",
.i2cAddress = 0x5C,
.pageIndex = 3,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "MGTAVTT",
.i2cAddress = 0x5D,
.pageIndex = 0,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "MGTVAUX",
.i2cAddress = 0x5D,
.pageIndex = 3,
.voltage = 0,
.current = 0,
.power = 0
}
};
/*
* This function reads the information of Power Management
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
*/
int pmReadInfo(void) {
int Status;
int i;
u8 WriteBuffer[10];
u8 ReadBuffer[30];
/*
* Write to the IIC Switch.
*/
WriteBuffer[0] = IIC_BUS_PCON; //Select Bus7 - DDR3
Status = IicWriteData(IIC_SWITCH_ADDRESS, WriteBuffer, 1);
if (Status != XST_SUCCESS) {
xil_printf("pmReadInfo: PCA9548 FAILED to select PM IIC Bus\r\n");
return XST_FAILURE;
}
for(i = 0; i < 8; i++) {
int decimal;
int small;
/*
* Load Corresponding Page Info
*/
WriteBuffer[0] = PM_CMD_LOAD_PAGE;
WriteBuffer[1] = pm[i].pageIndex; //Select Bus7 - Si5326
Status = IicWriteData(pm[i].i2cAddress, WriteBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("PMBus[%x]: Load Page %d Failed\r\n", pm[i].i2cAddress, pm[i].pageIndex);
return XST_FAILURE;
}
xil_printf("Power Rail %s:\r\n", pm[i].railName);
Status = IicReadData(pm[i].i2cAddress, PM_CMD_LOAD_PAGE, ReadBuffer, 1);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
// xil_printf("Page: %d\r\n", ReadBuffer[0]);
/*
* Read Voltage
*/
Status = IicReadData(pm[i].i2cAddress, PM_CMD_VOUT, ReadBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("PMBus[%x]: IIC Read Failed\r\n", pm[i].i2cAddress);
return XST_FAILURE;
}
pm[i].voltage = (ReadBuffer[1] << 8) + ReadBuffer[0];
// xil_printf("Voltage: 0x%x 0x%x V\r\n", ReadBuffer[0], ReadBuffer[1]);
// xil_printf("Voltage: 0x%x, %d V\r\n", pm[i].voltage, pm[i].voltage);
decimal = pm[i].voltage >> 13;
small = (pm[i].voltage - (decimal <<13)) * 1000 / (1<<13);
xil_printf("\tVoltage: %d.%d V\r\n", decimal, small);
/*
* Read Current
*/
Status = IicReadData(pm[i].i2cAddress, PM_CMD_IOUT, ReadBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("PMBus[%x]: IIC Read Failed\r\n", pm[i].i2cAddress);
return XST_FAILURE;
}
pm[i].current = (ReadBuffer[1] << 8) + ReadBuffer[0];
// xil_printf("Current: 0x%x 0x%x V\r\n", ReadBuffer[0], ReadBuffer[1]);
// xil_printf("Current: 0x%x, %d V\r\n", pm[i].current, pm[i].current);
decimal = pm[i].current >> 13;
small = (pm[i].current - (decimal <<13)) * 1000 / (1<<13);
xil_printf("\tCurrent: %d.%d A\r\n", decimal, small);
/*
* Read Voltage
*/
Status = IicReadData(pm[i].i2cAddress, PM_CMD_POUT, ReadBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("PMBus[%x]: IIC Read Failed\r\n", pm[i].i2cAddress);
return XST_FAILURE;
}
pm[i].power = (ReadBuffer[1] << 8) + ReadBuffer[0];
// xil_printf("Power: 0x%x 0x%x V\r\n", ReadBuffer[0], ReadBuffer[1]);
// xil_printf("Power: 0x%x, %d V\r\n", pm[i].power, pm[i].power);
decimal = pm[i].power >> 13;
small = (pm[i].power - (decimal <<13)) * 1000 / (1<<13);
xil_printf("\tPower: %d.%d W\r\n", decimal, small);
}
return XST_SUCCESS;
}

220
netfpga/minip4/simple_sume_switch/sw/embedded/src/iic_si5324.c Normal file
View file

@ -0,0 +1,220 @@
/*
* Copyright (c) 2015 Digilent Inc.
* Copyright (c) 2015 Tinghui Wang (Steve)
* All rights reserved.
*
* File:
* sw/embedded/src/iic_si5324.c
*
* Project:
* Reference project
*
* Author:
* Tinghui Wang (Steve)
*
* Description:
* IIC configuration to generate 156.25MHz clocks from SI5324
*
* @NETFPGA_LICENSE_HEADER_START@
*
* Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. NetFPGA licenses this
* file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.netfpga-cic.org
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* @NETFPGA_LICENSE_HEADER_END@
*
*/
#include "iic_config.h"
#include "xstatus.h"
#include <stdio.h>
/*
* Read register data from SI5324
*/
int read5324()
{
u32 Index;
int Status;
u8 reg_addr;
u8 ReadBuffer[20];
/*
* Read from Si5324
* Addr, Bit Field Description
* 25, N1_HS
* 31, NC1_LS
* 40, N2_HS
* 40, N2_LS
* 43, N31
*/
// for( delay = 0; delay < MAX_DELAY_COUNT; delay++);
reg_addr = 25; //N1_HS
Status = IicReadData2(IIC_SI5324_ADDRESS, reg_addr, ReadBuffer, 1);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Read Failed.\r\n");
return XST_FAILURE;
}
xil_printf("\r\n");
for (Index = 0; Index < 1; Index++) {
xil_printf("Reg %d: N1_HS = 0x%02X\r\n", reg_addr, ReadBuffer[0]);
}
reg_addr = 31; //NC1_LS
Status = IicReadData2(IIC_SI5324_ADDRESS, reg_addr, ReadBuffer, 3);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Read Failed.\r\n");
return XST_FAILURE;
}
xil_printf("\r\n");
for (Index = 0; Index < 3; Index++) {
xil_printf("Reg %d: NC1_LS = 0x%02X\r\n", reg_addr++, ReadBuffer[Index]);
}
reg_addr = 40; //N2_HS, N2_LS
Status = IicReadData2(IIC_SI5324_ADDRESS, reg_addr, ReadBuffer, 3);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Read Failed.\r\n");
return XST_FAILURE;
}
xil_printf("\r\n");
for (Index = 0; Index < 3; Index++) {
xil_printf("Reg %d: N2_HS_LS = 0x%02X\r\n",reg_addr++, ReadBuffer[Index]);
}
reg_addr = 43; //N31
Status = IicReadData2(IIC_SI5324_ADDRESS, reg_addr, ReadBuffer, 3);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Read Failed.\r\n");
return XST_FAILURE;
}
xil_printf("\r\n");
for (Index = 0; Index < 3; Index++) {
xil_printf("Reg %d: N31 = 0x%02X\r\n", reg_addr++, ReadBuffer[Index]);
}
return XST_SUCCESS;
}
/*
* Configure SI5324 to generate 156.25MHz
*/
int config_SI5324() {
int Status;
u8 WriteBuffer[10];
/*
* Write to the IIC Switch.
*/
WriteBuffer[0] = IIC_BUS_DDR3; //Select Bus7 - Si5326
Status = IicWriteData(IIC_SWITCH_ADDRESS, WriteBuffer, 1);
if (Status != XST_SUCCESS) {
xil_printf("PCA9548 FAILED to select Si5324 IIC Bus\r\n");
return XST_FAILURE;
}
// Set Reg 0, 1, 2, 3, 4
WriteBuffer[0] = 0;
WriteBuffer[1] = 0x54; // Reg 0: Free run, Clock always on, No Bypass (Normal Op)
WriteBuffer[2] = 0xE4; // Reg 1: CLKIN2 is second priority
WriteBuffer[3] = 0x12; // Reg 2: BWSEL set to 1
WriteBuffer[4] = 0x15; // Reg 3: CKIN1 selected, No Digital Hold, Output clocks disabled during ICAL
WriteBuffer[5] = 0x92; // Reg 4: Automatic Revertive, HIST_DEL = 0x12
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 6);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 0-4 FAILED\r\n");
return XST_FAILURE;
}
// Set Reg 10, 11
WriteBuffer[0] = 10;
WriteBuffer[1] = 0x08; // Reg 10: CKOUT2 disabled, CKOUT1 enabled
WriteBuffer[2] = 0x40; // Reg 11: CKIN1, CKIN2 enabled
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 3);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 10/11 FAILED\r\n");
return XST_FAILURE;
}
// Write Reg 25 to set N1_HS = 9
WriteBuffer[0] = 25;
WriteBuffer[1] = 0xA0;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 25 FAILED\r\n");
return XST_FAILURE;
}
// Write Regs 31,32,33 to set NC1_LS = 4
WriteBuffer[0] = 31;
WriteBuffer[1] = 0x00;
WriteBuffer[2] = 0x00;
WriteBuffer[3] = 0x03;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 4);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 31-33 FAILED\r\n");
return XST_FAILURE;
}
// Write Regs 40,41,42 to set N2_HS = 10, N2_LS = 150000
WriteBuffer[0] = 40;
WriteBuffer[1] = 0xC2;
WriteBuffer[2] = 0x49;
WriteBuffer[3] = 0xEF;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 4);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 40-42 FAILED\r\n");
return XST_FAILURE;
}
// Write Regs 43,44,45 to set N31 = 30475
WriteBuffer[0] = 43;
WriteBuffer[1] = 0x00;
WriteBuffer[2] = 0x77;
WriteBuffer[3] = 0x0B;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 4);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 43-45 FAILED\r\n");
return XST_FAILURE;
}
// Write Regs 46,47,48 to set N32 = 30475
WriteBuffer[0] = 46;
WriteBuffer[1] = 0x00;
WriteBuffer[2] = 0x77;
WriteBuffer[3] = 0x0B;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 4);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 46-48 FAILED\r\n");
return XST_FAILURE;
}
// Read Si5324 regs after update
#ifdef SI5324_DEBUG
read5324();
#endif
// Start Si5324 Internal Calibration process
// Write Reg 136 to set ICAL = 1
WriteBuffer[0] = 136;
WriteBuffer[1] = 0x40;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 136 FAILED\r\n");
return XST_FAILURE;
}
return XST_SUCCESS;
}

678
netfpga/minip4/simple_sume_switch/sw/embedded/src/sume_register_defines.h Normal file
View file

@ -0,0 +1,678 @@
//-
// Copyright (c) 2015 University of Cambridge
// All rights reserved.
//
// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
// under National Science Foundation under Grant No. CNS-0855268,
// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
// as part of the DARPA MRC research programme.
//
// @NETFPGA_LICENSE_HEADER_START@
//
// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. NetFPGA licenses this
// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.netfpga-cic.org
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @NETFPGA_LICENSE_HEADER_END@
/////////////////////////////////////////////////////////////////////////////////
// This is an automatically generated header definitions file
/////////////////////////////////////////////////////////////////////////////////
//######################################################
//# Definitions for MICROBLAZE_AXI_IIC
//######################################################
#define SUME_MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
#define SUME_MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
#define SUME_MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_UARTLITE
//######################################################
#define SUME_MICROBLAZE_UARTLITE_BASEADDR 0x40600000
#define SUME_MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
#define SUME_MICROBLAZE_UARTLITE_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_DLMB_BRAM
//######################################################
#define SUME_MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
#define SUME_MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
#define SUME_MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_ILMB_BRAM
//######################################################
#define SUME_MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
#define SUME_MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
#define SUME_MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_AXI_INTC
//######################################################
#define SUME_MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
#define SUME_MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
#define SUME_MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
//######################################################
//# Definitions for INPUT_ARBITER
//######################################################
#define SUME_INPUT_ARBITER_BASEADDR 0x44010000
#define SUME_INPUT_ARBITER_HIGHADDR 0x44010FFF
#define SUME_INPUT_ARBITER_SIZEADDR 0x1000
#define SUME_INPUT_ARBITER_0_ID_OFFSET 0x0
#define SUME_INPUT_ARBITER_0_ID_DEFAULT 0x0000DA01
#define SUME_INPUT_ARBITER_0_ID_WIDTH 32
#define SUME_INPUT_ARBITER_0_VERSION_OFFSET 0x4
#define SUME_INPUT_ARBITER_0_VERSION_DEFAULT 0x1
#define SUME_INPUT_ARBITER_0_VERSION_WIDTH 32
#define SUME_INPUT_ARBITER_0_RESET_OFFSET 0x8
#define SUME_INPUT_ARBITER_0_RESET_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_RESET_WIDTH 16
#define SUME_INPUT_ARBITER_0_FLIP_OFFSET 0xC
#define SUME_INPUT_ARBITER_0_FLIP_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_FLIP_WIDTH 32
#define SUME_INPUT_ARBITER_0_DEBUG_OFFSET 0x10
#define SUME_INPUT_ARBITER_0_DEBUG_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_DEBUG_WIDTH 32
#define SUME_INPUT_ARBITER_0_PKTIN_OFFSET 0x14
#define SUME_INPUT_ARBITER_0_PKTIN_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_PKTIN_WIDTH 32
#define SUME_INPUT_ARBITER_0_PKTOUT_OFFSET 0x18
#define SUME_INPUT_ARBITER_0_PKTOUT_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_PKTOUT_WIDTH 32
//######################################################
//# Definitions for OUTPUT_QUEUES
//######################################################
#define SUME_OUTPUT_QUEUES_BASEADDR 0x44030000
#define SUME_OUTPUT_QUEUES_HIGHADDR 0x44030FFF
#define SUME_OUTPUT_QUEUES_SIZEADDR 0x1000
#define SUME_OUTPUT_QUEUES_0_ID_OFFSET 0x0
#define SUME_OUTPUT_QUEUES_0_ID_DEFAULT 0x0000DA03
#define SUME_OUTPUT_QUEUES_0_ID_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_VERSION_OFFSET 0x4
#define SUME_OUTPUT_QUEUES_0_VERSION_DEFAULT 0x1
#define SUME_OUTPUT_QUEUES_0_VERSION_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_RESET_OFFSET 0x8
#define SUME_OUTPUT_QUEUES_0_RESET_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_RESET_WIDTH 16
#define SUME_OUTPUT_QUEUES_0_FLIP_OFFSET 0xC
#define SUME_OUTPUT_QUEUES_0_FLIP_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_FLIP_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_DEBUG_OFFSET 0x10
#define SUME_OUTPUT_QUEUES_0_DEBUG_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_DEBUG_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTIN_OFFSET 0x14
#define SUME_OUTPUT_QUEUES_0_PKTIN_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTIN_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTOUT_OFFSET 0x18
#define SUME_OUTPUT_QUEUES_0_PKTOUT_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTOUT_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_OFFSET 0x1C
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_OFFSET 0x20
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_OFFSET 0x24
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_OFFSET 0x28
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_OFFSET 0x2C
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_OFFSET 0x30
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_OFFSET 0x34
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_OFFSET 0x38
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_OFFSET 0x3C
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_OFFSET 0x40
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_OFFSET 0x44
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_OFFSET 0x48
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_OFFSET 0x4C
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_OFFSET 0x50
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_OFFSET 0x54
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_OFFSET 0x58
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_OFFSET 0x5C
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_OFFSET 0x60
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_OFFSET 0x64
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_OFFSET 0x68
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_OFFSET 0x6C
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_OFFSET 0x70
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_OFFSET 0x74
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_OFFSET 0x78
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_OFFSET 0x7C
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_OFFSET 0x80
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_OFFSET 0x84
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_OFFSET 0x88
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_OFFSET 0x8C
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_OFFSET 0x90
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_OFFSET 0x94
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_OFFSET 0x98
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_OFFSET 0x9C
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_OFFSET 0xA0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_OFFSET 0xA4
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_WIDTH 32
//######################################################
//# Definitions for OUTPUT_PORT_LOOKUP
//######################################################
#define SUME_OUTPUT_PORT_LOOKUP_BASEADDR 0x44020000
#define SUME_OUTPUT_PORT_LOOKUP_HIGHADDR 0x44020FFF
#define SUME_OUTPUT_PORT_LOOKUP_SIZEADDR 0x1000
#define SUME_OUTPUT_PORT_LOOKUP_0_ID_OFFSET 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_ID_DEFAULT 0x0001DA02
#define SUME_OUTPUT_PORT_LOOKUP_0_ID_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_OFFSET 0x4
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_DEFAULT 0x1
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_OFFSET 0x8
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_WIDTH 16
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_OFFSET 0xC
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_OFFSET 0x10
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_OFFSET 0x14
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_OFFSET 0x18
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_OFFSET 0x1C
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_OFFSET 0x20
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE0
//######################################################
#define SUME_NF_10G_INTERFACE0_BASEADDR 0x44040000
#define SUME_NF_10G_INTERFACE0_HIGHADDR 0x44040FFF
#define SUME_NF_10G_INTERFACE0_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_SHARED_0_ID_OFFSET 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_SHARED_0_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_OFFSET 0x4
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_OFFSET 0x8
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_OFFSET 0xC
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_OFFSET 0x10
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_OFFSET 0x14
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_OFFSET 0x18
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_OFFSET 0x1C
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_OFFSET 0x20
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_OFFSET 0x24
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_OFFSET 0x28
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_OFFSET 0x2C
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_OFFSET 0x30
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_OFFSET 0x34
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_OFFSET 0x38
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_OFFSET 0x3C
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_OFFSET 0x40
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_OFFSET 0x44
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_OFFSET 0x48
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_OFFSET 0x4C
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_OFFSET 0x50
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_OFFSET 0x54
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_OFFSET 0x58
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_OFFSET 0x5C
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE1
//######################################################
#define SUME_NF_10G_INTERFACE1_BASEADDR 0x44050000
#define SUME_NF_10G_INTERFACE1_HIGHADDR 0x44050FFF
#define SUME_NF_10G_INTERFACE1_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_1_ID_OFFSET 0x0
#define SUME_NF_10G_INTERFACE_1_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_1_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_VERSION_OFFSET 0x4
#define SUME_NF_10G_INTERFACE_1_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_1_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_RESET_OFFSET 0x8
#define SUME_NF_10G_INTERFACE_1_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_1_FLIP_OFFSET 0xC
#define SUME_NF_10G_INTERFACE_1_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_DEBUG_OFFSET 0x10
#define SUME_NF_10G_INTERFACE_1_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_INTERFACEID_OFFSET 0x14
#define SUME_NF_10G_INTERFACE_1_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PKTIN_OFFSET 0x18
#define SUME_NF_10G_INTERFACE_1_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PKTOUT_OFFSET 0x1C
#define SUME_NF_10G_INTERFACE_1_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_OFFSET 0x20
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_OFFSET 0x24
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_OFFSET 0x28
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_OFFSET 0x2C
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_OFFSET 0x30
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_OFFSET 0x34
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_OFFSET 0x38
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_OFFSET 0x3C
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_OFFSET 0x40
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_OFFSET 0x44
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_OFFSET 0x48
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_OFFSET 0x4C
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_OFFSET 0x50
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_OFFSET 0x54
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_OFFSET 0x58
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_OFFSET 0x5C
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE2
//######################################################
#define SUME_NF_10G_INTERFACE2_BASEADDR 0x44060000
#define SUME_NF_10G_INTERFACE2_HIGHADDR 0x44060FFF
#define SUME_NF_10G_INTERFACE2_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_2_ID_OFFSET 0x0
#define SUME_NF_10G_INTERFACE_2_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_2_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_VERSION_OFFSET 0x4
#define SUME_NF_10G_INTERFACE_2_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_2_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_RESET_OFFSET 0x8
#define SUME_NF_10G_INTERFACE_2_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_2_FLIP_OFFSET 0xC
#define SUME_NF_10G_INTERFACE_2_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_DEBUG_OFFSET 0x10
#define SUME_NF_10G_INTERFACE_2_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_INTERFACEID_OFFSET 0x14
#define SUME_NF_10G_INTERFACE_2_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PKTIN_OFFSET 0x18
#define SUME_NF_10G_INTERFACE_2_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PKTOUT_OFFSET 0x1C
#define SUME_NF_10G_INTERFACE_2_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_OFFSET 0x20
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_OFFSET 0x24
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_OFFSET 0x28
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_OFFSET 0x2C
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_OFFSET 0x30
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_OFFSET 0x34
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_OFFSET 0x38
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_OFFSET 0x3C
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_OFFSET 0x40
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_OFFSET 0x44
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_OFFSET 0x48
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_OFFSET 0x4C
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_OFFSET 0x50
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_OFFSET 0x54
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_OFFSET 0x58
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_OFFSET 0x5C
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE3
//######################################################
#define SUME_NF_10G_INTERFACE3_BASEADDR 0x44070000
#define SUME_NF_10G_INTERFACE3_HIGHADDR 0x44070FFF
#define SUME_NF_10G_INTERFACE3_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_3_ID_OFFSET 0x0
#define SUME_NF_10G_INTERFACE_3_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_3_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_VERSION_OFFSET 0x4
#define SUME_NF_10G_INTERFACE_3_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_3_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_RESET_OFFSET 0x8
#define SUME_NF_10G_INTERFACE_3_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_3_FLIP_OFFSET 0xC
#define SUME_NF_10G_INTERFACE_3_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_DEBUG_OFFSET 0x10
#define SUME_NF_10G_INTERFACE_3_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_OFFSET 0x14
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PKTIN_OFFSET 0x18
#define SUME_NF_10G_INTERFACE_3_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PKTOUT_OFFSET 0x1C
#define SUME_NF_10G_INTERFACE_3_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_OFFSET 0x20
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_OFFSET 0x24
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_OFFSET 0x28
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_OFFSET 0x2C
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_OFFSET 0x30
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_OFFSET 0x34
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_OFFSET 0x38
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_OFFSET 0x3C
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_OFFSET 0x40
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_OFFSET 0x44
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_OFFSET 0x48
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_OFFSET 0x4C
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_OFFSET 0x50
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_OFFSET 0x54
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_OFFSET 0x58
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_OFFSET 0x5C
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_RIFFA_DMA
//######################################################
#define SUME_NF_RIFFA_DMA_BASEADDR 0x44080000
#define SUME_NF_RIFFA_DMA_HIGHADDR 0x44080FFF
#define SUME_NF_RIFFA_DMA_SIZEADDR 0x1000
#define SUME_NF_RIFFA_DMA_0_ID_OFFSET 0x0
#define SUME_NF_RIFFA_DMA_0_ID_DEFAULT 0x00001FFA
#define SUME_NF_RIFFA_DMA_0_ID_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_VERSION_OFFSET 0x4
#define SUME_NF_RIFFA_DMA_0_VERSION_DEFAULT 0x1
#define SUME_NF_RIFFA_DMA_0_VERSION_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RESET_OFFSET 0x8
#define SUME_NF_RIFFA_DMA_0_RESET_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RESET_WIDTH 16
#define SUME_NF_RIFFA_DMA_0_FLIP_OFFSET 0xC
#define SUME_NF_RIFFA_DMA_0_FLIP_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_FLIP_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_DEBUG_OFFSET 0x10
#define SUME_NF_RIFFA_DMA_0_DEBUG_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_DEBUG_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RQPKT_OFFSET 0x14
#define SUME_NF_RIFFA_DMA_0_RQPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RQPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RCPKT_OFFSET 0x18
#define SUME_NF_RIFFA_DMA_0_RCPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RCPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_CQPKT_OFFSET 0x1C
#define SUME_NF_RIFFA_DMA_0_CQPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_CQPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_CCPKT_OFFSET 0x20
#define SUME_NF_RIFFA_DMA_0_CCPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_CCPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_XGETXPKT_OFFSET 0x24
#define SUME_NF_RIFFA_DMA_0_XGETXPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_XGETXPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_XGERXPKT_OFFSET 0x28
#define SUME_NF_RIFFA_DMA_0_XGERXPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_XGERXPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIERQ_OFFSET 0x2C
#define SUME_NF_RIFFA_DMA_0_PCIERQ_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIERQ_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_OFFSET 0x30
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_OFFSET 0x34
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_OFFSET 0x38
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEERROR_OFFSET 0x3C
#define SUME_NF_RIFFA_DMA_0_PCIEERROR_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEERROR_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_OFFSET 0x40
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIETPH_OFFSET 0x44
#define SUME_NF_RIFFA_DMA_0_PCIETPH_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIETPH_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC1_OFFSET 0x48
#define SUME_NF_RIFFA_DMA_0_PCIEFC1_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC1_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC2_OFFSET 0x4C
#define SUME_NF_RIFFA_DMA_0_PCIEFC2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_OFFSET 0x50
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_OFFSET 0x54
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_OFFSET 0x58
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_OFFSET 0x5C
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_OFFSET 0x60
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_OFFSET 0x64
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_OFFSET 0x68
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_WIDTH 32

41
netfpga/minip4/simple_sume_switch/sw/embedded/tcl/download.tcl Normal file
View file

@ -0,0 +1,41 @@
#
# Copyright (c) 2015 Digilent Inc.
# Copyright (c) 2015 Tinghui Wang (Steve)
# All rights reserved.
#
# File:
# download.tcl
#
# Project:
# acceptance_test
#
# Author:
# Tinghui Wang (Steve)
#
# Description:
# Downloads the acceptance test elf
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
fpga -f [lindex $argv 0]
connect mb mdm
dow SDK_Workspace/project/Debug/project.elf
run

37
netfpga/minip4/simple_sume_switch/sw/embedded/tcl/simple_sume_switch_xsdk.tcl Normal file
View file

@ -0,0 +1,37 @@
#
# Copyright (c) 2017 University of Cambridge
# Copyright (c) 2017 Salvator Galea
# All rights reserved.
#
# This software was developed by University of Cambridge Computer Laboratory
# under the ENDEAVOUR project (grant agreement 644960) as part of
# the European Union's Horizon 2020 research and innovation programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA Open Systems C.I.C. (NetFPGA) under one or more
# contributor license agreements. See the NOTICE file distributed with this
# work for additional information regarding copyright ownership. NetFPGA
# licenses this file to you under the NetFPGA Hardware-Software License,
# Version 1.0 (the License); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
set ws "SDK_Workspace"
set design $::env(NF_PROJECT_NAME)
setws ./$ws/$design
createhw -name hw_platform -hwspec ./$design.hdf
createbsp -name bsp -hwproject hw_platform -proc control_sub_i_nf_mbsys_mbsys_microblaze_0 -os standalone
createapp -name app -hwproject hw_platform -proc control_sub_i_nf_mbsys_mbsys_microblaze_0 -os standalone -lang C -app {Hello World} -bsp bsp
#importsources -name app -path ./src/
projects -build
exit

43
netfpga/minip4/simple_sume_switch/sw/embedded/xml/SDKproj.xml Normal file
View file

@ -0,0 +1,43 @@
<!--
# Copyright (c) 2015 Digilent Inc.
# Copyright (c) 2015 Tinghui Wang (Steve)
# All rights reserved.
#
# File:
# SDKproj.xml
#
# Project:
# reference project
#
# Author:
# Tinghui Wang (Steve)
#
# Description:
# compiles a project
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
-->
<project name="SDK Script" default="main">
<target name="main">
<createHwProject projname="hw_platform_0" hwspecpath="hw/control_sub.xml" />
<createAppProject projname="simple_sume_switch" hwprojname="hw_platform_0" processor="nf_mbsys_mbsys_microblaze_0" bspprojname="bsp" os="standalone" template="Hello World" language="C" />
</target>
</project>