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Signed-off-by: Nico Schottelius <nico@nico-notebook.schottelius.org>
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Nico Schottelius
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#
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# Copyright (c) 2017 Stephen Ibanez
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# All rights reserved.
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#
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# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
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# under National Science Foundation under Grant No. CNS-0855268,
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# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
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# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
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# as part of the DARPA MRC research programme.
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#
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# @NETFPGA_LICENSE_HEADER_START@
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#
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# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
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# license agreements. See the NOTICE file distributed with this work for
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# additional information regarding copyright ownership. NetFPGA licenses this
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# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at:
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#
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# http://www.netfpga-cic.org
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#
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# Unless required by applicable law or agreed to in writing, Work distributed
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# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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# CONDITIONS OF ANY KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations under the License.
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#
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# @NETFPGA_LICENSE_HEADER_END@
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#
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# Makefile to set up the simulation environment with the test data
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SDNET_BASE_ADDR=0x44020000
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all: clean
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cp ${P4_PROJECT_DIR}/testdata/config_writes.py ./
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clean:
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rm -f config_writes.py*
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rm -f *.pyc
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192
netfpga/minip4/simple_sume_switch/test/sim_switch_ctrlWrites/run.py
Executable file
192
netfpga/minip4/simple_sume_switch/test/sim_switch_ctrlWrites/run.py
Executable file
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#!/usr/bin/env python
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#
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# Copyright (c) 2015 University of Cambridge
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# Copyright (c) 2015 Neelakandan Manihatty Bojan, Georgina Kalogeridou
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# All rights reserved.
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#
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# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
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# under National Science Foundation under Grant No. CNS-0855268,
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# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
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# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
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# as part of the DARPA MRC research programme.
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#
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# @NETFPGA_LICENSE_HEADER_START@
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#
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# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
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# license agreements. See the NOTICE file distributed with this work for
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# additional information regarding copyright ownership. NetFPGA licenses this
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# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at:
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#
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# http://www.netfpga-cic.org
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#
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# Unless required by applicable law or agreed to in writing, Work distributed
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# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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# CONDITIONS OF ANY KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations under the License.
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#
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# @NETFPGA_LICENSE_HEADER_END@
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#
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# Author:
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# Modified by Neelakandan Manihatty Bojan, Georgina Kalogeridou
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import logging
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logging.getLogger("scapy.runtime").setLevel(logging.ERROR)
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from NFTest import *
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import sys, os, random, json
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from nf_sim_tools import *
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from collections import OrderedDict
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import config_writes
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sys.path.append(os.path.expandvars('$P4_PROJECT_DIR/testdata/'))
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from switch_calc_headers import *
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# read the externs defined in the P4 program
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EXTERN_DEFINES_FILE = os.path.expandvars('$P4_PROJECT_DIR/testdata/SimpleSumeSwitch_extern_defines.json')
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with open(EXTERN_DEFINES_FILE) as f:
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p4_externs = json.load(f)
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phy2loop0 = ('../connections/conn', [])
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nftest_init(sim_loop = [], hw_config = [phy2loop0])
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print "About to start the test"
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nftest_start()
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def schedule_pkts(pkt_list, iface):
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for pkt in pkt_list:
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pkt.time = baseTime + delta*pkt.time
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pkt.tuser_sport = nf_port_map[iface]
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# configure the tables in the P4_SWITCH
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nftest_regwrite(0x440200f0, 0x00000001)
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nftest_regwrite(0x440200f0, 0x00000001)
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nftest_regwrite(0x440200f0, 0x00000001)
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nftest_regwrite(0x440200f0, 0x00000001)
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nftest_regwrite(0x440200f0, 0x00000001)
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config_writes.config_tables()
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# send packets after the configuration writes have finished
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#baseTime = 1044e-9 + (232e-9)*config_writes.NUM_WRITES #120e-6
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baseTime = 20e-6
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delta = 1e-6 #1e-8
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###########
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# pkt generation tools
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###########
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# Pkt lists for SUME simulations
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nf_applied = OrderedDict()
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nf_applied[0] = []
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nf_applied[1] = []
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nf_applied[2] = []
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nf_applied[3] = []
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nf_expected = OrderedDict()
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nf_expected[0] = []
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nf_expected[1] = []
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nf_expected[2] = []
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nf_expected[3] = []
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nf_port_map = {"nf0":0b00000001, "nf1":0b00000100, "nf2":0b00010000, "nf3":0b01000000, "dma0":0b00000010}
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nf_id_map = {"nf0":0, "nf1":1, "nf2":2, "nf3":3}
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def applyPkt(pkt, ingress, time):
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pkt.time = time
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nf_applied[nf_id_map[ingress]].append(pkt)
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def expPkt(pkt, egress):
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if egress in ["nf0","nf1","nf2","nf3"]:
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nf_expected[nf_id_map[egress]].append(pkt)
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elif egress == "bcast":
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nf_expected[0].append(pkt)
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nf_expected[1].append(pkt)
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nf_expected[2].append(pkt)
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nf_expected[3].append(pkt)
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#####################
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# generate testdata #
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#####################
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MAC1 = "08:11:11:11:11:08"
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MAC2 = "08:22:22:22:22:08"
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pktCnt = 0
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INDEX_WIDTH = 4
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REG_DEPTH = 2**INDEX_WIDTH
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NUM_KEYS = 4
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lookup_table = {1: 0x00000001, 2: 0x00000010, 3: 0x00000100, 4: 0x00001000}
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CONST_REG = {}
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for i in range(REG_DEPTH):
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CONST_REG[i] = i
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# write the const register entires
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for i in range(REG_DEPTH):
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nftest_regwrite(p4_externs['const']['base_addr'] + i, CONST_REG[i])
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def test_reg_add(index, val):
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global pktCnt
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pkt = Ether(dst=MAC2, src=MAC1) / Calc(op1=index, opCode=ADD_REG_OP, op2=val, result=0)
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pkt = pad_pkt(pkt, 64)
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applyPkt(pkt, 'nf0', pktCnt)
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pktCnt += 1
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pkt = Ether(dst=MAC1, src=MAC2) / Calc(op1=index, opCode=ADD_REG_OP, op2=val, result=CONST_REG[index] + val)
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pkt = pad_pkt(pkt, 64)
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expPkt(pkt, 'nf0')
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def test_reg_set(index, val):
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global pktCnt
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# test set reg
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pkt = Ether(dst=MAC2, src=MAC1) / Calc(op1=index, opCode=SET_REG_OP, op2=val, result=0)
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pkt = pad_pkt(pkt, 64)
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applyPkt(pkt, 'nf0', pktCnt)
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pktCnt += 1
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pkt = Ether(dst=MAC1, src=MAC2) / Calc(op1=index, opCode=SET_REG_OP, op2=val, result=0)
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pkt = pad_pkt(pkt, 64)
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expPkt(pkt, 'nf0')
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# generate the test data
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for i in range(5):
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index = random.randint(0,REG_DEPTH-1)
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val = random.randint(0,2**31)
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test_reg_add(index, val)
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for i in range(5):
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index = random.randint(0,REG_DEPTH-1)
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val = random.randint(0,2**31)
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test_reg_set(index, val)
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CONST_REG[index] = val
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schedule_pkts(nf_applied[0], 'nf0')
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schedule_pkts(nf_applied[1], 'nf1')
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schedule_pkts(nf_applied[2], 'nf2')
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schedule_pkts(nf_applied[3], 'nf3')
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# Apply and check the packets
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nftest_send_phy('nf0', nf_applied[0])
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nftest_send_phy('nf1', nf_applied[1])
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nftest_send_phy('nf2', nf_applied[2])
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nftest_send_phy('nf3', nf_applied[3])
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nftest_expect_phy('nf0', nf_expected[0])
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nftest_expect_phy('nf1', nf_expected[1])
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nftest_expect_phy('nf2', nf_expected[2])
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nftest_expect_phy('nf3', nf_expected[3])
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nftest_barrier()
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# check to make sure the register entries were set correctly by the data-plane
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for i in range(REG_DEPTH):
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nftest_regread_expect(p4_externs['const']['base_addr'] + i, CONST_REG[i])
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nftest_barrier()
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mres=[]
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nftest_finish(mres)
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