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Re-organising

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Nico Schottelius 2019-07-28 16:27:53 +02:00
parent c3068206af
commit 58d7d91358
12 changed files with 257 additions and 43 deletions
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0
netpfga/bind-mount.sh → bin/bind-mount.sh
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0
netpfga/bind-umount.sh → bin/bind-umount.sh
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0
netpfga/build-load-drivers.sh → bin/build-load-drivers.sh
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0
netpfga/delete_ipv6_neighbor.sh → bin/delete_ipv6_neighbor.sh
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netpfga/delete_table_entries.sh → bin/delete_table_entries.sh
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0
netpfga/do-all-steps.sh → bin/do-all-steps.sh
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9
bin/gen_v4_table_test_entries.py Normal file
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@ -0,0 +1,9 @@
#!/usr/bin/env python3
import ipaddress
for i in range(1,65):
addr = ipaddress.IPv4Address("10.0.0.{}".format(i))
ip_int = int(addr)
print("table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port {} => 1 {} {} 0 0".format(ip_int, i, i))

0
netpfga/ping_ipv6_addresses.sh → bin/ping_ipv6_addresses.sh
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243
doc/plan.org
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@ -7277,11 +7277,11 @@ nf_port_map = {
"dma0":0b00000010 "dma0":0b00000010
} }
| port 0 | 1 | likely: esprimo enp2s0f0 | | | port 0 | 1 | eth1@ nsg ?! likely: esprimo enp2s0f0 | |
| port 1 | 4 | likely: esprimo enp2s0f1 | | | port 1 | 4 | likely: esprimo enp2s0f1 | |
| port 2 | 16 | not connected likely | | | port 2 | 16 | not connected likely | |
| port 3 | 64 | eth1 @ nsg | PROBALY NOT, probably 1! | | port 3 | 64 | eth1 @ nsg | PROBALY NOT, probably 1! |
| | | | | | | | | |
*** DONE 2019-07-28: testing with port = 64 (first or last in theory): LAST! WORKS! *** DONE 2019-07-28: testing with port = 64 (first or last in theory): LAST! WORKS!
CLOSED: [2019-07-28 Sun 13:19] CLOSED: [2019-07-28 Sun 13:19]
@ -7333,7 +7333,8 @@ nico@ESPRIMO-P956:~/master-thesis/netpfga$ sudo ip -6 neighbor add 2001:db8:42:
#+END_CENTER #+END_CENTER
*** TODO 2019-07-28: try setting correct out port for 42: seems all go to port3 *** DONE 2019-07-28: try setting correct out port for 42: seems all go to port3 (or 1?)
CLOSED: [2019-07-28 Sun 15:17]
- solution: lookup table still in place!!!! - solution: lookup table still in place!!!!
#+BEGIN_CENTER #+BEGIN_CENTER
@ -7382,6 +7383,236 @@ READ 0x44020144 = 0x0001
success success
>> >>
#+END_CENTER
*** TODO 2019-07-28: test with 6.8: very bare / only v4/v6 egress
- Expected: 1 -> nsg, 16 -> enp2s0f0, 64 -> enp2s0f1
- Actual@ no packet seen
#+BEGIN_CENTER
nico@ESPRIMO-P956:~$ sudo tcpdump -lni enp2s0f1
tcpdump: verbose output suppressed, use -v or -vv for full protocol decode
listening on enp2s0f1, link-type EN10MB (Ethernet), capture size 262144 bytes
15:19:36.015934 IP6 2001:db8:42::42 > 2001:db8:42::1: ICMP6, echo request, seq 1, length 64
15:20:11.989340 IP6 2001:db8:42::42 > 2001:db8:42::4: ICMP6, echo request, seq 1, length 64
15:20:25.279826 IP6 2001:db8:42::42 > 2001:db8:42::16: ICMP6, echo request, seq 1, length 64
15:20:48.624911 IP6 2001:db8:42::42 > 2001:db8:42::64: ICMP6, echo request, seq 1, length 64
^C
4 packets captured
4 packets received by filter
0 packets dropped by kernel
nico@ESPRIMO-P956:~$
#+END_CENTER
*** TODO 2019-07-28: test ipv4 with 6.8
#+BEGIN_CENTER
nico@ESPRIMO-P956:~/master-thesis/netpfga$ sudo ip neigh del 10.0.0.1 dev enp2s0f0
nico@ESPRIMO-P956:~/master-thesis/netpfga$ sudo ip neigh add 10.0.0.1 dev enp2s0f0 lladdr f8:f2:1e:41:44:9c
nico@ESPRIMO-P956:~/master-thesis/netpfga$
>> table_cam_delete_entry realmain_v4_networks_0 167772161
#+END_CENTER
#+BEGIN_CENTER
>> table_cam_delete_entry realmain_v4_networks_0 167772161
CAM_Init_ValidateContext() - done
WROTE 0x44020050 = 0xa000001
READ 0x44020044 = 0x0001
WROTE 0x44020040 = 0x0002
READ 0x44020044 = 0x0001
READ 0x44020044 = 0x0001
success
>> table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772161 => 1 1 1 0 0
fields = [(u'hit', 1), (u'action_run', 3), (u'out_port', 8), (u'out_port', 8), (u'mac_addr', 48), (u'task', 16), (u'table_id', 16)]
action_name = TopPipe.realmain.set_egress_port
field_vals = [1, '1', '1', '1', '0', '0']
CAM_Init_ValidateContext() - done
WROTE 0x44020050 = 0xa000001
WROTE 0x44020080 = 0x0000
WROTE 0x44020084 = 0x0001
WROTE 0x44020088 = 0x1010000
WROTE 0x4402008c = 0x0001
READ 0x44020044 = 0x0001
WROTE 0x44020040 = 0x0001
READ 0x44020044 = 0x0001
READ 0x44020044 = 0x0001
success
>>
>> table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 10.0.0.1 => 1 1 1 0 0
fields = [(u'hit', 1), (u'action_run', 3), (u'out_port', 8), (u'out_port', 8), (u'mac_addr', 48), (u'task', 16), (u'table_id', 16)]
action_name = TopPipe.realmain.set_egress_port
field_vals = [1, '1', '1', '1', '0', '0']
CAM_Init_ValidateContext() - done
WROTE 0x44020050 = 0xa000001
WROTE 0x44020080 = 0x0000
WROTE 0x44020084 = 0x0001
WROTE 0x44020088 = 0x1010000
WROTE 0x4402008c = 0x0001
READ 0x44020044 = 0x0001
WROTE 0x44020040 = 0x0001
READ 0x44020044 = 0x0001
READ 0x44020044 = 0x0001
success
#+END_CENTER
*** 2019-07-28: trying all ports with ipv4
#+BEGIN_CENTER
[16:26] line:bin% python3 gen_v4_table_test_entries.py
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772161 => 1 1 1 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772162 => 1 2 2 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772163 => 1 3 3 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772164 => 1 4 4 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772165 => 1 5 5 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772166 => 1 6 6 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772167 => 1 7 7 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772168 => 1 8 8 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772169 => 1 9 9 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772170 => 1 10 10 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772171 => 1 11 11 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772172 => 1 12 12 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772173 => 1 13 13 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772174 => 1 14 14 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772175 => 1 15 15 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772176 => 1 16 16 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772177 => 1 17 17 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772178 => 1 18 18 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772179 => 1 19 19 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772180 => 1 20 20 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772181 => 1 21 21 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772182 => 1 22 22 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772183 => 1 23 23 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772184 => 1 24 24 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772185 => 1 25 25 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772186 => 1 26 26 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772187 => 1 27 27 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772188 => 1 28 28 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772189 => 1 29 29 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772190 => 1 30 30 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772191 => 1 31 31 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772192 => 1 32 32 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772193 => 1 33 33 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772194 => 1 34 34 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772195 => 1 35 35 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772196 => 1 36 36 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772197 => 1 37 37 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772198 => 1 38 38 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772199 => 1 39 39 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772200 => 1 40 40 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772201 => 1 41 41 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772202 => 1 42 42 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772203 => 1 43 43 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772204 => 1 44 44 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772205 => 1 45 45 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772206 => 1 46 46 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772207 => 1 47 47 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772208 => 1 48 48 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772209 => 1 49 49 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772210 => 1 50 50 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772211 => 1 51 51 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772212 => 1 52 52 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772213 => 1 53 53 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772214 => 1 54 54 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772215 => 1 55 55 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772216 => 1 56 56 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772217 => 1 57 57 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772218 => 1 58 58 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772219 => 1 59 59 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772220 => 1 60 60 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772221 => 1 61 61 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772222 => 1 62 62 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772223 => 1 63 63 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772224 => 1 64 64 0 0
#+END_CENTER
*** 2019-07-28: reprogramming fpga fails
#+BEGIN_CENTER
INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application
INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121
100% 11MB 1.7MB/s 00:07
fpga configuration failed. DONE PIN is not HIGH
invoked from within
"::tcf::eval -progress ::xsdb::print_progress {::tcf::cache_enter tcfchan#0 {tcf_cache_eval {process_tcf_actions_cache_client ::tcfclient#0::arg}}}"
(procedure "::tcf::cache_eval_with_progress" line 2)
invoked from within
"::tcf::cache_eval_with_progress [dict get $arg chan] [list process_tcf_actions_cache_client $argvar] $progress"
(procedure "process_tcf_actions" line 1)
invoked from within
"process_tcf_actions $arg ::xsdb::print_progress"
(procedure "fpga" line 430)
invoked from within
"fpga -f $bitimage"
(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl" line 33)
+ bash /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/pci_rescan_run.sh
Completed rescan PCIe information !
+ rmmod sume_riffa
rmmod: ERROR: Module sume_riffa is not currently loaded
+ modprobe sume_riffa
+ ifconfig nf0 up
nf0: ERROR while getting interface flags: No such device
+ ifconfig nf1 up
nf1: ERROR while getting interface flags: No such device
+ ifconfig nf2 up
nf2: ERROR while getting interface flags: No such device
+ ifconfig nf3 up
nf3: ERROR while getting interface flags: No such device
+ bash config_writes.sh
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles$
#+END_CENTER
After 2nd
#+BEGIN_CENTER
+ xsct /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl -tclargs minip4.bit
rlwrap: warning: your $TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems.
RUN loading image file.
minip4.bit
attempting to launch hw_server
****** Xilinx hw_server v2018.2
**** Build date : Jun 14 2018-20:18:37
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application
INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121
100% 11MB 1.7MB/s 00:06
+ bash /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/pci_rescan_run.sh
Completed rescan PCIe information !
+ rmmod sume_riffa
rmmod: ERROR: Module sume_riffa is not currently loaded
+ modprobe sume_riffa
+ ifconfig nf0 up
nf0: ERROR while getting interface flags: No such device
+ ifconfig nf1 up
nf1: ERROR while getting interface flags: No such device
+ ifconfig nf2 up
nf2: ERROR while getting interface flags: No such device
+ ifconfig nf3 up
nf3: ERROR while getting interface flags: No such device
+ bash config_writes.sh
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles$
#+END_CENTER #+END_CENTER
** The NetPFGA saga ** The NetPFGA saga

1
p4src/actions_egress.p4
View file

@ -28,7 +28,6 @@ action controller_reply(task_t task) {
} }
#else #else
action controller_reply(task_t task) { action controller_reply(task_t task) {
meta.task = task; meta.task = task;
meta.ingress_port = sume_metadata.src_port; meta.ingress_port = sume_metadata.src_port;

30
p4src/minip4_solution.p4
View file

@ -58,36 +58,6 @@ control RealMain(
#include "actions_egress.p4" #include "actions_egress.p4"
#include "actions_delta_checksum.p4" #include "actions_delta_checksum.p4"
action swap_eth_addresses() {
mac_addr_t temp = hdr.ethernet.dst_addr;
hdr.ethernet.dst_addr = hdr.ethernet.src_addr;
hdr.ethernet.src_addr = temp;
/* set egress port */
sume_metadata.dst_port = sume_metadata.src_port;
}
action send_to_port1() {
sume_metadata.dst_port = 1;
}
action send_to_all_ports() {
/* Taken from commands.txt of the "int" project:
table_cam_add_entry forward set_output_port 0xffffffffffff => 0b01010101
python convert:
>>> 0b01010101
85
*/
sume_metadata.dst_port = 85;
}
action do_nothing() {
mac_addr_t temp = hdr.ethernet.dst_addr;
}
apply { apply {
bit<17> tmp17 = 0; bit<17> tmp17 = 0;
bool apply_v4networks = true; bool apply_v4networks = true;

17
p4src/no_commmands.txt
View file

@ -13,21 +13,26 @@ table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 425407664113
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434184 => 8 0 0 0 0 table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434184 => 8 0 0 0 0
// 1 // 1
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434177 => 1 1 1 0 0
// 4 // 4
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434180 => 1 4 4 0 0
// 16 // 16
// 64
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434177 => 1 1 1 0 0
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434180 => 1 4 4 0 0
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434198 => 1 16 16 0 0 table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434198 => 1 16 16 0 0
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434276 => 1 64 64 0 0
// 32 // 32
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434226 => 1 32 32 0 0 table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434226 => 1 32 32 0 0
//64
table_cam_add_entry realmain_v6_networks_0 realmain.set_egress_port 42540766411362381960998550477184434276 => 1 64 64 0 0
// deleting: table_cam_delete_entry realmain_v6_networks_0 42540766411362381960998550477184434179 // deleting: table_cam_delete_entry realmain_v6_networks_0 42540766411362381960998550477184434179
// 42 del: table_cam_delete_entry realmain_v6_networks_0 42540766411362381960998550477184434242 // 42 del: table_cam_delete_entry realmain_v6_networks_0 42540766411362381960998550477184434242
// IPv4:
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772161 => 1 1 1 0 0
table_cam_delete_entry realmain_v4_networks_0 167772161