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++doc ++setup egress

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Nico Schottelius 2019-05-26 11:12:49 +02:00
parent 16e9b4cab4
commit 61b807bd2e
2 changed files with 31 additions and 2 deletions
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30
doc/plan.org
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@ -2173,7 +2173,7 @@ new dic: OrderedDict()
-> Problem seems to be that no addresses are left. Why?
****** TODO try10: find out, why nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt has too less content
****** DONE try10: find out, why nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt has too less content
******* DONE find out what generates config_writes.txt
Seems to be step 5:
@ -2186,7 +2186,7 @@ Seems to be step 5:
Sat 25 May 2019 02:23:41 PM CEST
[14:23] rainbow:SimpleSumeSwitch%
#+END_CENTER
******* TODO Debug vivado_sim.bash -> run w/ x11 output, also vivado_sim_waveform.bash
******* DONE Debug vivado_sim.bash -> run w/ x11 output, also vivado_sim_waveform.bash
Open GUI, pressing "play" button, getting different / new errors
#+BEGIN_CENTER
[SW] CAM_Init() - done
@ -2264,7 +2264,33 @@ Modifying / adjusting P4 code to mirror input packets
******** switch_calc_headers creates some headers
some specific packet, uses bind_layers
****** TODO try11: fixing gen_testdata, adding p4 code for mirroring
Failure again at step 5:
#+BEGIN_CENTER
me_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.lahsy4kevbbz5f1pl25cndeyi9crlj_812.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/lahsy4kevbbz5f1pl25cndeyi9crlj_812/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1120 File: /home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv
[SW] CAM_Init() - start
[SW] CAM_Init() - done
[SW] CAM_EnableDevice() - start
SV_write_control()- start
SV_write_control()- done
SV_read_control()- start
SV_read_control()- done
SV_write_control()- start
SV_write_control()- done
[SW] CAM_EnableDevice() - done
[2260762] INFO: finished packet stimulus file
[2735572] ERROR: tuple mismatch for packet 1
expected < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
actual < tuple_out_digest_data, tuple_out_sume_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000010000 >
$finish called at time : 2735572 ps : File "/home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" Line 120
exit
INFO: [Common 17-206] Exiting xsim at Sun May 26 11:09:04 2019...
[11:09] rainbow:SimpleSumeSwitch%
#+END_CENTER
***** run step 11: checking design -- skipped
***** TODO run step 12: ok

3
netpfga/minip4/src/minip4_solution.p4
View file

@ -59,6 +59,9 @@ control TopPipe(inout Parsed_packet p,
EthAddr_t temp = p.ethernet.dstAddr;
p.ethernet.dstAddr = p.ethernet.srcAddr;
p.ethernet.srcAddr = temp;
/* set egress port */
sume_metadata.dst_port = sume_metadata.src_port;
}
action do_nothing() {