begin to integrate headers of real code into netpfga

This commit is contained in:
Nico Schottelius 2019-06-03 22:33:37 +02:00
parent e0226c4c90
commit 63ec17b9a4
5 changed files with 133 additions and 10 deletions

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@ -1422,6 +1422,9 @@ Please make sure that it is installed and available in your $PATH:
** TODO Setup test VM [dual stack] for Jool:
** TODO Setup test VM [dual stack] for tayga:
** TODO Port to Hardware
*** NetPFGA documentation
**** Port mapping
| 1 | nf0 |
*** DONE Get access to tofino: no, NDA issues
*** DONE Get NetFPGA running
**** DONE Understand the simulations part -> not atm
@ -2893,9 +2896,10 @@ SimpleSumeSwitch(
) main;
**** Understand the different switch models (?)
*** TODO Get ANY p4 program to successfully run on netpfga
**** sending data to switch port 1
***** figuring out which port 1
**** TODO mirroring ethernet
***** no packets seen on source interface
**** TODO sending data to switch port 1
***** figuring out which is port 1: nf0
expected
actual

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@ -0,0 +1 @@
../../../p4src/headers.p4

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@ -0,0 +1,119 @@
#include <core.p4>
#include <sume_switch.p4>
#include "headers.p4"
/********************************************************************************
* Header
*/
typedef bit<48> EthAddr_t;
header Ethernet_h {
EthAddr_t dstAddr;
EthAddr_t srcAddr;
bit<16> etherType;
}
struct Parsed_packet {
Ethernet_h ethernet;
}
// user defined metadata: can be used to share information between
// TopParser, TopPipe, and TopDeparser
struct user_metadata_t {
bit<8> unused;
}
// digest_data, MUST be 256 bits -- what is this used for?
struct digest_data_t {
bit<256> unused;
}
/********************************************************************************
* Parser
*/
@Xilinx_MaxPacketRegion(1024)
parser TopParser(packet_in b,
out Parsed_packet p,
out user_metadata_t user_metadata,
out digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
state start {
b.extract(p.ethernet);
user_metadata.unused = 0;
digest_data.unused = 0;
transition accept;
}
}
/********************************************************************************
* Main
*/
control TopPipe(inout Parsed_packet p,
inout user_metadata_t user_metadata,
inout digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
action swap_eth_addresses() {
EthAddr_t temp = p.ethernet.dstAddr;
p.ethernet.dstAddr = p.ethernet.srcAddr;
p.ethernet.srcAddr = temp;
/* set egress port */
sume_metadata.dst_port = sume_metadata.src_port;
}
action send_to_port1() {
sume_metadata.dst_port = 1;
}
action do_nothing() {
EthAddr_t temp = p.ethernet.dstAddr;
}
table lookup_table {
key = {
p.ethernet.dstAddr: exact;
}
actions = {
swap_eth_addresses;
do_nothing;
send_to_port1;
}
size = 64;
// default_action = swap_eth_addresses;
default_action = send_to_port1;
}
apply {
lookup_table.apply();
}
}
/********************************************************************************
* Deparser
*/
@Xilinx_MaxPacketRegion(1024)
control TopDeparser(packet_out b,
in Parsed_packet p,
in user_metadata_t user_metadata,
inout digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
apply {
b.emit(p.ethernet);
}
}
/********************************************************************************
* Switch
*/
SimpleSumeSwitch(
TopParser(),
TopPipe(),
TopDeparser()
) main;

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@ -3,7 +3,6 @@
#define HEADERS_P4
#include <core.p4>
#include <v1model.p4>
/**************************************** types ****************************************/

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@ -631,10 +631,10 @@ control MyEgress(inout headers hdr,
*************************************************************************/
V1Switch(
MyParser(),
MyVerifyChecksum(),
MyIngress(),
MyEgress(),
MyComputeChecksum(),
MyDeparser()
MyParser(),
MyVerifyChecksum(),
MyIngress(),
MyEgress(),
MyComputeChecksum(),
MyDeparser()
) main;