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Try fix shifting errors in first block

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Nico Schottelius 2019-07-21 10:50:26 +02:00
parent 266ab1d036
commit 6b478c87f1
2 changed files with 26 additions and 3 deletions
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23
doc/plan.org
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@ -5674,6 +5674,9 @@ Result: no reply, but translated packets seen on h3; wrong IPv4
checksum; tcp checksum is ok
-> doing manual calculation to see where diff comes from
*** TODO Shifting / compile errors
v1: wrong parenthesis
#+BEGIN_CENTER
p4c --target bmv2 --arch v1model --std p4-16 "../p4src/checksum_diff.p4" -o "/home/p4/master-thesis/p4src"
../p4src/actions_delta_checksum.p4(135): warning: <<: Shifting 16-bit value with 17
@ -5688,6 +5691,26 @@ p4c --target bmv2 --arch v1model --std p4-16 "../p4src/checksum_diff.p4" -o "/ho
Compilation Error
#+END_CENTER
v2: wrong bit width
#+BEGIN_CENTER
p4c --target bmv2 --arch v1model --std p4-16 "../p4src/checksum_diff.p4" -o "/home/p4/master-thesis/p4src"
../p4src/actions_delta_checksum.p4(135): warning: <<: shifting value with 4 bits by 12
shift_tmp = (bit<16>) (hdr.ipv4.version << 12) +
^^^^^^^^^^^^^^^^^^^^^^
../p4src/actions_delta_checksum.p4(136): warning: <<: shifting value with 4 bits by 8
(bit<16>) (hdr.ipv4.ihl << 8) +
^^^^^^^^^^^^^^^^^
../p4src/actions_delta_checksum.p4(135): warning: <<: shifting value with 4 bits by 12
shift_tmp = (bit<16>) (hdr.ipv4.version << 12) +
^^^^^^^^^^^^^^^^^^^^^^
../p4src/actions_delta_checksum.p4(136): warning: <<: shifting value with 4 bits by 8
(bit<16>) (hdr.ipv4.ihl << 8) +
^^^^^^^^^^^^^^^^^
#+END_CENTER
** The NetPFGA saga
Problems encountered:
- The logfile for a compile run is 10k+ lines

6
p4src/actions_delta_checksum.p4
View file

@ -132,9 +132,9 @@ action delta_ipv4_from_v6_to_v4()
Does NOT contain payload! -> can be done manually */
shift_tmp = (bit<16>) (hdr.ipv4.version << 12) +
(bit<16>) (hdr.ipv4.ihl << 8) +
(bit<16>) (hdr.ipv4.diff_serv << 2) +
shift_tmp = ((bit<16>) hdr.ipv4.version) << 12) +
((bit<16>) hdr.ipv4.ihl) << 8) +
((bit<16>) hdr.ipv4.diff_serv) << 2) +
((bit<16>) hdr.ipv4.ecn);
tmp = tmp + shift_tmp;