port controller sending code partially to netpfga
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2 changed files with 45 additions and 14 deletions
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@ -4879,6 +4879,8 @@ actual (tlast, tkeep, tdata) = (0, ffffffff, 000000000000000080fe403b0a0000000
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#+END_CENTER
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*** 2019-06-24: find out how the expected/actual packet lines are generated
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- afair: indirectly by running gen_testdata.py -> replace script
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with port1
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** References / Follow up
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*** RFC 791 IPv4 https://tools.ietf.org/html/rfc791
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*** RFC 792 ICMP https://tools.ietf.org/html/rfc792
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@ -7,8 +7,30 @@
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* Possible bugs / things to fix:
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- Does NoAction exist?
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- Aligment of "meta"
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- replace metadate with our own
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- Aligment of "meta" / replace metadate with our own
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- what does sume_metadata contain? ingress port is where?
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nico@nsg-System:~$ find . -name sume_switch.p4
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./master-thesis/support/semester-thesis-1/project/SSS_example_2_SS/bitsnpices/sume_switch.p4
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nico@nsg-System:~$
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// one-hot encoded: {DMA, NF3, DMA, NF2, DMA, NF1, DMA, NF0}
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typedef bit<8> port_t;
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/* standard sume switch metadata */
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struct sume_metadata_t {
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bit<16> dma_q_size; // measured in 32-byte words
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bit<16> nf3_q_size; // measured in 32-byte words
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bit<16> nf2_q_size; // measured in 32-byte words
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bit<16> nf1_q_size; // measured in 32-byte words
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bit<16> nf0_q_size; // measured in 32-byte words
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bit<8> send_dig_to_cpu; // send digest_data to CPU
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bit<8> drop;
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port_t dst_port; // one-hot encoded: {DMA, NF3, DMA, NF2, DMA, NF1, DMA, NF0}
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port_t src_port; // one-hot encoded: {DMA, NF3, DMA, NF2, DMA, NF1, DMA, NF0}
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bit<16> pkt_len; // unsigned int
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}
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*/
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@ -99,20 +121,27 @@ control TopPipe(inout Parsed_packet hdr,
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set_egress_port(out_port);
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}
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// action controller_reply(task_t task) {
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// meta.task = task;
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// meta.ingress_port = standard_metadata.ingress_port;
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// clone3(CloneType.I2E, 100, meta);
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// }
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action controller_reply(task_t task) {
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meta.task = task;
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#ifdef _SUME_SWITCH_P4_
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meta.ingress_port = sume_metadata.src_port;
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// action controller_debug_table_id(table_t table_id) {
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// meta.table_id = table_id;
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// controller_reply(TASK_DEBUG);
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// }
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/* FIXME: send to controller somehow -> port? */
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#else
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meta.ingress_port = standard_metadata.ingress_port;
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clone3(CloneType.I2E, 100, meta);
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#endif
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}
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action controller_debug_table_id(table_t table_id) {
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meta.table_id = table_id;
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controller_reply(TASK_DEBUG);
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}
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action controller_debug() {
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controller_reply(TASK_DEBUG);
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}
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// action controller_debug() {
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// controller_reply(TASK_DEBUG);
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// }
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// action multicast_pkg(mcast_t mcast_grp) { /* Output PKG on correct ports (plural) */
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// standard_metadata.mcast_grp = mcast_grp;
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