Merge branch 'master' of gitlab.ethz.ch:nicosc/master-thesis
This commit is contained in:
nico
commit
8e11bec804
3 changed files with 954 additions and 4 deletions
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@ -13,7 +13,9 @@
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\vfil % or it might be \null
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\vfil % or it might be \null
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\thispagestyle{plain}
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\thispagestyle{plain}
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\begin{center}\textbf{Abstract}\end{center}
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\begin{center}\textbf{Abstract}\end{center}
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In journal articles, research papers, published patent applications and patents, an abstract is a short summary placed prior to the introduction, often with different line justification (blockquote) from the rest of the article, used to help readers determine the purpose of the paper. While the length of the abstract varies by field of study, it is typically a paragraph in length (3-5 sentences), and never more than a page. See
|
In journal articles, research papers, published patent applications and patents, an abstract is a short summary placed prior to the introduction, often with different line justification (blockquote) from the rest of the article, used to help readers determine the purpose of the paper. While the length of the abstract varies by field of study, it is typically a paragraph in length (3-5 sentences), and never more than a page. See
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||||||
\url{en.wikipedia.org/wiki/Abstract(summary)} for details
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\url{en.wikipedia.org/wiki/Abstract(summary)} for details
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||||||
\vfil
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\vfil
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\clearpage
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\clearpage
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936
doc/plan.org
936
doc/plan.org
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@ -1415,13 +1415,926 @@ Please make sure that it is installed and available in your $PATH:
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** TODO Port to Hardware
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** TODO Port to Hardware
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*** DONE Get access to tofino: no, NDA issues
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*** DONE Get access to tofino: no, NDA issues
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*** TODO Get NetFPGA running
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*** TODO Get NetFPGA running
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**** TODO Understand the simulations part
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**** DONE Understand the simulations part -> not atm
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**** TODO Install vivado
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**** DONE Install vivado
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**** DONE Install SDNET
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**** DONE Install SDNET
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**** TODO Create either HDL or PX for supporting payload checksum
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**** TODO Create either HDL or PX for supporting payload checksum
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https://github.com/NetFPGA/P4-NetFPGA-public/issues/13
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https://github.com/NetFPGA/P4-NetFPGA-public/issues/13
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https://github.com/NetFPGA/P4-NetFPGA-public/issues/13#issuecomment-490431016
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***** TODO Explore HDL
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***** TODO Explore HDL
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***** TODO Explore PX
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***** TODO Explore PX
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**** DONE fix license issue
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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echo ok
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ok
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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sdnet ./src/switch_calc.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
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Xilinx SDNet Compiler version 2018.2, build 2342300
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Cannot obtain license
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make: *** [Makefile:67: compile_no_cpp_test] Error 1
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nico@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc$
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**** TODO Testing / compiling / uploading stuff to the NetPFGA --
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https://github.com/NetFPGA/P4-NetFPGA-public/wiki/Tutorial-Assignments
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***** DONE try 1
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According to
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DO NOT USE THIS:: ==> https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/NetFPGA-SUME-Reference-Learning-Switch
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root@loch:~/projects/P4-NetFPGA/tools/scripts# ./nf_test.py hw --major learning --minor sw
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Please set the environment variable 'SUME_FOLDER' to point to the local NetFPGA source
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Traceback (most recent call last):
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File "./nf_test.py", line 632, in <module>
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identifyWorkDir()
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File "./nf_test.py", line 418, in identifyWorkDir
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project = os.path.basename(os.path.abspath(os.environ['NF_DESIGN_DIR']))
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File "/usr/lib/python2.7/UserDict.py", line 40, in __getitem__
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raise KeyError(key)
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KeyError: 'NF_DESIGN_DIR'
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root@loch:~/projects/P4-NetFPGA/tools/scripts#
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Trying
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https://github.com/NetFPGA/P4-NetFPGA-public/wiki/Tutorial-Assignments
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root@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src# mv switch_calc.p4 switch_calc_orig.p4
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root@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src# ln -s switch_calc_solution.p4 switch_calc.p4
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root@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src#
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root@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc# make
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make -C src/ clean
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make[1]: Entering directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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make -C testdata/ clean
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make[1]: Entering directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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p4c-sdnet -o .sdnet --sdnet_info .sdnet_switch_info.dat _solution.p4
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make[1]: p4c-sdnet: Command not found
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make[1]: *** [Makefile:34: all] Error 127
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make[1]: Leaving directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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make: *** [Makefile:60: frontend] Error 2
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root@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc#
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As nico:
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nico@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc$ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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||||||
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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||||||
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make -C testdata/ clean
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||||||
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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||||||
|
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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||||||
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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||||||
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rm -rf nf_sume_sdnet_ip/
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rm -f
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||||||
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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p4c-sdnet -o switch_calc.sdnet --sdnet_info .sdnet_switch_info.dat switch_calc_solution.p4
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||||||
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cpp: error: switch_calc_solution.p4: No such file or directory
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||||||
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cpp: warning: ‘-x c’ after last input file has no effect
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||||||
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cpp: fatal error: no input files
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||||||
|
compilation terminated.
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||||||
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error: Preprocessor returned exit code 256; aborting compilation
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||||||
|
error: 1 errors encountered, aborting compilation
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||||||
|
make[1]: *** [Makefile:34: all] Error 1
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||||||
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
|
||||||
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make: *** [Makefile:60: frontend] Error 2
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||||||
|
nico@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc$
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||||||
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||||||
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nico@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src$ cp switch_calc.p4 switch_calc_solution.p4
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||||||
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$ cd $P4_PROJECT_DIR/nf_sume_sdnet_ip/SimpleSumeSwitch
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||||||
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||||||
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$ ./vivado_sim.bash.
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||||||
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||||||
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***** DONE try 2: create an almost empty p4 project based on switch_calc
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||||||
|
****** DONE frontend build: ok
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||||||
|
****** DONE testdata: skipped
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||||||
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****** DONE compile_cpp_test: ok
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||||||
|
****** DONE run_scripts: ok
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||||||
|
****** TODO cpp_test: error
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||||||
|
# Fix introduced for SDNet 2017.4
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||||||
|
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
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||||||
|
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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||||||
|
# Fix introduced for SDNet 2018.2
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||||||
|
sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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||||||
|
sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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||||||
|
cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
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||||||
|
cp: cannot stat 'src/*.tbl': No such file or directory
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||||||
|
make: *** [Makefile:23: cpp_test] Error 1
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||||||
|
[23:12] loch:minip4%
|
||||||
|
******* DONE Removing cp of *tbl
|
||||||
|
******* DONE Removing pcap copy
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||||||
|
******* TODO removing all cp's
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||||||
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***** DONE try 3: good until step 4; broken at the simulation
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||||||
|
****** log 1
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||||||
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[15:26] rainbow:~% echo $P4_PROJECT_DIR
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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||||||
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[15:26] rainbow:~%
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||||||
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[15:26] rainbow:~% cd $P4_PROJECT_DIR && make
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||||||
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||||||
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
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Compiling module work.S_SYNCER_for_S_SYNCER_for_TopDep...
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||||||
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
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||||||
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
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||||||
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
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||||||
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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||||||
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
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||||||
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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||||||
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
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||||||
|
Compiling module work.S_SYNCER_for_TopDeparser
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||||||
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
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||||||
|
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
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||||||
|
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
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||||||
|
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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||||||
|
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
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||||||
|
Compiling module work.S_SYNCER_for__OUT_
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||||||
|
Compiling module work.S_CONTROLLER_SimpleSumeSwitch
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||||||
|
Compiling module work.SimpleSumeSwitch
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||||||
|
Compiling module work.TB_System_Stim
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||||||
|
Compiling module work.Check
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||||||
|
Compiling module work.SimpleSumeSwitch_tb
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||||||
|
Compiling module work.glbl
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||||||
|
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.c.
|
||||||
|
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
|
||||||
|
[15:29] rainbow:SimpleSumeSwitch% ./vivado_sim.bash
|
||||||
|
****** trying to find the error in the generated c code
|
||||||
|
[15:29] rainbow:SimpleSumeSwitch% find . -name xsim_3.c
|
||||||
|
./xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.c
|
||||||
|
****** error seems to occur in xelab
|
||||||
|
***** DONE try 4: vivado 2018.2 instead of 2018.3
|
||||||
|
Probably both ok - errors are the same
|
||||||
|
***** DONE new error: /usr/include/stdio.h:27:36: fatal error: bits/libc-header-start.h: No such file or directory
|
||||||
|
apt-get install gcc-multilib g++-multilib
|
||||||
|
***** DONE same error
|
||||||
|
Compiling module work.glbl
|
||||||
|
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.c.
|
||||||
|
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
|
||||||
|
[17:47] rainbow:SimpleSumeSwitch%
|
||||||
|
***** DONE with verbosity / fixing ncurses dependency
|
||||||
|
|
||||||
|
ICR Memory Usage: 5072KB, 18432KB
|
||||||
|
/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/clang -fPIC -c -std=gnu89 -nobuiltininc -nostdinc++ -w -Wl,--unres
|
||||||
|
olved-symbols=ignore-in-object-files -fbracket-depth=1048576 -I/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/../li
|
||||||
|
b/clang/3.1/include -fPIC -m64 -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" "xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/ob
|
||||||
|
j/xsim_3.c" -O0 -sim -o "xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.lnx64.o" -DXILINX_SIMULATOR
|
||||||
|
/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/clang: error while loading shared libraries: libncurses.so.5: cannot
|
||||||
|
open shared object file: No such file or directory
|
||||||
|
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.c.
|
||||||
|
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
|
||||||
|
[20:00] rainbow:SimpleSumeSwitch%
|
||||||
|
|
||||||
|
root@rainbow:~# apt install libncurses5-dev
|
||||||
|
|
||||||
|
|
||||||
|
[20:02] rainbow:~% ldd /opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/clang
|
||||||
|
linux-vdso.so.1 (0x00007ffda6bf6000)
|
||||||
|
libz.so.1 => /lib/x86_64-linux-gnu/libz.so.1 (0x00007f8e23208000)
|
||||||
|
libpthread.so.0 => /lib/x86_64-linux-gnu/libpthread.so.0 (0x00007f8e231e7000)
|
||||||
|
libncurses.so.5 => not found
|
||||||
|
librt.so.1 => /lib/x86_64-linux-gnu/librt.so.1 (0x00007f8e231dc000)
|
||||||
|
libdl.so.2 => /lib/x86_64-linux-gnu/libdl.so.2 (0x00007f8e231d6000)
|
||||||
|
libstdc++.so.6 => /lib/x86_64-linux-gnu/libstdc++.so.6 (0x00007f8e22ff5000)
|
||||||
|
libm.so.6 => /lib/x86_64-linux-gnu/libm.so.6 (0x00007f8e22ea5000)
|
||||||
|
libgcc_s.so.1 => /lib/x86_64-linux-gnu/libgcc_s.so.1 (0x00007f8e22e8b000)
|
||||||
|
libc.so.6 => /lib/x86_64-linux-gnu/libc.so.6 (0x00007f8e22ca0000)
|
||||||
|
/lib64/ld-linux-x86-64.so.2 (0x00007f8e2323f000)
|
||||||
|
[20:02] rainbow:~%
|
||||||
|
|
||||||
|
root@rainbow:~# apt install libncurses5
|
||||||
|
|
||||||
|
***** DONE Run step 4: ok fully works now with switch_calc_headrs and gen_testdata
|
||||||
|
****** command
|
||||||
|
cd $P4_PROJECT_DIR && make
|
||||||
|
****** DONE commented out the test data step to progress
|
||||||
|
****** TODO re-enable test data cp step => data required later
|
||||||
|
all: clean frontend compile_no_cpp_test run_scripts
|
||||||
|
cp src/*.tbl ${SDNET_OUT_DIR}/${P4_SWITCH}/
|
||||||
|
cp testdata/*.txt ${SDNET_OUT_DIR}/${P4_SWITCH}/
|
||||||
|
cp testdata/*.axi ${SDNET_OUT_DIR}/${P4_SWITCH}/
|
||||||
|
|
||||||
|
# Fix introduced for SDNet 2018.2
|
||||||
|
sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
|
||||||
|
sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
|
||||||
|
cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
|
||||||
|
cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
|
||||||
|
cp: cannot stat 'testdata/*.txt': No such file or directory
|
||||||
|
make: *** [Makefile:17: all] Error 1
|
||||||
|
[15:46] rainbow:minip4%
|
||||||
|
|
||||||
|
In testdata/Makefile:
|
||||||
|
|
||||||
|
all:
|
||||||
|
echo ok
|
||||||
|
|
||||||
|
all2:
|
||||||
|
./gen_testdata.py
|
||||||
|
${SUME_SDNET}/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
|
||||||
|
${SUME_SDNET}/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
|
||||||
|
|
||||||
|
Changing back to all:
|
||||||
|
|
||||||
|
make -C testdata/
|
||||||
|
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
||||||
|
./gen_testdata.py
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
|
||||||
|
Traceback (most recent call last):
|
||||||
|
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi", line 108, in <module>
|
||||||
|
write_to_file(args.file_pcap, args.output)
|
||||||
|
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi", line 88, in write_to_file
|
||||||
|
for pkt in rdpcap(file_in):
|
||||||
|
File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 728, in rdpcap
|
||||||
|
with PcapReader(filename) as fdesc:
|
||||||
|
File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 751, in __call__
|
||||||
|
filename, fdesc, magic = cls.open(filename)
|
||||||
|
File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 778, in open
|
||||||
|
fdesc = open(filename, "rb")
|
||||||
|
IOError: [Errno 2] No such file or directory: 'src.pcap'
|
||||||
|
make[1]: *** [Makefile:5: all] Error 1
|
||||||
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
||||||
|
make: *** [Makefile:32: frontend] Error 2
|
||||||
|
[15:47] rainbow:minip4%
|
||||||
|
****** TODO debug gen_testdata.py
|
||||||
|
***** DONE Run step 5: ok
|
||||||
|
****** command
|
||||||
|
#+BEGIN_EXAMPLE
|
||||||
|
cd $P4_PROJECT_DIR/nf_sume_sdnet_ip/SimpleSumeSwitch && ./vivado_sim.bash
|
||||||
|
#+END_EXAMPLE
|
||||||
|
***** DONE Run step 6: ok => config_writes
|
||||||
|
****** command
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
cd $P4_PROJECT_DIR && make config_writes
|
||||||
|
#+END_CENTER
|
||||||
|
***** DONE Run step 7: ok - install sume library core
|
||||||
|
****** command
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
cd $P4_PROJECT_DIR && make uninstall_sdnet && make install_sdnet
|
||||||
|
#+END_CENTER
|
||||||
|
****** log
|
||||||
|
# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
||||||
|
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]]
|
||||||
|
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]]
|
||||||
|
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]]
|
||||||
|
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]]
|
||||||
|
# update_ip_catalog -rebuild
|
||||||
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||||
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
|
||||||
|
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
|
||||||
|
# ipx::infer_user_parameters [ipx::current_core]
|
||||||
|
# ipx::check_integrity [ipx::current_core]
|
||||||
|
INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
|
||||||
|
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||||
|
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||||
|
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
|
||||||
|
# ipx::save_core [ipx::current_core]
|
||||||
|
# update_ip_catalog
|
||||||
|
# close_project
|
||||||
|
INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:18:13 2019...
|
||||||
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
|
||||||
|
[15:18] rainbow:minip4% cd $P4_PROJECT_DIR && make uninstall_sdnet && make install_sdnet
|
||||||
|
|
||||||
|
***** DONE run step 8: just copies a python script
|
||||||
|
****** run command
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
cd $NF_DESIGN_DIR/test/sim_switch_default && make
|
||||||
|
#+END_CENTER
|
||||||
|
****** log
|
||||||
|
[15:18] rainbow:minip4% cd $NF_DESIGN_DIR/test/sim_switch_default && make
|
||||||
|
rm -f config_writes.py*
|
||||||
|
rm -f *.pyc
|
||||||
|
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./
|
||||||
|
[15:18] rainbow:sim_switch_default%
|
||||||
|
***** DONE run step 9: ok sume simulation: fails with various errors, python and cp failures
|
||||||
|
****** DONE run command
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
cd $SUME_FOLDER && ./tools/scripts/nf_test.py sim --major switch --minor default
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
****** DONE python indent bug
|
||||||
|
# update_compile_order -fileset sim_1
|
||||||
|
update_compile_order: Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 1995.594 ; gain = 0.016 ; free physic
|
||||||
|
al = 21975 ; free virtual = 33161
|
||||||
|
loading libsume..
|
||||||
|
Traceback (most recent call last):
|
||||||
|
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_de
|
||||||
|
fault/run.py", line 42, in <module>
|
||||||
|
import config_writes
|
||||||
|
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_de
|
||||||
|
fault/config_writes.py", line 7
|
||||||
|
|
||||||
|
^
|
||||||
|
IndentationError: expected an indented block
|
||||||
|
while executing
|
||||||
|
"exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py"
|
||||||
|
invoked from within
|
||||||
|
"set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]"
|
||||||
|
(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_s
|
||||||
|
ume_switch_sim.tcl" line 177)
|
||||||
|
INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:21:21 2019...
|
||||||
|
|
||||||
|
-> inserting pass in def config_tables()
|
||||||
|
****** DONE post python cp error: different error after fixing python
|
||||||
|
=== Work directory is /tmp/nico/test/simple_sume_switch
|
||||||
|
=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_stim.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_expected.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_stim.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_expected.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_stim.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_expected.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_stim.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_expected.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_expected.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.log': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_expect.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.axi': No such file or directory
|
||||||
|
=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
|
||||||
|
[15:21] rainbow:P4-NetFPGA%
|
||||||
|
****** DONE "add_wave failed" (post python fix) -> go back to step 4
|
||||||
|
# add_wave $nf_sume_sdnet_ip/out_src_port
|
||||||
|
# add_wave $nf_sume_sdnet_ip/out_dst_port
|
||||||
|
# set const_reg_ip /top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/const_reg_rw_0/
|
||||||
|
# add_wave_divider {const reg extern signals}
|
||||||
|
# add_wave $const_reg_ip
|
||||||
|
ERROR: [Wavedata 42-471] Note: Nothing was found for the following items: /top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/const_reg_rw_0/
|
||||||
|
ERROR: [Common 17-39] 'add_wave' failed due to earlier errors.
|
||||||
|
|
||||||
|
while executing
|
||||||
|
"add_wave $const_reg_ip "
|
||||||
|
(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 328)
|
||||||
|
INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:31:59 2019...
|
||||||
|
make: *** [Makefile:121: sim] Error 1
|
||||||
|
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
|
||||||
|
512
|
||||||
|
=== Work directory is /tmp/nico/test/simple_sume_switch
|
||||||
|
=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory
|
||||||
|
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
|
||||||
|
=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
|
||||||
|
[15:31] rainbow:P4-NetFPGA%
|
||||||
|
***** TODO run step 10: compiling the bitstream [takes hours]
|
||||||
|
****** command
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
cd $NF_DESIGN_DIR && make
|
||||||
|
|
||||||
|
# or
|
||||||
|
|
||||||
|
cd $NF_DESIGN_DIR && make 2>&1 | tee compilelog
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
****** log
|
||||||
|
Ignoring previous errors and continuing with this step => does not
|
||||||
|
work, ends with:
|
||||||
|
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
Opening simple_sume_switch XPR project
|
||||||
|
|
||||||
|
# open_project project/$design.xpr
|
||||||
|
Scanning sources...
|
||||||
|
Finished scanning sources
|
||||||
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||||
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
|
||||||
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
||||||
|
# puts "\nOpening $design Implementation design\n"
|
||||||
|
|
||||||
|
Opening simple_sume_switch Implementation design
|
||||||
|
|
||||||
|
# open_run impl_1
|
||||||
|
ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
|
||||||
|
Vivado%
|
||||||
|
#+END_CENTER
|
||||||
|
****** DONE try 2: Run 'impl_1' has not been launched. Unable to open
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
|
||||||
|
export simple_sume_switch project to SDK
|
||||||
|
|
||||||
|
****** Vivado v2018.2 (64-bit)
|
||||||
|
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||||
|
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||||
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|
||||||
|
source tcl/export_hardware.tcl
|
||||||
|
# set design [lindex $argv 0]
|
||||||
|
# puts "\nOpening $design XPR project\n"
|
||||||
|
|
||||||
|
Opening simple_sume_switch XPR project
|
||||||
|
|
||||||
|
# open_project project/$design.xpr
|
||||||
|
Scanning sources...
|
||||||
|
Finished scanning sources
|
||||||
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||||
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
|
||||||
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
||||||
|
# puts "\nOpening $design Implementation design\n"
|
||||||
|
|
||||||
|
Opening simple_sume_switch Implementation design
|
||||||
|
|
||||||
|
# open_run impl_1
|
||||||
|
ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
|
||||||
|
Vivado%
|
||||||
|
#+END_CENTER
|
||||||
|
****** DONE try3: debug the REAL failing command
|
||||||
|
******* command
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
vivado -mode batch -source tcl/simple_sume_switch.tcl
|
||||||
|
#+END_CENTER
|
||||||
|
******* log
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
ERROR: [BD 41-171] The modes of the interface pins 'cfg_interrupt'(Slave) and 'pcie3_cfg_interrupt'(Slave) are incompatible. They cannot be connected.
|
||||||
|
ERROR: [BD 5-3] Error: running connect_bd_intf_net.
|
||||||
|
ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
|
||||||
|
|
||||||
|
while executing
|
||||||
|
"connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_interrupt [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt] [get_bd_intf_pins pcie3_7x_1/pcie3_cf..."
|
||||||
|
(procedure "create_hier_cell_dma_sub" line 141)
|
||||||
|
invoked from within
|
||||||
|
"create_hier_cell_dma_sub [current_bd_instance .] dma_sub"
|
||||||
|
(procedure "create_root_design" line 68)
|
||||||
|
invoked from within
|
||||||
|
"create_root_design """
|
||||||
|
(file "./tcl/control_sub.tcl" line 729)
|
||||||
|
|
||||||
|
while executing
|
||||||
|
"source ./tcl/control_sub.tcl"
|
||||||
|
(file "tcl/simple_sume_switch.tcl" line 89)
|
||||||
|
|
||||||
|
.... after bugfixing:
|
||||||
|
|
||||||
|
Creating bitmap...
|
||||||
|
Creating bitstream...
|
||||||
|
Bitstream compression saved 132634496 bits.
|
||||||
|
Writing bitstream ../bitfiles/simple_sume_switch.bit...
|
||||||
|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||||
|
INFO: [Common 17-83] Releasing license: Implementation
|
||||||
|
100 Infos, 51 Warnings, 1 Critical Warnings and 0 Errors encountered.
|
||||||
|
write_bitstream completed successfully
|
||||||
|
write_bitstream: Time (s): cpu = 00:02:39 ; elapsed = 00:03:20 . Memory (MB): peak = 4301.938 ; gain = 944.953 ; free physical
|
||||||
|
= 23157 ; free virtual = 31451
|
||||||
|
# exit
|
||||||
|
INFO: [Common 17-206] Exiting Vivado at Mon May 20 13:07:53 2019...
|
||||||
|
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
|
||||||
|
[13:07] rainbow:simple_sume_switch%
|
||||||
|
#+END_CENTER
|
||||||
|
******* TODO clarifying "simple_sume_switch.tcl"
|
||||||
|
******** DONE What is it?
|
||||||
|
Seems to be some kind of batch system for vivado
|
||||||
|
******** DONE Who or what created it?
|
||||||
|
Seems to be manually / from the project / not generated
|
||||||
|
******** DONE What is it trying to do?
|
||||||
|
Assuming connecting "things" on the "board".
|
||||||
|
******** DONE Why is it incompatible?
|
||||||
|
******** DONE Trying to resolve the error 1: commenting out line 538
|
||||||
|
# connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_interrupt
|
||||||
|
[get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt] [get_bd_intf_pins
|
||||||
|
pcie3_7x_1/pcie3_cfg_interrupt]
|
||||||
|
|
||||||
|
****** DONE try4 going back to step 10 -> fails
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
ume_switch/hw/project/simple_sume_switch.runs/control_sub_m00_data_fifo_0_synth_1/runme.log
|
||||||
|
control_sub_s00_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_s00_data_fifo_0_synth_1/runme.log
|
||||||
|
control_sub_auto_cc_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_auto_cc_0_synth_1/runme.log
|
||||||
|
synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth_1/runme.log
|
||||||
|
[Fri May 24 11:55:57 2019] Launched impl_1...
|
||||||
|
Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/runme.log
|
||||||
|
launch_runs: Time (s): cpu = 00:00:34 ; elapsed = 00:01:10 . Memory (MB): peak = 2538.609 ; gain = 1199.879 ; free physical = 28377 ; free virtual = 34012
|
||||||
|
# wait_on_run impl_1
|
||||||
|
[Fri May 24 11:55:57 2019] Waiting for impl_1 to finish...
|
||||||
|
[Fri May 24 12:39:07 2019] impl_1 finished
|
||||||
|
wait_on_run: Time (s): cpu = 00:26:26 ; elapsed = 00:43:10 . Memory (MB): peak = 2538.609 ; gain = 0.000 ; free physical = 28208 ; free virtual = 34003
|
||||||
|
# open_run impl_1
|
||||||
|
ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
|
||||||
|
Vivado% q
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
****** DONE try5: error: No IP matching VLNV 'NetFPGA:NetFPGA:nf_sume_sdnet:*' was found
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
[11:52] rainbow:hw% vivado -mode batch -source tcl/simple_sume_switch.tcl
|
||||||
|
...
|
||||||
|
|
||||||
|
### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
|
||||||
|
### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
|
||||||
|
### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
|
||||||
|
### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
|
||||||
|
### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
|
||||||
|
### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
|
||||||
|
Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
|
||||||
|
# create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
|
||||||
|
ERROR: [Coretcl 2-1134] No IP matching VLNV 'NetFPGA:NetFPGA:nf_sume_sdnet:*' was found. Please check your repository configuration.
|
||||||
|
INFO: [Common 17-206] Exiting Vivado at Sat May 25 11:52:01 2019...
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
****** TODO try6: go back to clean netpfga-live, diff all sources
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
|
||||||
|
|
||||||
|
[13:44] rainbow:~% diff -ru ~/P4-NetFPGA-live-clean/tools ~/projects/P4-NetFPGA/tools
|
||||||
|
Only in /home/nico/projects/P4-NetFPGA/tools/scripts/NFTest: testcheck.pyc
|
||||||
|
diff -ru /home/nico/P4-NetFPGA-live-clean/tools/settings.sh /home/nico/projects/P4-NetFPGA/tools/settings.sh
|
||||||
|
--- /home/nico/P4-NetFPGA-live-clean/tools/settings.sh 2019-05-25 11:55:45.655636066 +0200
|
||||||
|
+++ /home/nico/projects/P4-NetFPGA/tools/settings.sh 2019-05-13 11:49:02.122265641 +0200
|
||||||
|
@@ -28,7 +28,8 @@
|
||||||
|
# @NETFPGA_LICENSE_HEADER_END@
|
||||||
|
#
|
||||||
|
|
||||||
|
-export P4_PROJECT_NAME=switch_calc
|
||||||
|
+export P4_PROJECT_NAME=switch_calc
|
||||||
|
+export P4_PROJECT_NAME=minip4
|
||||||
|
export NF_PROJECT_NAME=simple_sume_switch
|
||||||
|
export SUME_FOLDER=${HOME}/projects/P4-NetFPGA
|
||||||
|
export SUME_SDNET=${SUME_FOLDER}/contrib-projects/sume-sdnet-switch
|
||||||
|
@@ -47,4 +48,3 @@
|
||||||
|
export DRIVER_FOLDER=${SUME_FOLDER}/lib/sw/std/driver/${DRIVER_NAME}
|
||||||
|
export APPS_FOLDER=${SUME_FOLDER}/lib/sw/std/apps/${DRIVER_NAME}
|
||||||
|
export HWTESTLIB_FOLDER=${SUME_FOLDER}/lib/sw/std/hwtestlib
|
||||||
|
-
|
||||||
|
[13:44] rainbow:~%
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
|
||||||
|
****** TODO try7: restart from beginning in minip4 alongside try6
|
||||||
|
- steps 1...8 ok
|
||||||
|
- step 9: fails to cp axi files
|
||||||
|
- step 9: before that a python error
|
||||||
|
****** DONE try8: fix python error in config_writes.py: script is generated
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
# set_property compxlib.xsim_compiled_library_dir {} [current_project] [0/1819]
|
||||||
|
# set_property top_lib xil_defaultlib [get_filesets sim_1]
|
||||||
|
# update_compile_order -fileset sim_1
|
||||||
|
update_compile_order: Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 2003.578 ; gain = 8.004 ; free physical = 27661 ; free virtual = 33990
|
||||||
|
loading libsume..
|
||||||
|
Traceback (most recent call last):
|
||||||
|
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py", line 42, in <module>
|
||||||
|
import config_writes
|
||||||
|
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py", line 7
|
||||||
|
|
||||||
|
^
|
||||||
|
IndentationError: expected an indented block
|
||||||
|
while executing
|
||||||
|
"exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py"
|
||||||
|
invoked from within
|
||||||
|
"set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]"
|
||||||
|
(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 177)
|
||||||
|
INFO: [Common 17-206] Exiting Vivado at Sat May 25 13:45:13 2019...
|
||||||
|
make: *** [Makefile:121: sim] Error 1
|
||||||
|
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
|
||||||
|
512
|
||||||
|
=== Work directory is /tmp/nico/test/simple_sume_switch
|
||||||
|
=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
config_writes.py
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
[13:50] rainbow:~% find ~/P4-NetFPGA-live-clean -name config_writes.py
|
||||||
|
[13:50] rainbow:~%
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
******* File does not EXIST in original repo -> might be created in step6?
|
||||||
|
"Generate the scripts that can be used in the NetFPGA SUME simulations to configure the table entries.
|
||||||
|
|
||||||
|
$ cd $P4_PROJECT_DIR && make config_writes
|
||||||
|
"
|
||||||
|
|
||||||
|
#+BEGIN_CENTER!
|
||||||
|
[13:50] rainbow:~% find ~/projects/P4-NetFPGA -name config_writes.py
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py
|
||||||
|
[13:53] rainbow:~%
|
||||||
|
|
||||||
|
[13:53] rainbow:~% grep -r config_writes.py /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/vivado.log: File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py", line 7
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/Makefile: cp ${P4_PROJECT_DIR}/testdata/config_writes.py ./
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/Makefile: rm -f config_writes.py*
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_ctrlWrites/Makefile: cp ${P4_PROJECT_DIR}/testdata/config_writes.py ./
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_ctrlWrites/Makefile: rm -f config_writes.py*
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/Makefile: ${SUME_SDNET}/bin/gen_config_writes.py ${SDNET_OUT_DIR}/${P4_SWITCH}/config_writes.txt ${P4_SWITCH_BASE_ADDR} testdata
|
||||||
|
[13:56] rainbow:~%
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
Likely:
|
||||||
|
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/Makefile: ${SUME_SDNET}/bin/gen_config_writes.py ${SDNET_OUT_DIR}/${P4_SWITCH}/config_writes.txt ${P4_SWITCH_BASE_ADDR} testdata
|
||||||
|
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch
|
||||||
|
[14:01] rainbow:sume-sdnet-switch% ls bin
|
||||||
|
conv_p414_cmds gen_P4_SWITCH_externs.py libtcam_templates.pyc nf_sim_tools.pyc
|
||||||
|
extern_data.py gen_P4_SWITCH_regs.py make_config_tables.py p4_px_tables.py
|
||||||
|
extern_data.pyc libcam_templates.py make_new_p4_proj.py pcap2axi
|
||||||
|
gen_config_fsm_writes.py libcam_templates.pyc make_regs_addressable.py sss_sume_metadata.py
|
||||||
|
gen_config_writes.py liblpm_templates.py modify_P4_SWITCH_tb.py sss_sume_metadata.pyc
|
||||||
|
gen_P4_SWITCH_API.py liblpm_templates.pyc nf_sim_compare_axi_logs.py
|
||||||
|
gen_P4_SWITCH_CLI.py libtcam_templates.py nf_sim_tools.py
|
||||||
|
[14:01] rainbow:sume-sdnet-switch%
|
||||||
|
|
||||||
|
sim_config = 'config_writes.py'
|
||||||
|
hw_config = 'config_writes.sh'
|
||||||
|
|
||||||
|
****** DONE try9: debug the script that generates the script that generates the error
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
[14:01] rainbow:sume-sdnet-switch% pwd
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch
|
||||||
|
[14:01] rainbow:sume-sdnet-switch% ls bin
|
||||||
|
conv_p414_cmds gen_P4_SWITCH_externs.py libtcam_templates.pyc nf_sim_tools.pyc
|
||||||
|
extern_data.py gen_P4_SWITCH_regs.py make_config_tables.py p4_px_tables.py
|
||||||
|
extern_data.pyc libcam_templates.py make_new_p4_proj.py pcap2axi
|
||||||
|
gen_config_fsm_writes.py libcam_templates.pyc make_regs_addressable.py sss_sume_metadata.py
|
||||||
|
gen_config_writes.py liblpm_templates.py modify_P4_SWITCH_tb.py sss_sume_metadata.pyc
|
||||||
|
gen_P4_SWITCH_API.py liblpm_templates.pyc nf_sim_compare_axi_logs.py
|
||||||
|
gen_P4_SWITCH_CLI.py libtcam_templates.py nf_sim_tools.py
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
Find the input file to find the script call directory
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
[14:04] rainbow:sume-sdnet-switch% find ~/projects/P4-NetFPGA -name config_writes.txt
|
||||||
|
/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt
|
||||||
|
[14:08] rainbow:sume-sdnet-switch%
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
Input data in nf_sume_sdnet_ip is:
|
||||||
|
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
<addr, data>: (00000020, 00000001)
|
||||||
|
<addr, data>: (00000020, 00000000)
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
Original call in the Makefile:
|
||||||
|
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
[14:10] rainbow:minip4% make config_writes
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata
|
||||||
|
[14:10] rainbow:minip4%
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
Understading gen_config_writes.py:
|
||||||
|
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
def main():
|
||||||
|
parser = argparse.ArgumentParser()
|
||||||
|
parser.add_argument('filename', type=str, help="the config_writes.txt file")
|
||||||
|
parser.add_argument('baseaddr', type=str, help="the base address of the P4_SWITCH")
|
||||||
|
parser.add_argument('outdir', type=str, help="the name of the output directory")
|
||||||
|
args = parser.parse_args()
|
||||||
|
|
||||||
|
dic = parse_config_writes(args.filename)
|
||||||
|
new_dic = remove_init_addresses(dic)
|
||||||
|
write_sim_config(new_dic, int(args.baseaddr, 0), args.outdir)
|
||||||
|
write_hw_config(new_dic, int(args.baseaddr, 0), args.outdir)
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
read arguments, create a dictionary by removing init addresses (why?
|
||||||
|
which?), create the two output files, one of them being
|
||||||
|
config_writes.py that does not have any lines.
|
||||||
|
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
def parse_config_writes(filename):
|
||||||
|
regex = r"<addr, data>: \(([abcdefABCDEF\d]*), ([abcdefABCDEF\d]*)\)"
|
||||||
|
dic = collections.OrderedDict()
|
||||||
|
i = 0
|
||||||
|
with open(filename) as f:
|
||||||
|
for line in f:
|
||||||
|
searchObj = re.match(regex, line)
|
||||||
|
if searchObj is not None:
|
||||||
|
dic[i] = (searchObj.group(1), searchObj.group(2))
|
||||||
|
else:
|
||||||
|
print >> sys.stderr, "ERROR: encountered unexpected line in file: \n", line
|
||||||
|
sys.exit(1)
|
||||||
|
i += 1
|
||||||
|
return dic
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
Looks for all matching lines, errors out if wrong lines are in there.
|
||||||
|
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
def remove_init_addresses(dic):
|
||||||
|
result = collections.OrderedDict()
|
||||||
|
for (index, tup) in dic.iteritems():
|
||||||
|
if tup[0][-2:] != "20":
|
||||||
|
result[index] = tup
|
||||||
|
return result
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
Adding debug:
|
||||||
|
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
def main():
|
||||||
|
parser = argparse.ArgumentParser()
|
||||||
|
parser.add_argument('filename', type=str, help="the config_writes.txt file")
|
||||||
|
parser.add_argument('baseaddr', type=str, help="the base address of the P4_SWITCH")
|
||||||
|
parser.add_argument('outdir', type=str, help="the name of the output directory")
|
||||||
|
args = parser.parse_args()
|
||||||
|
|
||||||
|
dic = parse_config_writes(args.filename)
|
||||||
|
print("orig dic: {}".format(dic))
|
||||||
|
new_dic = remove_init_addresses(dic)
|
||||||
|
print("new dic: {}".format(new_dic))
|
||||||
|
write_sim_config(new_dic, int(args.baseaddr, 0), args.outdir)
|
||||||
|
write_hw_config(new_dic, int(args.baseaddr, 0), args.outdir)
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
Output:
|
||||||
|
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
nfig_writes.txt 0x44020000 testdata
|
||||||
|
[14:10] rainbow:minip4% make config_writes
|
||||||
|
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata
|
||||||
|
orig dic: OrderedDict([(0, ('00000020', '00000001')), (1, ('00000020', '00000000'))])
|
||||||
|
new dic: OrderedDict()
|
||||||
|
[14:15] rainbow:minip4%
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
-> Problem seems to be that no addresses are left. Why?
|
||||||
|
|
||||||
|
|
||||||
|
****** TODO try10: find out, why nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt has too less content
|
||||||
|
|
||||||
|
***** run step 11: checking design -- skipped
|
||||||
|
***** TODO run step 12: ok
|
||||||
|
****** code
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
cd $NF_DESIGN_DIR/bitfiles && \
|
||||||
|
mv simple_sume_switch.bit ${P4_PROJECT_NAME}.bit && \
|
||||||
|
cp $P4_PROJECT_DIR/testdata/config_writes.sh ./
|
||||||
|
#+END_CENTER
|
||||||
|
***** TODO run step 13:
|
||||||
|
****** command
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
cd $NF_DESIGN_DIR/bitfiles/ && sudo bash ./program_switch.sh
|
||||||
|
#+END_CENTER
|
||||||
|
****** DONE try1: paths not setup for root
|
||||||
|
[14:54] rainbow:bitfiles% cd $NF_DESIGN_DIR/bitfiles/ && sudo bash ./program_switch.sh
|
||||||
|
./program_switch.sh: line 34: /tools/program_switch.sh: No such file or directory
|
||||||
|
[14:56] rainbow:bitfiles% ls
|
||||||
|
config_writes.sh minip4.bit program_switch.sh README
|
||||||
|
[14:56] rainbow:bitfiles%
|
||||||
|
****** DONE try2: setup paths as root: various other errors
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
root@rainbow:~# cd $NF_DESIGN_DIR/bitfiles/ && bash ./program_switch.sh
|
||||||
|
rmmod: ERROR: Module sume_riffa is not currently loaded
|
||||||
|
rlwrap: warning: your $TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems.
|
||||||
|
RUN loading image file.
|
||||||
|
switch_calc.bit
|
||||||
|
attempting to launch hw_server
|
||||||
|
****** Xilinx hw_server v2018.2
|
||||||
|
**** Build date : Jun 14 2018-20:18:37
|
||||||
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|
||||||
|
INFO: hw_server application started
|
||||||
|
INFO: Use Ctrl-C to exit hw_server application
|
||||||
|
|
||||||
|
INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121
|
||||||
|
|
||||||
|
|
||||||
|
couldn't open "switch_calc.bit": no such file or directory
|
||||||
|
invoked from within
|
||||||
|
"::tcf::eval -progress ::xsdb::print_progress {::tcf::cache_enter tcfchan#0 {tcf_cache_eval {process_tcf_actions_cache_client ::tcfclient#0::arg}}}"
|
||||||
|
(procedure "::tcf::cache_eval_with_progress" line 2)
|
||||||
|
invoked from within
|
||||||
|
"::tcf::cache_eval_with_progress [dict get $arg chan] [list process_tcf_actions_cache_client $argvar] $progress"
|
||||||
|
(procedure "process_tcf_actions" line 1)
|
||||||
|
invoked from within
|
||||||
|
"process_tcf_actions $arg ::xsdb::print_progress"
|
||||||
|
(procedure "fpga" line 430)
|
||||||
|
invoked from within
|
||||||
|
"fpga -f $bitimage"
|
||||||
|
(file "/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl" line 33)
|
||||||
|
Check programming FPGA or Reboot machine !
|
||||||
|
rmmod: ERROR: Module sume_riffa is not currently loaded
|
||||||
|
nf0: ERROR while getting interface flags: No such device
|
||||||
|
nf1: ERROR while getting interface flags: No such device
|
||||||
|
nf2: ERROR while getting interface flags: No such device
|
||||||
|
nf3: ERROR while getting interface flags: No such device
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
****** TODO try3: adjusting/analysing "./program_switch.sh"
|
||||||
|
Calls another script
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
|
||||||
|
# Program the switch with the bit file and then configure the tables
|
||||||
|
${SUME_SDNET}/tools/program_switch.sh switch_calc.bit config_writes.sh
|
||||||
|
#+END_CENTER
|
||||||
|
****** TODO try4: analyse ANOTHER program_switch.sh
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
root@rainbow:~/projects/P4-NetFPGA# find . -name program_switch.sh
|
||||||
|
./contrib-projects/sume-sdnet-switch/projects/int/simple_sume_switch/bitfiles/program_switch.sh
|
||||||
|
./contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles/program_switch.sh
|
||||||
|
./contrib-projects/sume-sdnet-switch/projects/switch_calc/simple_sume_switch/bitfiles/program_switch.sh
|
||||||
|
./contrib-projects/sume-sdnet-switch/projects/learning_switch/simple_sume_switch/bitfiles/program_switch.sh
|
||||||
|
./contrib-projects/sume-sdnet-switch/projects/tcp_monitor/simple_sume_switch/bitfiles/program_switch.sh
|
||||||
|
./contrib-projects/sume-sdnet-switch/tools/program_switch.sh
|
||||||
|
./contrib-projects/sume-sdnet-switch/templates/sss_p4_proj/simple_sume_switch/bitfiles/program_switch.sh
|
||||||
|
root@rainbow:~/projects/P4-NetFPGA#
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
Add set -x debugging, see real error
|
||||||
|
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
****** TODO try 5: reboot && retry
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
[9:24] rainbow:~% sudo -i
|
||||||
|
root@rainbow:~# lsmod | grep riffa
|
||||||
|
root@rainbow:~# modprobe sume_riffa
|
||||||
|
modprobe: FATAL: Module sume_riffa not found in directory /lib/modules/5.0.0-15-generic
|
||||||
|
root@rainbow:~#
|
||||||
|
#+END_CENTER
|
||||||
|
-> not changing
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
******* DONE Going back to setup steps
|
||||||
|
[10:11] rainbow:tcam_v1_1_0% cd $SUME_FOLDER/lib/hw/xilinx/cores/tcam_v1_1_0/ && make update && make
|
||||||
|
cd $SUME_FOLDER/lib/hw/xilinx/cores/cam_v1_1_0/ && make update && make
|
||||||
|
cd $SUME_SDNET/sw/sume && make
|
||||||
|
cd $SUME_FOLDER && make
|
||||||
|
|
||||||
|
-> all good so far
|
||||||
|
|
||||||
|
cd $DRIVER_FOLDER
|
||||||
|
make all
|
||||||
|
sudo make install
|
||||||
|
sudo modprobe sume_riffa
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#+BEGIN_CENTER
|
||||||
|
[11:44] rainbow:sume_riffa_v1_0_0% sudo make install
|
||||||
|
make -C /lib/modules/5.0.0-15-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0 modules
|
||||||
|
make[1]: Entering directory '/usr/src/linux-headers-5.0.0-15-generic'
|
||||||
|
Building modules, stage 2.
|
||||||
|
MODPOST 1 modules
|
||||||
|
make[1]: Leaving directory '/usr/src/linux-headers-5.0.0-15-generic'
|
||||||
|
install -o root -g root -m 0755 -d /lib/modules/5.0.0-15-generic/extra/sume_riffa/
|
||||||
|
install -o root -g root -m 0755 sume_riffa.ko /lib/modules/5.0.0-15-generic/extra/sume_riffa/
|
||||||
|
depmod -a 5.0.0-15-generic
|
||||||
|
[11:44] rainbow:sume_riffa_v1_0_0%
|
||||||
|
|
||||||
|
[11:44] rainbow:sume_riffa_v1_0_0% lsmod | grep sume_riffa
|
||||||
|
sume_riffa 28672 0
|
||||||
|
[11:45] rainbow:sume_riffa_v1_0_0%
|
||||||
|
|
||||||
|
#+END_CENTER
|
||||||
|
|
||||||
|
|
||||||
|
**** DONE Understand a bit of xilinx/netfpga/vivado ~ somewhat
|
||||||
|
- https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug900-vivado-logic-simulation.pdf
|
||||||
|
The xvhdl and xvlog commands parse VHDL and Verilog files, respectively. Descriptions
|
||||||
|
for each option are available in Table 5-2, page 102.
|
||||||
|
|
||||||
|
This command parses the VHDL source file(s) and stores the parsed dump into a HDL library
|
||||||
|
on disk.
|
||||||
|
***** xelab
|
||||||
|
xelab
|
||||||
|
The xelab command, for given top-level units, does the following:
|
||||||
|
• Loads children design units using language binding rules or the –L <library>
|
||||||
|
command line specified HDL libraries
|
||||||
|
• Performs a static elaboration of the design (sets parameters, generics, puts generate
|
||||||
|
statements into effect, and so forth)
|
||||||
|
• Generates executable code
|
||||||
|
• Links the generated executable code with the simulation kernel library to create an
|
||||||
|
executable simulation snapshot
|
||||||
|
You then use the produced executable simulation snapshot name as an option to the xsim
|
||||||
|
command along with other options to effect HDL simulation
|
||||||
|
***** Summary of xilinx toolchain
|
||||||
|
VHDL->[via xvhdl]-> HDL
|
||||||
|
Verilog->[via xvlog]->HDL
|
||||||
|
|
||||||
|
***** TODO Understand SimpleSumeSwitch
|
||||||
|
SimpleSumeSwitch(
|
||||||
|
TopParser(),
|
||||||
|
TopPipe(),
|
||||||
|
TopDeparser()
|
||||||
|
) main;
|
||||||
|
**** TODO Understand the different switch models (?)
|
||||||
** NAT64/NAT46 Features in jool and tayga
|
** NAT64/NAT46 Features in jool and tayga
|
||||||
*** TODO Static 1:1 NAT46: translate from IPv4 to IPv6 with a table
|
*** TODO Static 1:1 NAT46: translate from IPv4 to IPv6 with a table
|
||||||
**** TODO TCP
|
**** TODO TCP
|
||||||
|
|
@ -1897,6 +2810,25 @@ INFO:main:unhandled reassambled=<Ether dst=00:00:0a:00:00:42 src=00:00:0a:00:00
|
||||||
**** TODO tcp session
|
**** TODO tcp session
|
||||||
**** TODO udp session
|
**** TODO udp session
|
||||||
**** TODO tcp session
|
**** TODO tcp session
|
||||||
|
** TODO Hardware port
|
||||||
|
*** Installation issues
|
||||||
|
Installing vivado would stall/sleep/hang forverer due to missing
|
||||||
|
system library, no error output.
|
||||||
|
*** Build process
|
||||||
|
- Very fragile, many pieces, unclear which step is required for creating
|
||||||
|
what.
|
||||||
|
- Fails at every step
|
||||||
|
- Dependencies in over 80k lines of code (Makefile, python, shell)
|
||||||
|
- Unclear error messages
|
||||||
|
Some step did something and another step fails due do something that
|
||||||
|
was generated by a step that is not clear what it is supposed to do
|
||||||
|
- one step huge output, hundreds to thousands of lines, errors
|
||||||
|
somewher in between => exceeding tmux buffers
|
||||||
|
- some steps take VERY long correctly
|
||||||
|
- some steps stopped in an infinite loop => hard to distinguish
|
||||||
|
- non fatal/fatal errors cannot be distinguished
|
||||||
|
grep: ../../../RELEASE_NOTES: No such file or directory
|
||||||
|
|
||||||
** TODO Comparison with existing tools (Performance, Features)
|
** TODO Comparison with existing tools (Performance, Features)
|
||||||
*** Features
|
*** Features
|
||||||
| What? | Description | State in P4 | References |
|
| What? | Description | State in P4 | References |
|
||||||
|
|
|
||||||
|
|
@ -93,7 +93,7 @@ fi
|
||||||
|
|
||||||
```
|
```
|
||||||
|
|
||||||
### Compile the NetPFGA drivers
|
### Compile "SUME hardware library cores and some software to access registers"
|
||||||
|
|
||||||
|
|
||||||
```
|
```
|
||||||
|
|
@ -101,8 +101,24 @@ cd $SUME_FOLDER/lib/hw/xilinx/cores/tcam_v1_1_0/ && make update && make
|
||||||
cd $SUME_FOLDER/lib/hw/xilinx/cores/cam_v1_1_0/ && make update && make
|
cd $SUME_FOLDER/lib/hw/xilinx/cores/cam_v1_1_0/ && make update && make
|
||||||
cd $SUME_SDNET/sw/sume && make
|
cd $SUME_SDNET/sw/sume && make
|
||||||
cd $SUME_FOLDER && make
|
cd $SUME_FOLDER && make
|
||||||
|
```
|
||||||
|
|
||||||
|
### Compile SUME drivers
|
||||||
|
|
||||||
```
|
```
|
||||||
|
cd $DRIVER_FOLDER
|
||||||
|
make all
|
||||||
|
sudo make install
|
||||||
|
sudo modprobe sume_riffa
|
||||||
|
lsmod | grep sume_riffa
|
||||||
|
```
|
||||||
|
|
||||||
|
### Install packages for P4
|
||||||
|
|
||||||
|
```
|
||||||
|
root@loch:~# apt install python-scapy
|
||||||
|
```
|
||||||
|
|
||||||
|
|
||||||
## Known / encountered BUGS
|
## Known / encountered BUGS
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue