@ -49,11 +49,12 @@ After that the variable \texttt{P4\_PROJECT\_NAME} in
read \texttt { export P4\_ PROJECT\_ NAME=minip4}
instead of \texttt { export P4\_ PROJECT\_ NAME=switch\_ calc} .
Sample code for installation:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
mkdir -p ~/projects
git clone git@github.com:NetFPGA/P4-NetFPGA-live.git P4-NetFPGA
sed -i 's/\( P 4 _ PROJECT _ NAME = \) .*/\1 minip4/' ~/projects/P4-NetFPGA/tools/settings.sh
\end { verbatim}
\end { tiny}
Version \textbf { v1.3.1-46-g97d3aaa} of the P4-NetPFGA repository was
used for creating the bitfiles of this project.
\begin { verbatim}
@ -87,7 +88,7 @@ First we get the integer values of the IPv4 addresses in python:
>>>
\end { verbatim}
After that we set the table table entries for the NetFPGA.
\begin { verbatim}
\begin { tiny} \begin { verbatim}
>> table_ cam_ add_ entry realmain_ v4_ networks_ 0 realmain.set_ egress_ port 167772202 => 16 0 0 0 0
fields = [(u'hit', 1), (u'action_ run', 3), (u'out_ port', 8), (u'out_ port', 8), (u'mac_ addr', 48), (u'task', 16), (u'table_ id', 16)]
action_ name = TopPipe.realmain.set_ egress_ port
@ -120,16 +121,18 @@ READ 0x44020244 = 0x0001
success
>>
\end { verbatim}
\end { tiny}
On the host we setup the ARP entries:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
root@ESPRIMO-P956:~# ip neigh add 10.0.0.6 lladdr f8:f2:1e:09:62:d1 dev enp2s0f0
root@ESPRIMO-P956:~# ip neigh add 10.0.0.4 lladdr f8:f2:1e:09:62:d1 dev enp2s0f0
\end { verbatim}
\end { tiny}
And then we generate test packets and expect 4 packets to show up on
enp2s0f0.
The following \texttt { tcpdump} output shows the expected packets
arriving on enp2s0f0:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
nico@ESPRIMO-P956:~$ sudo tcpdump - ni enp 2 s 0 f 0
tcpdump: verbose output suppressed, use -v or -vv for full protocol decode
listening on enp2s0f0, link-type EN10MB (Ethernet), capture size 262144 bytes
@ -138,6 +141,7 @@ listening on enp2s0f0, link-type EN10MB (Ethernet), capture size 262144 bytes
10:49:29.222340 IP 10.0.0.42 > 10.0.0.4: ICMP echo request, id 4440, seq 2, length 64
10:49:29.222418 IP 10.0.0.42 > 10.0.0.4: ICMP echo request, id 4440, seq 2, length 64
\end { verbatim}
\end { tiny}
% ok
% ----------------------------------------------------------------------
\subsection { Test 2: IPv6 egress}
@ -153,6 +157,7 @@ the Integer values of the IPv6 addresses:
42540766411362381960998550477184434242L
\end { verbatim}
After that we set the table entries:
\begin { tiny}
\begin { verbatim}
>> table_ cam_ add_ entry realmain_ v6_ networks_ 0 realmain.set_ egress_ port 42540766411362381960998550477184434182 => 64 0 0 0 0
fields = [(u'hit', 1), (u'action_ run', 3), (u'out_ port', 8), (u'out_ port', 8), (u'mac_ addr', 48), (u'task', 16), (u'table_ id', 16)]
@ -192,13 +197,15 @@ READ 0x44020344 = 0x0001
success
>>
\end { verbatim}
\end { tiny}
On the host we set the IPv6 neighbor entries:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
nico@ESPRIMO-P956:~$ sudo ip - 6 neigh add 2001 :db 8 : 42 :: 6 lladdr f 8 :f 2 : 1 e: 09 : 62 :d 0 dev enp 2 s 0 f 1
nico@ESPRIMO-P956:~$ sudo ip - 6 neigh add 2001 :db 8 : 42 :: 4 lladdr f 8 :f 2 : 1 e: 09 : 62 :d 0 dev enp 2 s 0 f 1
\end { verbatim}
\end { tiny}
And generate the test packets:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
nico@ESPRIMO-P956:~$ ping 6 - c 2 2001 :db 8 : 42 :: 6
PING 2001:db8:42::6(2001:db8:42::6) 56 data bytes
@ -211,6 +218,7 @@ listening on enp2s0f1, link-type EN10MB (Ethernet), capture size 262144 bytes
11:30:18.310178 IP6 2001:db8:42::42 > 2001:db8:42::6: ICMP6, echo request, seq 2, length 64
11:30:18.310258 IP6 2001:db8:42::42 > 2001:db8:42::6: ICMP6, echo request, seq 2, length 64
\end { verbatim}
\end { tiny}
The packets are successfully seen by tcpdump.
% ----------------------------------------------------------------------
\section { \label { appendix:bmv2} P4/BMV2 environment and tests}
@ -250,7 +258,7 @@ Sometimes flashing bitfiles to the NetFPGA will fail. A random amount
of reboots (1 to 3) and a random amount of reflashing will fix this
problem.
Below can be found the log output from the flashing process.
\begin { verbatim}
\begin { tiny} \begin { verbatim}
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/bitfiles$
sudo bash -c ". $ HOME / master - thesis / netpfga / bashinit & & $ (pwd -P)/program_ switch.sh"
++ which vivado
@ -296,6 +304,7 @@ nf3: ERROR while getting interface flags: No such device
+ bash config_ writes.sh
\end { verbatim}
\end { tiny}
% ok
% ----------------------------------------------------------------------
\section { \label { appendix:netpfgalogs:flashsuccess} NetFPGA Flash Success}
@ -305,7 +314,7 @@ its succeeding lines are missing, as seen below.
After that in all cases a reboot is required; the PCI rescan in none
of our test cases re enabled the nf devices.
\begin { verbatim}
\begin { tiny} \begin { verbatim}
nico@nsg-System:~$ cd $ NF_ DESIGN_ DIR/bitfiles/
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/bitfiles$
sudo bash -c ". $ HOME / master - thesis / netpfga / bashinit & & $ (pwd -P)/program_ switch.sh"
@ -349,12 +358,13 @@ nf3: ERROR while getting interface flags: No such device
+ bash config_ writes.sh
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/bitfiles$
\end { verbatim}
\end { tiny}
% ok
% ----------------------------------------------------------------------
\section { \label { appendix:netfpgalogs:kernelmodule} NetFPGA Kernel module}
After a successful flash, loading the kernel module will enable nf
devices to appear in the operating system.
\begin { verbatim}
\begin { tiny} \begin { verbatim}
nico@nsg-System:~$ ip l
1: lo: <LOOPBACK,UP,LOWER_ UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
@ -420,13 +430,14 @@ nico@nsg-System:~$ ip l
nico@nsg-System:~$
\end { verbatim}
\end { tiny}
% ----------------------------------------------------------------------
\section { \label { appendix:netfpgalogs:compilelogs} NetFPGA compile logs}
% ----------------------------------------------------------------------
This section shows a compilation of of NetFPGA compile output and errors.
Unfound tbl files that are not correctly generated fail the compilation:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
# Fix introduced for SDNet 2017.4
sed -i 's/xsim\. dir\/ xsc\/ dpi\. so/dpi\. so/g' nf_ sume_ sdnet_ ip/SimpleSumeSwitch/vivado_ sim.bash
sed -i 's/xsim\. dir\/ xsc\/ dpi\. so/dpi\. so/g' nf_ sume_ sdnet_ ip/SimpleSumeSwitch/vivado_ sim_ waveform.bash
@ -438,13 +449,15 @@ cp: cannot stat 'src/*.tbl': No such file or directory
make: *** [Makefile:23: cpp_ test] Error 1
[23:12] loch:minip4%
\end { verbatim}
\end { tiny}
Failure to generate an intermediate file:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSumeSwitch_ tb#work.glbl/obj/xsim_ 3.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
\end { verbatim}
\end { tiny}
Failure to compile because libncurses.so.5 is missing:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/clang -fPIC -c -std=gnu89 -nobuiltininc -nostdinc++ -w -Wl,--unres
olved-symbols=ignore-in-object-files -fbracket-depth=1048576 -I/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/../li
b/clang/3.1/include -fPIC -m64 -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" "xsim.dir/work.SimpleSumeSwitch_ tb#work.glbl/ob
@ -455,9 +468,10 @@ ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSum
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
[20:00] rainbow:SimpleSumeSwitch%
\end { verbatim}
\end { tiny}
Failure to access txt files that were not correctly generated in a
different compilation step:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
# Fix introduced for SDNet 2018.2
sed -i 's/glbl_ sim/glbl/g' nf_ sume_ sdnet_ ip/SimpleSumeSwitch/vivado_ sim_ waveform.bash
sed -i 's/SimpleSumeSwitch_ tb_ sim#work.glbl/SimpleSumeSwitch_ tb/g' nf_ sume_ sdnet_ ip/SimpleSumeSwitch/vivado_ sim_ waveform.bash
@ -467,8 +481,9 @@ cp: cannot stat 'testdata/*.txt': No such file or directory
make: *** [Makefile:17: all] Error 1
[15:46] rainbow:minip4%
\end { verbatim}
\end { tiny}
Missing pcap files of non generated testdata causing compile abortion:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
make -C testdata/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
./gen_ testdata.py
@ -490,7 +505,9 @@ make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume
make: *** [Makefile:32: frontend] Error 2
[15:47] rainbow:minip4%
\end { verbatim}
\end { tiny}
Syntax errors due to incorrect generation of a python script:
\begin { tiny}
\begin { verbatim}
update_ compile_ order: Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 1995.594 ; gain = 0.016 ; free physic
al = 21975 ; free virtual = 33161
@ -512,8 +529,9 @@ IndentationError: expected an indented block
ume_ switch_ sim.tcl" line 177)
INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:21:21 2019...
\end { verbatim}
\end { tiny}
Missing axi files don't abort the compilation process: (shortened for formatting)
\begin { verbatim}
\begin { tiny} \begin { verbatim}
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 0_ log.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 0_ stim.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 0_ expected.axi': No such file or directory
@ -536,8 +554,9 @@ cp: cannot stat 'simple_sume_switch/test/reg_stim.axi': No such file or director
['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/test/sim_ switch_ default/run.py',
'--sim', 'xsim']
\end { verbatim}
\end { tiny}
Add Wave error during compilation: (shortened for formatting)
\begin { verbatim}
\begin { tiny} \begin { verbatim}
# add_ wave $ nf _ sume _ sdnet _ ip / out _ src _ port
# add_ wave $ nf _ sume _ sdnet _ ip / out _ dst _ port
# set const_ reg_ ip /top_ tb/top_ sim/nf_ datapath_ 0/nf_ sume_ sdnet_ wrapper_ 1/inst/SimpleSumeSwitch_ inst/const_ reg_ rw_ 0/
@ -565,8 +584,9 @@ cp: cannot stat 'simple_sume_switch/test/dma_0_log.axi': No such file or directo
using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/test/sim_ switch_ default/run.py', '--sim', 'xsim']
[15:31] rainbow:P4-NetFPGA%
\end { verbatim}
\end { tiny}
Compilation error failing to run ``connect\_ bd\_ intf\_ net.''
\begin { verbatim}
\begin { tiny} \begin { verbatim}
ERROR: [BD 41-171] The modes of the interface pins 'cfg_ interrupt'(Slave) and 'pcie3_ cfg_ interrupt'(Slave) are incompatible. They cannot be connected.
ERROR: [BD 5-3] Error: running connect_ bd_ intf_ net.
ERROR: [Common 17-39] 'connect_ bd_ intf_ net' failed due to earlier errors.
@ -585,8 +605,9 @@ ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
"source ./tcl/control_ sub.tcl"
(file "tcl/simple_ sume_ switch.tcl" line 89)
\end { verbatim}
\end { tiny}
Compilation aborts due to missing IP:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
### set NF_ 10G_ INTERFACE3_ BASEADDR $ M 07 _ BASEADDR
### set NF_ 10G_ INTERFACE3_ HIGHADDR $ M 07 _ HIGHADDR
### set NF_ 10G_ INTERFACE3_ SIZEADDR $ M 07 _ SIZEADDR
@ -600,8 +621,9 @@ hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
ERROR: [Coretcl 2-1134] No IP matching VLNV 'NetFPGA:NetFPGA:nf_ sume_ sdnet:*' was found. Please check your repository configuration.
INFO: [Common 17-206] Exiting Vivado at Sat May 25 11:52:01 2019...
\end { verbatim}
\end { tiny}
Mismatch: a non-critical critical error that does not abort the compilation process
\begin { verbatim}
\begin { tiny} \begin { verbatim}
[SW] CAM_ EnableDevice() - done
[2420698] INFO: finished packet stimulus file
[2735572] ERROR: tuple mismatch for packet 1
@ -611,8 +633,9 @@ $finish called at time : 2735572 ps : File
"/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_ sume_ sdnet_ ip/SimpleSumeSwitch/Testbench/Check.v"
Line 120
\end { verbatim}
\end { tiny}
Missing interface when testing switch\_ calc:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
root@rainbow:~/master-thesis/netpfga/minip4/sw/hw_ test_ tool# python switch_ calc_ tester.py
SIOCSIFADDR: No such device
eth1: ERROR while getting interface flags: No such device
@ -623,6 +646,7 @@ The HW testing tool for the switch_calc design
type help to see all commands
testing>
\end { verbatim}
\end { tiny}
Ioctl error when adding table errors on the first NetFPGA card:
\begin { verbatim}
>> table_ cam_ add_ entry lookup_ table send_ to_ port1 ff:ff:ff:ff:ff:ff =>
@ -634,7 +658,7 @@ python: ioctl: Unknown error 512
[20:27] rainbow:CLI%
\end { verbatim}
Exec format errors when loading the kernel module due to incompabilities:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
[7:05] rainbow:netpfga% bash build-load-drivers.sh
+ cd /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0
+ make all
@ -656,8 +680,10 @@ depmod -a 5.0.0-16-generic
modprobe: ERROR: could not insert 'sume_ riffa': Exec format error
[7:06] rainbow:netpfga%
\end { verbatim}
\end { tiny}
Java traceback when trying to install SDNET:
(reason was a hidden window)
\begin { tiny}
\begin { verbatim}
Exception in thread "AWT-EventQueue-0" java.lang.IllegalArgumentException: Window must not be zero
at java.desktop/sun.awt.X11.XAtom.checkWindow(Unknown Source)
@ -719,8 +745,9 @@ Exception in thread "AWT-EventQueue-0" java.lang.IllegalArgumentException: Windo
at java.desktop/java.awt.EventDispatchThread.pumpEvents(Unknown Source)
at java.desktop/java.awt.EventDispatchThread.run(Unknown Source)
\end { verbatim}
\end { tiny}
Failures when testing the first NetFPGA card
\begin { verbatim}
\begin { tiny} \begin { verbatim}
---------------------------------------------
[ddr3B]: Running Auto Test
---------------------------------------------
@ -752,7 +779,9 @@ Traceback (most recent call last):
raise child_ exception
OSError: [Errno 2] No such file or directory
\end { verbatim}
\end { tiny}
More failures when testing the first NetFPGA card
\begin { tiny}
\begin { verbatim}
---------------------------------------------
[pcie]: Running Auto Test
@ -777,6 +806,7 @@ Traceback (most recent call last):
raise SerialException('device reports readiness to read but returned no data (device disconnected or multiple access on port?)')
SerialException: device reports readiness to read but returned no data (device disconnected or multiple access on port?)
\end { verbatim}
\end { tiny}
Unexpected EOF during compilation:
\begin { verbatim}
ERROR: [VRFC 10-1491] unexpected EOF
@ -791,6 +821,7 @@ INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_5_ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_ t_ EngineStage_ 6_ ErrorCheck
\end { verbatim}
The function syntax is not supported by p4/netfpga:
\begin { tiny}
\begin { verbatim}
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
p4c-sdnet -o minip4.sdnet --sdnet_ info .sdnet_ switch_ info.dat minip4_ solution.p4
@ -805,9 +836,10 @@ Makefile:31: recipe for target 'frontend' failed
make: *** [frontend] Error 2
nico@nsg-System:~/master-thesis/netpfga$
\end { verbatim}
\end { tiny}
The config\_ writes.py is missing due to a previous, non critical
compilation error:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/test/sim_ switch_ default$
cd $ NF _ DESIGN _ DIR / test / sim _ switch _ default & & make 2 > & 1 | tee ~ / master - thesis / netpfga / log / step 8 - $ (date +% F-% H% M% S)
rm -f config_ writes.py*
@ -817,8 +849,9 @@ cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-swit
Makefile:36: recipe for target 'all' failed
make: *** [all] Error 1
\end { verbatim}
\end { tiny}
Failed to synthesizing module errors:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
WARNING: [Synth 8-689] width (12) of port connection 'control_ S_ AXI_ ARADDR' does not match port width (8) of module 'SimpleSumeSwitch'
[/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/hw/project/
simple_ sume_ switch.srcs/sources_ 1/ip/nf_ sume_ sdnet_ ip/nf_ sume_ sdnet_ ip/wrapper/nf_ sume_ sdnet.v:199]
@ -841,8 +874,9 @@ ERROR: [Synth 8-6156] failed synthesizing module 'top'
[/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/
simple_ sume_ switch/hw/hdl/top.v:43]
\end { verbatim}
\end { tiny}
Missing ``souce'' files abort CLI compilation errors:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c
-I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
cc -std=c99 -Wall -Werror -fPIC -c libcam.c
@ -857,7 +891,9 @@ make[1]: *** [libcam] Error 1
make[1]: Leaving directory '/home/nico/master-thesis/netpfga/minip4/sw/CLI'
ERROR: could not compile libcam souce files
\end { verbatim}
\end { tiny}
Generated axi files not found at a different stage:
\begin { tiny}
\begin { verbatim}
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/
sume-sdnet-switch/projects/minip4/simple_ sume_ switch/test/dma_ 0_ expected.axi': No such file or directory
@ -877,14 +913,16 @@ NetFPGA environment:
512
=== Work directory is /tmp/nico/test/simple_ sume_ switch
=== Setting up test in /tmp/nico/test/simple_ sume_ switch/sim_ switch_ default
=== Running test /tmp/nico/test/simple_ sume_ switch/sim_ switch_ default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/test/sim_ switch_ default/run.py', '--sim', 'xsim']
+ date
=== Running test /tmp/nico/test/simple_ sume_ switch/sim_ switch_ default ... using
cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/
minip4/simple_ sume_ switch/test/sim_ switch_ default/run.py', '--sim', 'xsim']+ date
Die Jul 23 13:34:54 CEST 2019
+ [ = no ]
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch
+ make
make: *** No targets specified and no makefile found. Stop.
\end { verbatim}
\end { tiny}
Renaming variables as follows breaks the compile process
\begin { verbatim}
@Xilinx_ MaxPacketRegion(1024)
@ -906,6 +944,7 @@ Renaming variables as follows breaks the compile process
}
\end { verbatim}
In NetPFGA the LPM table size must be != 64:
\begin { tiny}
\begin { verbatim}
minip4_ solution.p4(38): [--Wwarn=uninitialized_ out_ param] warning: out parameter meta may be uninitialized when RealParser terminates
out metadata meta,
@ -932,8 +971,9 @@ Makefile:31: recipe for target 'frontend' failed
make: *** [frontend] Error 2
nico@nsg-System:~/master-thesis/netpfga/log$
\end { verbatim}
\end { tiny}
Cannot mix the key table types with P4/NetFPGA:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
p4c-sdnet -o minip4.sdnet --sdnet_ info .sdnet_ switch_ info.dat minip4_ solution.p4
actions_ egress.p4(52): warning: Table v6_ networks is not used; removing
@ -973,8 +1013,9 @@ make[1]: *** [all] Error 1
default_ action = controller_ debug_ table_ id(TABLE_ ARP);
}
\end { verbatim}
\end { tiny}
Implicit error saying that LPM tables don't work in P4/NetFPGA:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
s/sume-sdnet-switch/projects/minip4/nf_ sume_ sdnet_ ip/SimpleSumeSwitch/realmain_ lookup_ table_ 0_ t.HDL/xpm_ memory.sv
[SW] LPM_ Init() - start
[SW] LPM_ Init() - done
@ -984,8 +1025,9 @@ FATAL_ERROR: Vivado Simulator kernel has encounted an exception from DPI C funct
Time: 2016466 ps Iteration: 0 Process: /SimpleSumeSwitch_ tb/LPM_ VerifyDataset
File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_ sume_ sdnet_ ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_ tb.sv
\end { verbatim}
\end { tiny}
The table for exact matches must be at least 64 in P4/NetFPGA:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
minip4_ solution.p4(35)
parser RealParser(
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
@ -996,8 +1038,9 @@ actions_nat64_generic.p4(173): error: could not not map table size size
size = 63;
^ ^ ^ ^
\end { verbatim}
\end { tiny}
Unsupported default parameters in P4/NetFPGA:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
actions_ egress.p4(89): error: data-plane arguments in default_ actions are currently unsupported: realmain_ controller_ debug_ table_ id_ 0
default_ action = controller_ debug_ table_ id(TABLE_ V4_ NETWORKS);
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
@ -1007,8 +1050,9 @@ Compiler Bug: actions_egress.p4(89): unhandled expression realmain_controller_de
default_ action = controller_ debug_ table_ id(TABLE_ V4_ NETWORKS);
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
\end { verbatim}
\end { tiny}
Causing compiler bug by using an if statement at a wrong place in P4/NetFPGA:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
minip4_ solution.p4(39)
parser RealParser(
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
@ -1021,8 +1065,10 @@ make[1]: *** [all] Error 134
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
Makefile:31: recipe for target 'frontend' failed
\end { verbatim}
\end { tiny}
Applying table ``twice'' in different branches is impossible in
P4/NetFPGA causes a different compiler bug:
\begin { tiny}
\begin { verbatim}
make -C src/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
@ -1039,20 +1085,26 @@ Compiler Bug: overwrite
Makefile:34: recipe for target 'all' failed
\end { verbatim}
\end { tiny}
Adding table entries requires setting parameters for all possible
actions that are registered in a table:
\begin { tiny}
\begin { verbatim}
>> table_ cam_ add_ entry realmain_ v6_ networks_ 0 realmain.set_ egress_ port
42540766411362381960998550477184434178 => 1 ERROR: not enough fields provided to complete _ hexify()
\end { verbatim}
\end { tiny}
The table handling scripts do not handle conversion for long integers
for P4/NetFPGA:
\begin { tiny}
\begin { verbatim}
>> table_ cam_ delete_ entry realmain_ v6_ networks_ 0 42540766411362381960998550477184434179
ERROR: failed to convert 42540766411362381960998550477184434179 of type <type 'long'> to an integer
nico@nsg-System:~/master-thesis/netpfga/minip4/sw/CLI$
\end { verbatim}
\end { tiny}
A P4/BMV2 compiler error:
\begin { tiny}
\begin { verbatim}
Warning: you requested the nanomsg event logger, but bmv2 was compiled without -DBMELOG, and the event logger cannot be activated
Calling target program-options parser
@ -1083,6 +1135,7 @@ bad json:
}
}
\end { verbatim}
\end { tiny}
Inability of P4/BMV2 to have multiple LPM keys in a table:
\begin { verbatim}
@ -1106,12 +1159,15 @@ Compilation Error
}
\end { verbatim}
Switch statements are not allowed in P4/BMV:
\begin { tiny}
\begin { verbatim}
../p4src/static-mapping.p4(60): error: SwitchStatement: switch statements not allowed in actions
switch(hdr.icmp6.type) {
^ ^ ^ ^ ^ ^
\end { verbatim}
\end { tiny}
And also no ifs in actions:
\begin { tiny}
\begin { verbatim}
../p4src/static-mapping.p4(57): error: MethodCallStatement: Conditional execution in actions is not supported on this target
hdr.icmp.setValid();
@ -1132,7 +1188,9 @@ p4@ubuntu:~/master-thesis/p4app$
nat64_ icmp6();
}
\end { verbatim}
\end { tiny}
Compiler bug in P4/BMV2:
\begin { tiny}
\begin { verbatim}
p4c --target bmv2 --arch v1model --std p4-16 "../p4src/checksum_ diff.p4" -o "/home/p4/master-thesis/p4src"
In file: /home/p4/p4-tools/p4c/backends/bmv2/common/expression.cpp:168
@ -1157,6 +1215,7 @@ And p4c version:
```p4@ubuntu:~/master-thesis/p4app$ p 4 c - - version
p4c 0.5 (SHA: 5ae30ee)```
\end { verbatim}
\end { tiny}
% ----------------------------------------------------------------------
\chapter { \label { benchmark} Benchmark Logs}
@ -1273,7 +1332,7 @@ rtt min/avg/max/mdev = 0.097/0.200/0.304/0.104 ms
[15:12] nsg-System:~#
\end { verbatim}
We also setup the IPv6 networking:
\begin { verbatim}
\begin { tiny} \begin { verbatim}
nico@ESPRIMO-P956:~$ ip addr show dev enp 2 s 0 f 1
13: enp2s0f1: <BROADCAST,MULTICAST,UP,LOWER_ UP> mtu 1500 qdisc mq state UP group default qlen 1000
link/ether f8:f2:1e:09:62:d1 brd ff:ff:ff:ff:ff:ff
@ -1286,6 +1345,7 @@ nico@ESPRIMO-P956:~$ sudo ip route add 2001:db8:23::/96 via 2001:db8:42::77
[15:12] nsg-System:~# ip addr add 2001:db8:42::77/64 dev eth2
[15:15] nsg-System:~# ip link set eth2 up
\end { verbatim}
\end { tiny}
And verify that IPv6 networking works:
\begin { verbatim}
nico@ESPRIMO-P956:~$ ping 6 - c 2 2001 :db 8 : 42 :: 77
@ -1307,6 +1367,7 @@ net.ipv6.conf.all.forwarding = 1
net.ipv4.ip_ forward = 1
\end { verbatim}
And we test NAT64 with tayga:
\begin { tiny}
\begin { verbatim}
nico@ESPRIMO-P956:~$ ping - c 2 10 . 0 . 1 . 42
PING 10.0.1.42 (10.0.1.42) 56(84) bytes of data.
@ -1331,6 +1392,8 @@ listening on enp2s0f1, link-type EN10MB (Ethernet), capture size 262144 bytes
0 packets dropped by kernel
nico@ESPRIMO-P956:~$
\end { verbatim}
\end { tiny}
And test NAT64 from IPv6 to IPv4:
\begin { verbatim}
nico@ESPRIMO-P956:~$ ping 6 - c 2 2001 :db 8 : 23 ::a 00 : 2 a
@ -1347,6 +1410,7 @@ nico@ESPRIMO-P956:~$
\section { \label { benchmark:jool} Jool}
We install Jool 4.0.1 from source from
\url { https://www.jool.mx/en/download.html} as follows:
\begin { tiny}
\begin { verbatim}
nico@nsg-System:~$ wget https: / / github.com / NICMx / Jool / releases / download / v 4 . 0 . 1 / jool _ 4 . 0 . 1 .tar.gz
nico@nsg-System:~$ tar xvfz jool _ 4 . 0 . 1 .tar.gz
@ -1356,6 +1420,7 @@ nico@nsg-System:~/jool-4.0.1$ sudo apt install libnl-genl-3-dev
nico@nsg-System:~/jool-4.0.1$ sudo apt install iptables - dev
nico@nsg-System:~/jool-4.0.1$ sudo make install
\end { verbatim}
\end { tiny}
We enable forwarding:
\begin { verbatim}
sysctl -w net.ipv4.conf.all.forwarding=1
@ -1363,6 +1428,7 @@ sysctl -w net.ipv6.conf.all.forwarding=1
\end { verbatim}
We configure jool to map the network prefixes and setup iptables to
redirect the traffic into the jool instance:
\begin { tiny}
\begin { verbatim}
[16:53] nsg-System:~# modprobe jool_ siit
[16:54] nsg-System:~# jool_ siit instance add "example" --iptables
@ -1371,6 +1437,7 @@ redirect the traffic into the jool instance:
[16:57] nsg-System:~# ip6tables -t mangle -A PREROUTING -s 2001:db8:42::/120 -d 2001:db8:23::/120 -j JOOL_ SIIT --instance example
[16:57] nsg-System:~# iptables -t mangle -A PREROUTING -s 10.0.0.0/24 -d 10.0.1.0/24 -j JOOL_ SIIT --instance example
\end { verbatim}
\end { tiny}
Afterwards we test NAT64:
\begin { verbatim}
nico@ESPRIMO-P956:~/master-thesis/iperf$ ping 6 2001 :db 8 : 23 :: 2 a