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Change testdata offset by 1 and find checksum error

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master
Nico Schottelius 4 years ago
parent 85fee75077
commit a9cc93281e
2 changed files with 143 additions and 32 deletions
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doc/plan.org
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@ -1167,10 +1167,12 @@ Install the project...
(virtualenv-with-site) [0:42] line:build% ls /home/nico/vcs/master-thesis/support/p4c-installation/bin/
p4c p4c-bm2-psa p4c-bm2-ss p4c-ebpf p4c-graphs p4test
(virtualenv-with-site) [0:42] line:build%
*** TODO install behavioral-model
*** TODO Debug / reread the virtualbox script from the lecture
*** TODO Get p4c installed / running
*** DONE install behavioral-model
CLOSED: [2019-07-13 Sat 21:49]
*** DONE Debug / reread the virtualbox script from the lecture
CLOSED: [2019-07-13 Sat 21:50]
*** DONE Get p4c installed / running
CLOSED: [2019-07-13 Sat 21:50]
https://github.com/p4lang/p4c
**** log
[16:31] line:p4c% git submodule update --init --recursive
@ -1322,7 +1324,8 @@ CMake Warning at backends/bmv2/CMakeLists.txt:199 (MESSAGE):
CMAKE_INSTALL_PREFIX
cmake .. '-DCMAKE_CXX_FLAGS:STRING=-O3' -DCMAKE_INSTALL_PREFIX=/home/nico/vcs/master-thesis/support/p4c-installation
*** TODO Get p4utils running (?)
*** DONE Get p4utils running (?)
CLOSED: [2019-07-13 Sat 21:50]
*** log of python, p4app, p4c installation
[16:16] line:support% virtualenv virtualenv2
Running virtualenv with interpreter /usr/bin/python2
@ -3247,8 +3250,28 @@ ERROR: failed to convert p.ethernet.dstAddr of type <type 'str'> to an integer
**** TODO Explore PX
*** TODO Integrate nat64 code into netfpga
**** figure out how to do ANY checksums
** Diff / Delta based checksums
*** create test case / test theory
** TODO Diff / Delta based checksums
*** DONE create test case / test theory
CLOSED: [2019-07-13 Sat 21:50]
*** Understand the complement implementation in P4/C
**** P4
- Fixed-width signed integers represented using two's complement
int<>
- • Bitwise “complement” of a single bit-string, denoted by ~ .
**** RFC 791/IPv4
The checksum field is the 16-bit one's complement of the one's
complement sum of all 16-bit words in the header. For purposes of
computing the checksum, the value of the checksum field is zero.
"The result of summing the entire IP header, including checksum,
should be zero if there is no corruption."
2x carry bit ! The result of summing the entire IP header, including
checksum, should be zero if there is no corruption.
https://en.wikipedia.org/wiki/IPv4_header_checksum
**** TODO try first v6/v6
**** using python/struct
***** find right byte orders
@ -5199,11 +5222,118 @@ nico 6399 0.0 0.0 4508 708 pts/10 S+ 18:24 0:00 | |
lse \ ?echo "Project simple_sume_switch does not exist.";\ ?echo "Please run \"make project\" to create and build the project first";\ fi;\ nico 6400 0.0 0.0 12948 3368 pts/10 S+ 18:24 0:00 | | \_ /bin/bash /opt/Xilinx/Vivado/2018.2/bin/vivado -mode tcl -source tcl/export_hardware.tcl -tclargs simple_sume_switch
nico 6424 0.0 0.0 12944 3132 pts/10 S+ 18:24 0:00 | | \_ /bin/bash /opt/Xilinx/Vivado/2018.2/bin/loader -exec vivado -mode tcl -source tcl/export_hardware.tcl -tclargs simple_sume_switch
nico 6440 0.4 4.0 1397068 643640 pts/10 Sl+ 18:24 0:11 | | \_ /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/vivado -mode tcl -source tcl/export_hardware.tcl -tclargs simple_sume_switch
#+END_CENTER
Check whether symlink is a problem:
#+BEGIN_CENTER
nico@nsg-System:~/master-thesis/netpfga$ rm ~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
nico@nsg-System:~/master-thesis/netpfga$ mkdir ~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
nico@nsg-System:~/master-thesis/netpfga$ sudo mount --bind ~nico/master-thesis/netpfga/minip4/ ~nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
nico@nsg-System:~/master-thesis/netpfga$
nico@nsg-System:~/master-thesis/netpfga$ rm /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src
nico@nsg-System:~/master-thesis/netpfga$ mkdir /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src
nico@nsg-System:~/master-thesis/netpfga$ sudo mount --bind ~nico/master-thesis/p4src/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src
#+END_CENTER
likely this is the cause for the main error:
+ ./tools/scripts/nf_test.py sim --major switch --minor default
**** go through all steps again and try to understand why it (silently) fails later
*** 2019-07-13: fix overflow error
** The NetPFGA saga
Problems encountered:
- The logfile for a compile run is 10k+ lines
- Many logged errors can actually be ignored (?) like:
ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_DATA on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:219]
ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_VALID on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:218]
ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_DATA on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:185]
ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_VALID on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:184]
ERROR: [VRFC 10-2063] Module <S_RESETTER_line> not found while processing module instance <S_RESET_clk_line> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/Simp
leSumeSwitch/SimpleSumeSwitch.v:332]
ERROR: [VRFC 10-2063] Module <S_RESETTER_lookup> not found while processing module instance <S_RESET_clk_lookup> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/
SimpleSumeSwitch/SimpleSumeSwitch.v:343]
ERROR: [VRFC 10-2063] Module <S_RESETTER_control> not found while processing module instance <S_RESET_clk_control> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_i
p/SimpleSumeSwitch/SimpleSumeSwitch.v:354]
ERROR: [VRFC 10-2063] Module <TopParser_t> not found while processing module instance <TopParser> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitc
h/SimpleSumeSwitch.v:436]
ERROR: [VRFC 10-2063] Module <TopPipe_lvl_t> not found while processing module instance <TopPipe_lvl> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeS
witch/SimpleSumeSwitch.v:474]
ERROR: [VRFC 10-2063] Module <dummy_table_for_netpfga_t> not found while processing module instance <dummy_table_for_netpfga> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_s
ume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:502]
ERROR: [VRFC 10-2063] Module <TopPipe_lvl_0_t> not found while processing module instance <TopPipe_lvl_0> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleS
umeSwitch/SimpleSumeSwitch.v:533]
ERROR: [VRFC 10-2063] Module <TopDeparser_t> not found while processing module instance <TopDeparser> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeS
witch/SimpleSumeSwitch.v:561]
# launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
CRITICAL WARNING: [BD 41-1356] Address block </M04_AXI/Reg> is not mapped into </S00_AXI>. Please use Address Editor to either map or exclude it.
CRITICAL WARNING: [BD 41-1356] Address block </M05_AXI/Reg> is not mapped into </S00_AXI>. Please use Address Editor to either map or exclude it.
WARNING: [VRFC 10-756] identifier state is used before its declaration [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:93]
WARNING: [VRFC 10-756] identifier ready_count is used before its declaration [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:94]
INFO: [#UNDEF] Sorry, too many errors..
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' file for more information.
nico@nsg-System:~/master-thesis$ find . -name elaborate.log
nico@nsg-System:~/master-thesis$ find ~ -name elaborate.log
nico@nsg-System:~/master-thesis$
- Scripts that "fail" (generate wrong data) do exit 0 ->
There is no easy / reliable error detection
- Writing tables resulted in ioctl errors
- Hardware test: unclear if first board was/is broken or not,
BUT: second board in different computer allows writing tables
- Many scripts depend on each other in later stages, without clear
dependencies
- There is basically no documentation for someone who "just wants to
compile from P4 to netpfga" or A LOT of documentation (if vivado,
vhld, sdnet documentation is counted)
- Very high complexity in toolchain, scripts that are generated
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default
+ make
rm -f config_writes.py*
rm -f *.pyc
nico@nsg-System:~$ cat /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py
from NFTest import *
NUM_WRITES = 4
def config_tables():
nftest_regwrite(0x44020050, 0x22222208)
nftest_regwrite(0x44020054, 0x00000822)
nftest_regwrite(0x44020080, 0x00000201)
nftest_regwrite(0x44020040, 0x00000001)
nico@nsg-System:~$ cat /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.sh
#!/bin/bash
${SUME_SDNET}/sw/sume/rwaxi -a 0x44020050 -w 0x22222208
${SUME_SDNET}/sw/sume/rwaxi -a 0x44020054 -w 0x00000822
${SUME_SDNET}/sw/sume/rwaxi -a 0x44020080 -w 0x00000201
${SUME_SDNET}/sw/sume/rwaxi -a 0x44020040 -w 0x00000001
nico@nsg-System:~$
- Misleading errors like
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' file for more information.
nico@nsg-System:~/master-thesis/netpfga$ ls /home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log
ls: cannot access '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log': No such file or directory
** References / Follow up
*** RFC 791 IPv4 https://tools.ietf.org/html/rfc791
*** RFC 792 ICMP https://tools.ietf.org/html/rfc792

31
netpfga/minip4/testdata/gen_testdata-port1.py vendored
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@ -106,33 +106,14 @@ def test_port1():
pkt = Ether(dst=MAC2, src=MAC1)
pkt = pad_pkt(pkt, 64)
# Send on nf0
pktCnt += 1
applyPkt(pkt, 'nf0', pktCnt)
# Receive on nf0
expPkt(pkt, 'nf0')
# Send on nf1
pktCnt += 1
applyPkt(pkt, 'nf1', pktCnt)
for inport in [ 'nf0', 'nf1', 'nf2', 'nf3' ]:
# Send on nf0
applyPkt(pkt, inport, pktCnt)
# Receive on nf0
expPkt(pkt, 'nf0')
# Send on nf2
pktCnt += 1
applyPkt(pkt, 'nf2', pktCnt)
# Receive on nf0
expPkt(pkt, 'nf0')
# Send on nf3
pktCnt += 1
applyPkt(pkt, 'nf3', pktCnt)
# Always receive on nf0
expPkt(pkt, 'nf0')
# Receive on nf0
expPkt(pkt, 'nf0')
pktCnt += 1
# Test that packets are being mirrored
def test_mirror():

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