Change testdata offset by 1 and find checksum error
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Nico Schottelius
parent
85fee75077
commit
a9cc93281e
144
doc/plan.org
144
doc/plan.org
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@ -1167,10 +1167,12 @@ Install the project...
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(virtualenv-with-site) [0:42] line:build% ls /home/nico/vcs/master-thesis/support/p4c-installation/bin/
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p4c p4c-bm2-psa p4c-bm2-ss p4c-ebpf p4c-graphs p4test
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(virtualenv-with-site) [0:42] line:build%
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*** TODO install behavioral-model
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*** TODO Debug / reread the virtualbox script from the lecture
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*** TODO Get p4c installed / running
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*** DONE install behavioral-model
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CLOSED: [2019-07-13 Sat 21:49]
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*** DONE Debug / reread the virtualbox script from the lecture
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CLOSED: [2019-07-13 Sat 21:50]
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*** DONE Get p4c installed / running
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CLOSED: [2019-07-13 Sat 21:50]
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https://github.com/p4lang/p4c
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**** log
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[16:31] line:p4c% git submodule update --init --recursive
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@ -1322,7 +1324,8 @@ CMake Warning at backends/bmv2/CMakeLists.txt:199 (MESSAGE):
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CMAKE_INSTALL_PREFIX
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cmake .. '-DCMAKE_CXX_FLAGS:STRING=-O3' -DCMAKE_INSTALL_PREFIX=/home/nico/vcs/master-thesis/support/p4c-installation
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*** TODO Get p4utils running (?)
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*** DONE Get p4utils running (?)
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CLOSED: [2019-07-13 Sat 21:50]
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*** log of python, p4app, p4c installation
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[16:16] line:support% virtualenv virtualenv2
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Running virtualenv with interpreter /usr/bin/python2
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@ -3247,8 +3250,28 @@ ERROR: failed to convert p.ethernet.dstAddr of type <type 'str'> to an integer
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**** TODO Explore PX
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*** TODO Integrate nat64 code into netfpga
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**** figure out how to do ANY checksums
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** Diff / Delta based checksums
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*** create test case / test theory
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** TODO Diff / Delta based checksums
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*** DONE create test case / test theory
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CLOSED: [2019-07-13 Sat 21:50]
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*** Understand the complement implementation in P4/C
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**** P4
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- Fixed-width signed integers represented using two's complement
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int<>
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- • Bitwise “complement” of a single bit-string, denoted by ~ .
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**** RFC 791/IPv4
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The checksum field is the 16-bit one's complement of the one's
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complement sum of all 16-bit words in the header. For purposes of
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computing the checksum, the value of the checksum field is zero.
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"The result of summing the entire IP header, including checksum,
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should be zero if there is no corruption."
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2x carry bit ! The result of summing the entire IP header, including
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checksum, should be zero if there is no corruption.
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https://en.wikipedia.org/wiki/IPv4_header_checksum
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**** TODO try first v6/v6
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**** using python/struct
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***** find right byte orders
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@ -5199,11 +5222,118 @@ nico 6399 0.0 0.0 4508 708 pts/10 S+ 18:24 0:00 | |
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lse \ ?echo "Project simple_sume_switch does not exist.";\ ?echo "Please run \"make project\" to create and build the project first";\ fi;\ nico 6400 0.0 0.0 12948 3368 pts/10 S+ 18:24 0:00 | | \_ /bin/bash /opt/Xilinx/Vivado/2018.2/bin/vivado -mode tcl -source tcl/export_hardware.tcl -tclargs simple_sume_switch
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nico 6424 0.0 0.0 12944 3132 pts/10 S+ 18:24 0:00 | | \_ /bin/bash /opt/Xilinx/Vivado/2018.2/bin/loader -exec vivado -mode tcl -source tcl/export_hardware.tcl -tclargs simple_sume_switch
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nico 6440 0.4 4.0 1397068 643640 pts/10 Sl+ 18:24 0:11 | | \_ /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/vivado -mode tcl -source tcl/export_hardware.tcl -tclargs simple_sume_switch
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#+END_CENTER
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Check whether symlink is a problem:
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#+BEGIN_CENTER
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nico@nsg-System:~/master-thesis/netpfga$ rm ~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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nico@nsg-System:~/master-thesis/netpfga$ mkdir ~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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nico@nsg-System:~/master-thesis/netpfga$ sudo mount --bind ~nico/master-thesis/netpfga/minip4/ ~nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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nico@nsg-System:~/master-thesis/netpfga$
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nico@nsg-System:~/master-thesis/netpfga$ rm /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src
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nico@nsg-System:~/master-thesis/netpfga$ mkdir /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src
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nico@nsg-System:~/master-thesis/netpfga$ sudo mount --bind ~nico/master-thesis/p4src/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src
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#+END_CENTER
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likely this is the cause for the main error:
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+ ./tools/scripts/nf_test.py sim --major switch --minor default
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**** go through all steps again and try to understand why it (silently) fails later
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*** 2019-07-13: fix overflow error
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** The NetPFGA saga
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Problems encountered:
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- The logfile for a compile run is 10k+ lines
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- Many logged errors can actually be ignored (?) like:
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ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
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ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_DATA on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:219]
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ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_VALID on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:218]
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ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_DATA on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:185]
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ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_VALID on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:184]
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ERROR: [VRFC 10-2063] Module <S_RESETTER_line> not found while processing module instance <S_RESET_clk_line> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/Simp
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leSumeSwitch/SimpleSumeSwitch.v:332]
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ERROR: [VRFC 10-2063] Module <S_RESETTER_lookup> not found while processing module instance <S_RESET_clk_lookup> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/
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SimpleSumeSwitch/SimpleSumeSwitch.v:343]
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ERROR: [VRFC 10-2063] Module <S_RESETTER_control> not found while processing module instance <S_RESET_clk_control> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_i
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p/SimpleSumeSwitch/SimpleSumeSwitch.v:354]
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ERROR: [VRFC 10-2063] Module <TopParser_t> not found while processing module instance <TopParser> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitc
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h/SimpleSumeSwitch.v:436]
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ERROR: [VRFC 10-2063] Module <TopPipe_lvl_t> not found while processing module instance <TopPipe_lvl> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeS
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witch/SimpleSumeSwitch.v:474]
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ERROR: [VRFC 10-2063] Module <dummy_table_for_netpfga_t> not found while processing module instance <dummy_table_for_netpfga> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_s
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ume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:502]
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ERROR: [VRFC 10-2063] Module <TopPipe_lvl_0_t> not found while processing module instance <TopPipe_lvl_0> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleS
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umeSwitch/SimpleSumeSwitch.v:533]
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ERROR: [VRFC 10-2063] Module <TopDeparser_t> not found while processing module instance <TopDeparser> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeS
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witch/SimpleSumeSwitch.v:561]
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# launch_simulation -simset sim_1 -mode behavioral
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INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
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CRITICAL WARNING: [BD 41-1356] Address block </M04_AXI/Reg> is not mapped into </S00_AXI>. Please use Address Editor to either map or exclude it.
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CRITICAL WARNING: [BD 41-1356] Address block </M05_AXI/Reg> is not mapped into </S00_AXI>. Please use Address Editor to either map or exclude it.
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WARNING: [VRFC 10-756] identifier state is used before its declaration [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:93]
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WARNING: [VRFC 10-756] identifier ready_count is used before its declaration [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:94]
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INFO: [#UNDEF] Sorry, too many errors..
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ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
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INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
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INFO: [USF-XSim-99] Step results log file:'/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log'
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ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' file for more information.
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nico@nsg-System:~/master-thesis$ find . -name elaborate.log
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nico@nsg-System:~/master-thesis$ find ~ -name elaborate.log
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nico@nsg-System:~/master-thesis$
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- Scripts that "fail" (generate wrong data) do exit 0 ->
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There is no easy / reliable error detection
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- Writing tables resulted in ioctl errors
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- Hardware test: unclear if first board was/is broken or not,
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BUT: second board in different computer allows writing tables
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- Many scripts depend on each other in later stages, without clear
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dependencies
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- There is basically no documentation for someone who "just wants to
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compile from P4 to netpfga" or A LOT of documentation (if vivado,
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vhld, sdnet documentation is counted)
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- Very high complexity in toolchain, scripts that are generated
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default
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+ make
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rm -f config_writes.py*
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rm -f *.pyc
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nico@nsg-System:~$ cat /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py
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from NFTest import *
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NUM_WRITES = 4
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def config_tables():
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nftest_regwrite(0x44020050, 0x22222208)
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nftest_regwrite(0x44020054, 0x00000822)
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nftest_regwrite(0x44020080, 0x00000201)
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nftest_regwrite(0x44020040, 0x00000001)
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nico@nsg-System:~$ cat /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.sh
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#!/bin/bash
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${SUME_SDNET}/sw/sume/rwaxi -a 0x44020050 -w 0x22222208
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${SUME_SDNET}/sw/sume/rwaxi -a 0x44020054 -w 0x00000822
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${SUME_SDNET}/sw/sume/rwaxi -a 0x44020080 -w 0x00000201
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${SUME_SDNET}/sw/sume/rwaxi -a 0x44020040 -w 0x00000001
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nico@nsg-System:~$
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- Misleading errors like
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ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' file for more information.
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nico@nsg-System:~/master-thesis/netpfga$ ls /home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log
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ls: cannot access '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log': No such file or directory
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** References / Follow up
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*** RFC 791 IPv4 https://tools.ietf.org/html/rfc791
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*** RFC 792 ICMP https://tools.ietf.org/html/rfc792
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@ -106,33 +106,14 @@ def test_port1():
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pkt = Ether(dst=MAC2, src=MAC1)
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pkt = pad_pkt(pkt, 64)
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# Send on nf0
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pktCnt += 1
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applyPkt(pkt, 'nf0', pktCnt)
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for inport in [ 'nf0', 'nf1', 'nf2', 'nf3' ]:
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# Send on nf0
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applyPkt(pkt, inport, pktCnt)
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# Receive on nf0
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expPkt(pkt, 'nf0')
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# Always receive on nf0
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expPkt(pkt, 'nf0')
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# Send on nf1
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pktCnt += 1
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applyPkt(pkt, 'nf1', pktCnt)
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# Receive on nf0
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expPkt(pkt, 'nf0')
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# Send on nf2
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pktCnt += 1
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applyPkt(pkt, 'nf2', pktCnt)
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# Receive on nf0
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expPkt(pkt, 'nf0')
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# Send on nf3
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pktCnt += 1
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applyPkt(pkt, 'nf3', pktCnt)
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# Receive on nf0
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expPkt(pkt, 'nf0')
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pktCnt += 1
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# Test that packets are being mirrored
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def test_mirror():
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