+another compile failure
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+ date
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Die Jul 23 12:29:36 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
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minip4_solution.p4(59):syntax error, unexpected IDENTIFIER, expecting STATE
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digest_data
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^^^^^^^^^^^
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error: 1 errors encountered, aborting compilation
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Makefile:34: recipe for target 'all' failed
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make[1]: *** [all] Error 1
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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Makefile:31: recipe for target 'frontend' failed
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make: *** [frontend] Error 2
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+ date
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Die Jul 23 12:30:28 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
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minip4_solution.p4(59):syntax error, unexpected IDENTIFIER, expecting STATE
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digest_data
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^^^^^^^^^^^
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error: 1 errors encountered, aborting compilation
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Makefile:34: recipe for target 'all' failed
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make[1]: *** [all] Error 1
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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Makefile:31: recipe for target 'frontend' failed
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make: *** [frontend] Error 2
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+ date
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Die Jul 23 12:33:35 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
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headers.p4(86): error: Structure header ethernet_t does not have a field dstAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(78)
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EthAddr_t temp = hdr.ethernet.dstAddr;
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^^^^^^^
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headers.p4(86): error: Structure header ethernet_t does not have a field dstAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(79)
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hdr.ethernet.dstAddr = hdr.ethernet.srcAddr;
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^^^^^^^
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headers.p4(86): error: Structure header ethernet_t does not have a field srcAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(79)
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hdr.ethernet.dstAddr = hdr.ethernet.srcAddr;
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^^^^^^^
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headers.p4(86): error: Structure header ethernet_t does not have a field srcAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(80)
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hdr.ethernet.srcAddr = temp;
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^^^^^^^
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headers.p4(86): error: Structure header ethernet_t does not have a field dstAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(103)
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EthAddr_t temp = hdr.ethernet.dstAddr;
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^^^^^^^
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headers.p4(86): error: Structure header ethernet_t does not have a field dstAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(108)
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hdr.ethernet.dstAddr: exact;
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^^^^^^^
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Makefile:34: recipe for target 'all' failed
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make[1]: *** [all] Error 1
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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Makefile:31: recipe for target 'frontend' failed
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make: *** [frontend] Error 2
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Load Diff
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+ find -name '*.v' -o -name '*.vp' -o -name '*.sv'
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+ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv %
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_TopPipe_fl_temp
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_hdr_ethernet_dst_addr
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_hdr_ethernet_src_addr
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_sume_metadata_dst_port
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_control_increment_offset
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_nextSection
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INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_increment_offset
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work
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INFO: [VRFC 10-311] analyzing module xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module xpm_counter_updn
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
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INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
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INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
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INFO: [VRFC 10-311] analyzing module xpm_fifo_async
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INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work
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INFO: [VRFC 10-311] analyzing module xpm_memory_base
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INFO: [VRFC 10-311] analyzing module asym_bwe_bb
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INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
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INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
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INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
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INFO: [VRFC 10-311] analyzing module xpm_memory_spram
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INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
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INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work
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INFO: [VRFC 10-311] analyzing module xpm_cdc_single
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INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
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INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
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INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
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INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
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INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work
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INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser
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