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Nico Schottelius 2019-07-29 09:40:20 +02:00
parent ed4db31e2c
commit bbe78a44c1
2 changed files with 16 additions and 1 deletions
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15
doc/plan.org
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@ -8015,6 +8015,21 @@ reflashing switch
- ..hardcoded: sets to 4 (default) 16 (natted v4->v6) 64 (natted
v6->v4)
- ... dummy: 1 for arp, 1 for v4, 16 for v6
*** TODO 2019-07-29: fix precedence
#+BEGIN_CENTER
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
netpfga_dummy.p4(20): warning: >>: shifting value with 8 bits by 11
sume_metadata.dst_port = (bit<8>) hdr.ethernet.ethertype >> 11;
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
netpfga_dummy.p4(20): warning: >>: shifting value with 8 bits by 11
sume_metadata.dst_port = (bit<8>) hdr.ethernet.ethertype >> 11;
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
netpfga_dummy.p4(20): warning: >>: shifting value with 8 bits by 11
sume_metadata.dst_port = (bit<8>) hdr.ethernet.ethertype >> 11;
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
#+END_CENTER
** The NetPFGA saga
Problems encountered:
- The logfile for a compile run is 10k+ lines

2
p4src/netpfga_dummy.p4
View File

@ -17,7 +17,7 @@ action select_port_by_type() {
*/
sume_metadata.dst_port = (bit<8>) hdr.ethernet.ethertype >> 11;
sume_metadata.dst_port = (bit<8>) (hdr.ethernet.ethertype >> 11);
}