Browse Source

Only use v4_networks() and set default port to 4

master
Nico Schottelius 3 years ago
parent
commit
c3331bcea7
  1. 9
      bin/gen_v4_table_remove_entries.py
  2. 3
      bin/gen_v4_table_test_entries.py
  3. 142
      doc/plan.org
  4. 2
      p4src/actions_egress.p4
  5. 10
      p4src/minip4_solution.p4

9
bin/gen_v4_table_remove_entries.py

@ -0,0 +1,9 @@
#!/usr/bin/env python3
import ipaddress
for i in range(1,65):
addr = ipaddress.IPv4Address("10.0.0.{}".format(i))
ip_int = int(addr)
print("table_cam_delete_entry realmain_v4_networks_0 {}".format(ip_int))

3
bin/gen_v4_table_test_entries.py

@ -6,4 +6,5 @@ for i in range(1,65):
addr = ipaddress.IPv4Address("10.0.0.{}".format(i))
ip_int = int(addr)
print("table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port {} => 1 {} {} 0 0".format(ip_int, i, i))
# print("table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port {} => 1 {} {} 0 0".format(ip_int, i, i))
print("table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port {} => {} {} 0 0 0".format(ip_int, i, i))

142
doc/plan.org

@ -7267,8 +7267,7 @@ success
*** DONE 2019-07-28: ping6 test for getting packet: failure
CLOSED: [2019-07-28 Sun 12:43]
*** DONE 2019-07-28: !!!!!!! NETPFGA PORT MAPPINGS
CLOSED: [2019-07-28 Sun 13:07]
*** TODO 2019-07-28: !!!!!!! NETPFGA PORT MAPPINGS
nf_port_map = {
"nf0":0b00000001,
"nf1":0b00000100,
@ -7277,6 +7276,9 @@ nf_port_map = {
"dma0":0b00000010
}
- esprimo either nf0 & nf1
- or esprimo nf2 & nf3
| port 0 | 1 | eth1@ nsg ?! likely: esprimo enp2s0f0 | |
| port 1 | 4 | likely: esprimo enp2s0f1 | |
| port 2 | 16 | not connected likely | |
@ -7463,7 +7465,7 @@ success
#+END_CENTER
*** 2019-07-28: trying all ports with ipv4
*** TODO 2019-07-28: trying all ports with ipv4
#+BEGIN_CENTER
[16:26] line:bin% python3 gen_v4_table_test_entries.py
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772161 => 1 1 1 0 0
@ -7533,7 +7535,105 @@ table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772224 =>
#+END_CENTER
*** 2019-07-28: reprogramming fpga fails
adding ip again:
#+BEGIN_CENTER
nico@ESPRIMO-P956:~/master-thesis/pcap$ sudo ip addr add 10.0.0.200/24 dev enp2s0f0
#+END_CENTER
Using
#+BEGIN_CENTER
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772161 => 1 1 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772162 => 2 2 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772163 => 3 3 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772164 => 4 4 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772165 => 5 5 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772166 => 6 6 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772167 => 7 7 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772168 => 8 8 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772169 => 9 9 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772170 => 10 10 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772171 => 11 11 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772172 => 12 12 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772173 => 13 13 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772174 => 14 14 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772175 => 15 15 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772176 => 16 16 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772177 => 17 17 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772178 => 18 18 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772179 => 19 19 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772180 => 20 20 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772181 => 21 21 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772182 => 22 22 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772183 => 23 23 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772184 => 24 24 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772185 => 25 25 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772186 => 26 26 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772187 => 27 27 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772188 => 28 28 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772189 => 29 29 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772190 => 30 30 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772191 => 31 31 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772192 => 32 32 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772193 => 33 33 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772194 => 34 34 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772195 => 35 35 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772196 => 36 36 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772197 => 37 37 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772198 => 38 38 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772199 => 39 39 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772200 => 40 40 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772201 => 41 41 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772202 => 42 42 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772203 => 43 43 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772204 => 44 44 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772205 => 45 45 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772206 => 46 46 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772207 => 47 47 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772208 => 48 48 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772209 => 49 49 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772210 => 50 50 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772211 => 51 51 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772212 => 52 52 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772213 => 53 53 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772214 => 54 54 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772215 => 55 55 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772216 => 56 56 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772217 => 57 57 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772218 => 58 58 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772219 => 59 59 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772220 => 60 60 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772221 => 61 61 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772222 => 62 62 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772223 => 63 63 0 0 0
table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 167772224 => 64 64 0 0 0
#+END_CENTER
also does not work/add packets
*** TODO 2019-07-28: Bit / byte order issues?
#+BEGIN_CENTER
>> table_cam_add_entry realmain_v4_networks_0 realmain.set_egress_port 16777226 => 1 1 1 0 0
fields = [(u'hit', 1), (u'action_run', 3), (u'out_port', 8), (u'out_port', 8), (u'mac_addr', 48), (u'task', 16), (u'table_id', 16)]
action_name = TopPipe.realmain.set_egress_port
field_vals = [1, '1', '1', '1', '0', '0']
CAM_Init_ValidateContext() - done
WROTE 0x44020050 = 0x100000a
WROTE 0x44020080 = 0x0000
WROTE 0x44020084 = 0x0001
WROTE 0x44020088 = 0x1010000
WROTE 0x4402008c = 0x0001
READ 0x44020044 = 0x0001
WROTE 0x44020040 = 0x0001
READ 0x44020044 = 0x0001
READ 0x44020044 = 0x0001
success
>>
#+END_CENTER
*** DONE 2019-07-28: reprogramming fpga fails
CLOSED: [2019-07-28 Sun 16:30]
#+BEGIN_CENTER
INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application
@ -7613,6 +7713,40 @@ nf3: ERROR while getting interface flags: No such device
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles$
#+END_CENTER
*** DONE 2019-07-28: nf* interfaces gone: rebooting, reload module helps
CLOSED: [2019-07-28 Sun 16:31]
#+BEGIN_CENTER
make[1]: Leaving directory '/usr/src/linux-headers-4.15.0-55-generic'
install -o root -g root -m 0755 -d /lib/modules/4.15.0-55-generic/extra/sume_riffa/
install -o root -g root -m 0755 sume_riffa.ko /lib/modules/4.15.0-55-generic/extra/sume_riffa/
depmod -a 4.15.0-55-generic
+ sudo modprobe sume_riffa
+ + grep sume_riffa
lsmod
sume_riffa 28672 0
nico@nsg-System:~$ ip l
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast state UP mode DEFAULT group default qlen 1000
link/ether 74:d0:2b:98:38:f6 brd ff:ff:ff:ff:ff:ff
3: eth1: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether f8:f2:1e:41:44:9c brd ff:ff:ff:ff:ff:ff
4: eth2: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether f8:f2:1e:41:44:9d brd ff:ff:ff:ff:ff:ff
5: wg0: <POINTOPOINT,NOARP,UP,LOWER_UP> mtu 1420 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
link/none
6: nf0: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether 02:53:55:4d:45:00 brd ff:ff:ff:ff:ff:ff
7: nf1: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether 02:53:55:4d:45:01 brd ff:ff:ff:ff:ff:ff
8: nf2: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether 02:53:55:4d:45:02 brd ff:ff:ff:ff:ff:ff
9: nf3: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether 02:53:55:4d:45:03 brd ff:ff:ff:ff:ff:ff
nico@nsg-System:~$
#+END_CENTER
** The NetPFGA saga

2
p4src/actions_egress.p4

@ -31,7 +31,7 @@ action controller_reply(task_t task) {
action controller_reply(task_t task) {
meta.task = task;
meta.ingress_port = sume_metadata.src_port;
set_egress_port(1);
set_egress_port(4);
}
#endif /* _SUME_SWITCH_P4_ */

10
p4src/minip4_solution.p4

@ -65,13 +65,13 @@ control RealMain(
// #include "netpfga_nat64.p4"
if(apply_v4networks == true) {
// if(apply_v4networks == true) {
v4_networks.apply();
}
// }
if(apply_v6networks == true) {
v6_networks.apply();
}
// if(apply_v6networks == true) {
// v6_networks.apply();
// }
}
}

Loading…
Cancel
Save