Merge branch 'master' of gitlab.ethz.ch:nicosc/master-thesis
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netpfga/log/compile-2019-07-28-165712
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netpfga/log/compile-2019-07-28-165712
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netpfga/log/compile-2019-07-28-165815
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netpfga/log/compile-2019-07-28-165815
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netpfga/log/compile-2019-07-28-201511-7.0-no-tables-static-nat64
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netpfga/log/compile-2019-07-28-201511-7.0-no-tables-static-nat64
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netpfga/log/compile-2019-07-29-020109-7.0-switch-to-16
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netpfga/log/compile-2019-07-29-020109-7.0-switch-to-16
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netpfga/log/compile-2019-07-29-093804
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netpfga/log/compile-2019-07-29-093804
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netpfga/log/compile-2019-07-29-093902-7.1-ethertype
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netpfga/log/compile-2019-07-29-093902-7.1-ethertype
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@ -0,0 +1,64 @@
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+ date
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Mon Jul 29 09:39:02 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
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netpfga_dummy.p4(20): warning: >>: shifting value with 8 bits by 11
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sume_metadata.dst_port = (bit<8>) hdr.ethernet.ethertype >> 11;
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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netpfga_dummy.p4(20): warning: >>: shifting value with 8 bits by 11
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sume_metadata.dst_port = (bit<8>) hdr.ethernet.ethertype >> 11;
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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netpfga_dummy.p4(20): warning: >>: shifting value with 8 bits by 11
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sume_metadata.dst_port = (bit<8>) hdr.ethernet.ethertype >> 11;
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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actions_egress.p4(51): warning: Table v6_networks is not used; removing
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table v6_networks {
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^^^^^^^^^^^
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actions_egress.p4(77): warning: Table v4_networks is not used; removing
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table v4_networks {
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^^^^^^^^^^^
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actions_nat64_generic.p4(159): warning: Table nat64 is not used; removing
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table nat64 {
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^^^^^
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actions_nat64_generic.p4(177): warning: Table nat46 is not used; removing
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table nat46 {
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^^^^^
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minip4_solution.p4(19): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates
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out metadata meta,
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^^^^
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minip4_solution.p4(16)
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parser RealParser(
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^^^^^^^^^^
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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./gen_testdata.py
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Applying pkt on nf0 at 1:
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Applying pkt on nf1 at 2:
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Applying pkt on nf2 at 3:
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Applying pkt on nf3 at 4:
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nf0_applied times: [1]
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nf1_applied times: [2]
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nf2_applied times: [3]
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nf3_applied times: [4]
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
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Xilinx SDNet Compiler version 2018.2, build 2342300
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netpfga/log/compile-2019-07-29-094034-7.1-ethertype
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netpfga/log/compile-2019-07-29-094034-7.1-ethertype
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