+doc +log +allports

doc/plan.org

@@ -310,6 +310,8 @@
 |            | - Not Receiving                                                            |       |
 |            | - Output all ports -> unclear how test data should look like               |       |
 |            | - Found out broad/multicasting in theory -> bitmask                        |       |
+|            | - Theory: code is not persistent in flash (???) -> not there after power   |       |
+|            |   down                                                                     |       |
 |            |                                                                            |       |
 | 2018-06-27 |                                                                            |       |
 |            | Target Hardware: code running                                              |       |
@@ -4019,7 +4021,6 @@ python: ioctl: Unknown error 512
 
 #+END_CENTER
 
-
 *** 2019-06-10: testing with INT (hint from Hendrik)
 **** 15:54 compile & upload done
 **** 16:36 ...testing
@@ -4094,6 +4095,79 @@ mapping
 Test data in gen_testdata.py expects order. If we output to 0b1010101
 (=85), then the packet should arrive on all ports. Order unknown.
 
+*** 2019-06-11: rebooted -> card is missing from lspci
+reprogramming. why is it missing?
+
+#+BEGIN_CENTER
+[18:25] rainbow:bitfiles% sudo bash -c ". $HOME/master-thesis/netpfga/bashinit && $(pwd -P)/program_switch.sh"
+++ which vivado
++ xilinx_tool_path=/opt/Xilinx/Vivado/2018.2/bin/vivado
++ bitimage=int.bit
++ configWrites=config_writes.sh
++ '[' -z int.bit ']'
++ '[' -z config_writes.sh ']'
++ '[' /opt/Xilinx/Vivado/2018.2/bin/vivado == '' ']'
++ rmmod sume_riffa
+rmmod: ERROR: Module sume_riffa is not currently loaded
++ xsct /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl -tclargs int.bit
+rlwrap: warning: your $TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems.
+RUN loading image file.
+int.bit
+attempting to launch hw_server
+
+****** Xilinx hw_server v2018.2
+  **** Build date : Jun 14 2018-20:18:37
+    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+
+INFO: hw_server application started
+INFO: Use Ctrl-C to exit hw_server application
+
+INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121
+
+100%   13MB   1.7MB/s  00:08
+
++ bash /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/pci_rescan_run.sh
+Check programming FPGA or Reboot machine !
++ rmmod sume_riffa
+rmmod: ERROR: Module sume_riffa is not currently loaded
++ modprobe sume_riffa
++ ifconfig nf0 up
+nf0: ERROR while getting interface flags: No such device
++ ifconfig nf1 up
+nf1: ERROR while getting interface flags: No such device
++ ifconfig nf2 up
+nf2: ERROR while getting interface flags: No such device
++ ifconfig nf3 up
+nf3: ERROR while getting interface flags: No such device
++ bash config_writes.sh
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+rwaxi: ioctl: No such device
+
+#+END_CENTER
+
+After reprogram AND reboot:
+
+10:00.0 Memory controller: Xilinx Corporation Device 7028
+
+
 ** References / Follow up
 *** RFC 791 IPv4 https://tools.ietf.org/html/rfc791
 *** RFC 792 ICMP https://tools.ietf.org/html/rfc792

netpfga/build-load-drivers.sh

@@ -4,6 +4,8 @@ set -e
 set -x
 
 cd "$DRIVER_FOLDER"
+# remove old/bad version
+sudo modprobe -r sume_riffa || true
 make clean
 make all
 sudo make install

netpfga/do-all-steps.sh

@@ -53,4 +53,6 @@ cp $P4_PROJECT_DIR/testdata/config_writes.sh ./
 
 # Step 13:
 cd $NF_DESIGN_DIR/bitfiles/
+# some scripts are, some scripts aren't executable...
+chmod u+x $(pwd -P)/program_switch.sh
 sudo bash -c ". $HOME/master-thesis/netpfga/bashinit && $(pwd -P)/program_switch.sh"

netpfga/minip4/src/minip4_solution.p4

@@ -69,6 +69,18 @@ control TopPipe(inout Parsed_packet p,
         sume_metadata.dst_port = 1;
     }
 
+    action send_to_all_ports() {
+        /* Taken from commands.txt of the "int" project:
+        table_cam_add_entry forward set_output_port 0xffffffffffff => 0b01010101
+
+        python convert:
+        >>> 0b01010101
+        85
+
+        */
+        sume_metadata.dst_port = 85;
+    }
+
     action do_nothing() {
         EthAddr_t temp = p.ethernet.dstAddr;
     }
@@ -82,10 +94,12 @@ control TopPipe(inout Parsed_packet p,
             swap_eth_addresses;
             do_nothing;
             send_to_port1;
+            send_to_all_ports;
         }
         size = 64;
 //        default_action = swap_eth_addresses;
-        default_action = send_to_port1;
+//        default_action = send_to_port1;
+        default_action = send_to_all_ports;
     }
 
     apply {

netpfga/minip4/sw/hw_test_tool/switch_calc_tester.py

@@ -4,10 +4,10 @@
 # Copyright (c) 2017 Stephen Ibanez
 # All rights reserved.
 #
-# This software was developed by Stanford University and the University of Cambridge Computer Laboratory 
+# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
 # under National Science Foundation under Grant No. CNS-0855268,
 # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
-# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 
+# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
 # as part of the DARPA MRC research programme.
 #
 # @NETFPGA_LICENSE_HEADER_START@
@@ -38,7 +38,7 @@ from switch_calc_headers import *
 from nf_sim_tools import *
 
 PKT_SIZE = 64
-IFACE = "eth1"
+IFACE = "nf0"
 
 ETH_SRC = "08:11:11:11:11:08"
 ETH_DST = "08:22:22:22:22:08"
@@ -57,7 +57,7 @@ class SwitchCalcTester(cmd.Cmd):
     intro = "The HW testing tool for the switch_calc design\n type help to see all commands"
 
     def _to_int(self, op):
-        try: 
+        try:
             val = int(op, 0)
             assert(val >= 0)
             return val
@@ -105,7 +105,7 @@ class SwitchCalcTester(cmd.Cmd):
         return pkt
 
     def do_run_test(self, line):
-        pkt = self._parse_line(line) 
+        pkt = self._parse_line(line)
         self._submit_pkt(pkt)
 
     def help_run_test(self):
@@ -113,9 +113,9 @@ class SwitchCalcTester(cmd.Cmd):
 run_test <op1> <operation> <op2>
 DESCRIPTION: Create a single test packet to test the functionality of the switch_calc implementation
 NOTES:
-    <operation> : must be one of the following [ADD, +, SUB, -, LOOKUP, ADD_REG, SET_REG] 
+    <operation> : must be one of the following [ADD, +, SUB, -, LOOKUP, ADD_REG, SET_REG]
     LOOKUP : <op1> = the key to lookup, <op2> = unused
-    ADD_REG / SET_REG : <op1> = register index, <op2> = value 
+    ADD_REG / SET_REG : <op1> = register index, <op2> = value
 """
 
     def do_exit(self, line):

netpfga/minip4/testdata/gen_testdata.py

@@ -84,8 +84,12 @@ def write_pcap_files():
 # generate testdata #
 #####################
 
-MAC1 = "08:11:11:11:11:08"
+MACSRC = "08:11:11:11:11:08"
-MAC2 = "08:22:22:22:22:08"
+MAC0 = "08:22:22:22:22:00"
+#MAC1 = "08:22:22:22:22:01"
+#MAC2 = "08:22:22:22:22:02"
+#MAC3 = "08:22:22:22:22:03"
+
 pktCnt = 0
 
 INDEX_WIDTH = 4
@@ -110,15 +114,44 @@ def test_port1():
     applyPkt(pkt, 'nf0', pktCnt)
     expPkt(pkt,   'nf0')
 
+def test_allports():
+    pktCnt = 0
+
+    # First ethernet
+    pkt = Ether(dst=MAC2, src=MAC1)
+    pkt = pad_pkt(pkt, 64)
+
+    pktCnt += 1
+    applyPkt(pkt, 'nf1', pktCnt)
+    expPkt(pkt,   'nf0')
+    expPkt(pkt,   'nf1')
+    expPkt(pkt,   'nf2')
+    expPkt(pkt,   'nf3')
+
+    pktCnt += 1
+    applyPkt(pkt, 'nf2', pktCnt)
+    expPkt(pkt,   'nf0')
+    expPkt(pkt,   'nf1')
+    expPkt(pkt,   'nf2')
+    expPkt(pkt,   'nf3')
+
+    pktCnt += 1
+    applyPkt(pkt, 'nf3', pktCnt)
+    expPkt(pkt,   'nf0')
+    expPkt(pkt,   'nf1')
+    expPkt(pkt,   'nf2')
+    expPkt(pkt,   'nf3')
+
 # Test that packets are being mirrored
 def test_mirror():
     pktCnt = 0
 
-    # First ethernet
+    # inject into nf1,2,3
+
     pktCnt += 1
     pkt = Ether(dst=MAC2, src=MAC1)
     pkt = pad_pkt(pkt, 64)
-    applyPkt(pkt, 'nf0', pktCnt)
+    applyPkt(pkt, 'nf1', pktCnt)
 
     pktCnt += 1
     pkt = Ether(dst=MAC1, src=MAC2)
@@ -146,6 +179,7 @@ def test_mirror():
     # expPkt(pkt, 'nf0')
 
 #test_mirror()
-test_port1()
+#test_port1()
+test_all_ports()
 
 write_pcap_files()