199 lines
6.9 KiB
Verilog
199 lines
6.9 KiB
Verilog
//-
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// Copyright (c) 2015 Noa Zilberman
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// All rights reserved.
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//
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// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
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// under National Science Foundation under Grant No. CNS-0855268,
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// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
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// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
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// as part of the DARPA MRC research programme.
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//
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// File:
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// top_tb.v
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//
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// Module:
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// top
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//
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// Author: Noa Zilberman
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//
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// Description:
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// reference nic top module
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//
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// @NETFPGA_LICENSE_HEADER_START@
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//
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// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
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// license agreements. See the NOTICE file distributed with this work for
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// additional information regarding copyright ownership. NetFPGA licenses this
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// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
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// "License"); you may not use this file except in compliance with the
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// License. You may obtain a copy of the License at:
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//
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// http://www.netfpga-cic.org
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//
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// Unless required by applicable law or agreed to in writing, Work distributed
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// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// @NETFPGA_LICENSE_HEADER_END@
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//
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`timescale 1ns / 100ps
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module top_tb # (
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parameter PL_SIM_FAST_LINK_TRAINING = "TRUE", // Simulation Speedup
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parameter C_DATA_WIDTH = 256, // RX/TX interface data width
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parameter KEEP_WIDTH = C_DATA_WIDTH / 32,
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parameter integer USER_CLK2_FREQ = 4,
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parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
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parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE",
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parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE",
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parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE",
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parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE",
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parameter AXISTEN_IF_ENABLE_CLIENT_TAG = 0,
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parameter AXISTEN_IF_RQ_PARITY_CHECK = 0,
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parameter AXISTEN_IF_CC_PARITY_CHECK = 0,
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parameter AXISTEN_IF_MC_RX_STRADDLE = 0,
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parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = 0,
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parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h2FFFF
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) (
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);
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parameter PCIE_PERIOD = 10;
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parameter XPHY_PERIOD = 6.4;
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parameter CORE_PERIOD = 4;
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localparam TCQ = 1;
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localparam BAR0AXI = 32'h40000000;
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localparam BAR1AXI = 32'h10000000;
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localparam BAR2AXI = 32'h20000000;
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localparam BAR3AXI = 32'h30000000;
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localparam BAR4AXI = 32'h40000000;
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localparam BAR5AXI = 32'h50000000;
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localparam BAR0SIZE = 64'hFFFF_FFFF_FFFF_FF80;
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localparam BAR1SIZE = 64'hFFFF_FFFF_FFFF_FF80;
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localparam BAR2SIZE = 64'hFFFF_FFFF_FFFF_FF80;
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localparam BAR3SIZE = 64'hFFFF_FFFF_FFFF_FF80;
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localparam BAR4SIZE = 64'hFFFF_FFFF_FFFF_FF80;
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localparam BAR5SIZE = 64'hFFFF_FFFF_FFFF_FF80;
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localparam throttle_percent = 50;
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reg sys_reset_n;
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reg sys_clk;
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wire sys_clkp,sys_clkn;
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reg xphy_clk;
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wire xphy_refclk_p,xphy_refclk_n;
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reg clk_ref;
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wire clk_ref_p,clk_ref_n;
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//----------------------------------------------------------------------------------------------------------------//
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// axis interface //
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//----------------------------------------------------------------------------------------------------------------//
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top_sim # (
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.PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING ),
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.C_DATA_WIDTH (C_DATA_WIDTH ),
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.KEEP_WIDTH (KEEP_WIDTH ),
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.USER_CLK2_FREQ (USER_CLK2_FREQ ),
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.REF_CLK_FREQ (REF_CLK_FREQ ),
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.AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE ),
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.AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE ),
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.AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE ),
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.AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE ),
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.AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG ),
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.AXISTEN_IF_RQ_PARITY_CHECK (AXISTEN_IF_RQ_PARITY_CHECK ),
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.AXISTEN_IF_CC_PARITY_CHECK (AXISTEN_IF_CC_PARITY_CHECK ),
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.AXISTEN_IF_MC_RX_STRADDLE (AXISTEN_IF_MC_RX_STRADDLE ),
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.AXISTEN_IF_ENABLE_RX_MSG_INTFC (AXISTEN_IF_ENABLE_RX_MSG_INTFC ),
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.AXISTEN_IF_ENABLE_MSG_ROUTE (AXISTEN_IF_ENABLE_MSG_ROUTE )
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) top_sim (
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//PCI Express
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.pcie_7x_mgt_rxn(pcie_7x_mgt_rxn),
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.pcie_7x_mgt_rxp(pcie_7x_mgt_rxp),
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.pcie_7x_mgt_txn(pcie_7x_mgt_txn),
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.pcie_7x_mgt_txp(pcie_7x_mgt_txp),
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//10G Interface
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.sfp0_rx_p(rxp),
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.sfp0_rx_n(rxn),
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.sfp0_tx_p(txp),
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.sfp0_tx_n(txn),
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// PCIe Clock
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.sys_clkp(sys_clkp),
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.sys_clkn(sys_clkn),
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//200MHz Clock
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.fpga_sysclk_p(clk_ref_p),
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.fpga_sysclk_n(clk_ref_n),
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//-SI5324 I2C programming interface
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.i2c_clk (i2c_clk),
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.i2c_data (i2c_data),
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.i2c_reset(si5324_rst_n),
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// 156.25 MHz clock in
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.xphy_refclk_p (xphy_refclk_p),
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.xphy_refclk_n (xphy_refclk_n),
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.led_0(led_0),
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.led_1(led_1),
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.sys_reset_n(sys_reset_n)
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);
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//Reset handling
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// Important! polarity here is opposite the one in the actual design
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initial begin
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sys_reset_n = 1'b0;
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#(CORE_PERIOD * 200);
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sys_reset_n = 1'b1;
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$display("Reset Deasserted");
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end
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//Clock generation
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initial begin
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sys_clk = 1'b0;
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#(PCIE_PERIOD/2);
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forever
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#(PCIE_PERIOD/2) sys_clk = ~sys_clk;
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end
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assign sys_clkp = sys_clk;
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assign sys_clkn = ~sys_clk;
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initial begin
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xphy_clk = 1'b0;
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#(XPHY_PERIOD/2);
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forever
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#(XPHY_PERIOD/2) xphy_clk = ~xphy_clk;
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end
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assign xphy_refclk_p = xphy_clk;
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assign xphy_refclk_n = ~xphy_clk;
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initial begin
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clk_ref = 1'b0;
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#(CORE_PERIOD/2);
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forever
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#(CORE_PERIOD/2) clk_ref = ~clk_ref;
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end
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assign clk_ref_p = clk_ref;
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assign clk_ref_n = ~clk_ref;
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endmodule
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