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27 lines
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+ date
Mit Jul 24 09:50:24 CEST 2019
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
+ make
make -C src/ clean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
make -C testdata/ clean
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
rm -rf nf_sume_sdnet_ip/
rm -f ./nf_sume_sdnet_ip/SimpleSumeSwitch/xelab.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xvlog.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsc.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_28815.backup.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimcrash.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimkernel.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_28815.backup.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.jou ./simple_sume_switch/hw/vivado.log ./simple_sume_switch/hw/vivado.jou ./simple_sume_switch/hw/vivado_29846.backup.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_auto_cc_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_auto_cc_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_mdm_1_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_mdm_1_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m03_data_fifo_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m03_data_fifo_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m01_data_fifo_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m01_data_fifo_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m07_data_fifo_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m07_data_fifo_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_rx_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_rx_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m08_data_fifo_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m08_data_fifo_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/synth/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_clk_wiz_1_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_clk_wiz_1_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_bram_if_cntlr_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_bram_if_cntlr_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_s00_data_fifo_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_s00_data_fifo_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m06_data_fifo_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m06_data_fifo_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_clock_converter_0_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_clock_converter_0_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_tx_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_tx_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie_reset_inv_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie_reset_inv_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_v10_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_dlmb_v10_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie3_7x_1_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_pcie3_7x_1_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_nf_riffa_dma_1_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_nf_riffa_dma_1_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_xlconcat_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_xlconcat_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_lmb_bram_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_lmb_bram_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_rx_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_fifo_10g_rx_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m00_data_fifo_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m00_data_fifo_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_v10_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_v10_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_tx_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axis_dwidth_dma_tx_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_uartlite_0_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_uartlite_0_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m05_data_fifo_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m05_data_fifo_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_rst_clk_wiz_1_100M_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_rst_clk_wiz_1_100M_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_iic_0_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_axi_iic_0_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_bram_if_cntlr_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_ilmb_bram_if_cntlr_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_1_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_xbar_1_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_axi_intc_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_microblaze_0_axi_intc_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m04_data_fifo_0_synth_1/vivado.jou ./simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m04_data_fifo_0_synth_1/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/identifier_ip/summary.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/7bfef02244461664.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/bb89f09b44165778.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/efe6e3d49c3a8039.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/7c0f5c85c14564bf.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/3e60498069fd8bd5.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/74db4bf3f7578076.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/729c75d02cfc530d.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/f84a275938957408.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/bbbd46440b5c7213.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/3b530f2d27ae946b.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/37ac3cdf312077f7.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/9783353c4ff76f6c.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/b97cfdfeee8f8d17.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/12896bd3f3d414eb.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/a767e4aa25ef8a2e.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/a355d5924fa4a281.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/66c48b9feb81b863.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/b534406ce6538971.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/9c58bca45284afc8.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/21dbb55d3f7b1967.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/0c40fc07b96d1658.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/9b8a1c9dada027fa.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/9278bfe6c99dbe18.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/cd1648cfd505e41d.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/bcb85672e1d51456.logs/runme.log ./simple_sume_switch/hw/project/simple_sume_switch.cache/ip/2018.2/cc4a2809a8a54e43.logs/runme.log ./simple_sume_switch/hw/vivado_29846.backup.log ./simple_sume_switch/hw/ip_repo/std/cores/output_queues_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/output_queues_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/nf_10ge_interface_shared_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/nf_10ge_interface_shared_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/nf_10ge_interface_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/nf_10ge_interface_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/axi_sim_transactor_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/axi_sim_transactor_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/axis_sim_record_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/axis_sim_record_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/fallthrough_small_fifo_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/fallthrough_small_fifo_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/barrier_gluelogic_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/barrier_gluelogic_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/axis_sim_stim_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/axis_sim_stim_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/input_arbiter_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/input_arbiter_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/identifier_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/identifier_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/barrier_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/barrier_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/nf_axis_converter_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/nf_axis_converter_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/nf_riffa_dma_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/nf_riffa_dma_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/std/cores/axis_fifo_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/std/cores/axis_fifo_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/vivado.log ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/vivado.jou ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/xelab.log ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/xvlog.log ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.jou ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/xsc.log ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_28815.backup.log ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.log ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimcrash.log ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimkernel.log ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_28815.backup.jou ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.log ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.jou ./simple_sume_switch/hw/ip_repo/contrib/cores/input_arbiter_drr_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/contrib/cores/input_arbiter_drr_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/contrib/cores/sss_fallthrough_small_fifo_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/contrib/cores/sss_fallthrough_small_fifo_v1_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/contrib/cores/sss_output_queues_v2_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/contrib/cores/sss_output_queues_v2_0_0/vivado.jou ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_endianess_manager_v1_0_0/vivado.log ./simple_sume_switch/hw/ip_repo/contrib/cores/nf_endianess_manager_v1_0_0/vivado.jou
rm -f sw/config_tables.c
make -C src/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
minip4_solution.p4(36):syntax error, unexpected INOUT, expecting CONST or STATE
inout
^^^^^
error: 1 errors encountered, aborting compilation
Makefile:34: recipe for target 'all' failed
make[1]: *** [all] Error 1
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
Makefile:31: recipe for target 'frontend' failed
make: *** [frontend] Error 2