master-thesis/p4src/minip4_solution.p4
2019-07-23 16:10:28 +02:00

276 lines
7.8 KiB
Text

#include <core.p4>
#include <sume_switch.p4>
#include "headers.p4"
/********************************************************************************
* Features
*/
// #define ENABLE_CONTROLLER 1
/********************************************************************************
* Header
*/
typedef bit<48> EthAddr_t;
header Ethernet_h {
EthAddr_t dstAddr;
EthAddr_t srcAddr;
bit<16> etherType;
}
struct Parsed_packet {
Ethernet_h ethernet;
}
// user defined metadata: can be used to share information between
// TopParser, TopPipe, and TopDeparser
struct user_metadata_t {
bit<8> unused;
}
// digest_data, MUST be 256 bits -- what is this used for?
struct digest_data_t {
bit<256> unused;
}
/********************************************************************************
* Parser
*/
// @Xilinx_MaxPacketRegion(1024)
// parser TopParser(packet_in b,
// out Parsed_packet p,
// out user_metadata_t user_metadata,
// out digest_data_t digest_data,
// inout sume_metadata_t sume_metadata) {
// }
@Xilinx_MaxPacketRegion(1024)
parser TopParser(packet_in packet,
out headers hdr,
// out metadata meta,
out user_metadata_t user_metadata,
out digest_data_t digest_data,
inout sume_metadata_t standard_metadata) {
state start {
packet.extract(hdr.ethernet);
user_metadata.unused = 0;
digest_data.unused = 0;
transition accept;
}
// #include "parsers.p4"
}
/********************************************************************************
* Main
*/
// control TopPipe(inout Parsed_packet p,
// inout digest_data_t digest_data,
// inout sume_metadata_t sume_metadata) {
control TopPipe(inout headers hdr,
//inout metadata meta,
inout user_metadata_t user_metadata,
inout digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
// actions to be enabled
// #include "actions_nat64_generic.p4" // includes controller & delta checksum
// #include "actions_egress.p4" // includes v6_networks, v4_networks
// #include "actions_icmp6_ndp_icmp.p4" // includes icmp6 table, triggers payload checksum!
// #include "actions_arp.p4" // includes v4_arp, v4_egress
// #include "actions_delta_checksum.p4" // non payload based checksumming
// apply {
// if(hdr.ipv6.isValid()) {
// if(nat64.apply().hit) { /* generic / static nat64 done */
// if(hdr.icmp6.isValid()) {
// nat64_icmp6_generic();
// if(hdr.icmp6.type == ICMP6_ECHO_REPLY) {
// hdr.icmp.type = ICMP_ECHO_REPLY;
// hdr.icmp.code = 0;
// }
// if(hdr.icmp6.type == ICMP6_ECHO_REQUEST) {
// hdr.icmp.type = ICMP_ECHO_REQUEST;
// hdr.icmp.code = 0;
// }
// }
// if(hdr.udp.isValid()) {
// #ifdef USE_NICO_DELTA_CHECKSUM
// delta_udp_from_v6_to_v4();
// #else
// meta.chk_udp_v4 = 1;
// #endif
// }
// if(hdr.tcp.isValid()) {
// #ifdef USE_NICO_DELTA_CHECKSUM
// delta_tcp_from_v6_to_v4();
// #else
// meta.chk_tcp_v4 = 1;
// #endif
// }
// v4_networks.apply(); /* apply egress for IPv4 */
// exit; /* no further v6 processing */
// }
// icmp6.apply(); /* icmp6 echo, icmp6 ndp */
// v6_networks.apply(); /* regular egress / routing */
// } else if(hdr.ipv4.isValid()) {
// if(icmp.apply().hit) {
// v4_networks.apply();
// exit;
// } else if(nat46.apply().hit) {
// if(hdr.icmp.isValid()) {
// nat46_icmp_generic();
// if(hdr.icmp.type == ICMP_ECHO_REPLY) {
// hdr.icmp6.type = ICMP6_ECHO_REPLY;
// }
// if(hdr.icmp.type == ICMP_ECHO_REQUEST) {
// hdr.icmp6.type = ICMP6_ECHO_REQUEST;
// }
// }
// if(hdr.udp.isValid()) {
// #ifdef USE_NICO_DELTA_CHECKSUM
// delta_udp_from_v4_to_v6();
// #else
// meta.chk_udp_v6 = 1;
// #endif
// }
// if(hdr.tcp.isValid()) {
// #ifdef USE_NICO_DELTA_CHECKSUM
// delta_tcp_from_v4_to_v6();
// #else
// meta.chk_tcp_v6 = 1;
// #endif
// }
// v6_networks.apply();
// exit;
// }
// v4_networks.apply(); /* regular routing, egress */
// } else if(hdr.arp.isValid()) {
// if(v4_arp.apply().hit) {
// v4_arp_egress.apply();
// }
// }
// }
action swap_eth_addresses() {
EthAddr_t temp = hdr.ethernet.dst_addr;
hdr.ethernet.dst_addr = hdr.ethernet.src_addr;
hdr.ethernet.src_addr = temp;
/* set egress port */
sume_metadata.dst_port = sume_metadata.src_port;
}
action send_to_port1() {
sume_metadata.dst_port = 1;
}
// action send_testdata_to_port1() {
// // python: MAC2 = "08:22:22:22:22:08"
// if(hdr.ethernet.dst_addr == 0x082222222208) {
// sume_metadata.dst_port = 1;
// }
// }
action send_to_all_ports() {
/* Taken from commands.txt of the "int" project:
table_cam_add_entry forward set_output_port 0xffffffffffff => 0b01010101
python convert:
>>> 0b01010101
85
*/
sume_metadata.dst_port = 85;
}
action do_nothing() {
EthAddr_t temp = hdr.ethernet.dst_addr;
}
#ifdef ENABLE_CONTROLLER
#include "actions_controller.p4"
#endif
table lookup_table {
key = {
hdr.ethernet.dst_addr: exact;
}
actions = {
#ifdef ENABLE_CONTROLLER
controller_debug;
#endif
swap_eth_addresses;
do_nothing;
send_to_port1;
send_to_all_ports;
}
size = 64;
// default_action = swap_eth_addresses; // test_mirror(): in gen_testdata.py
default_action = send_to_port1; // test_port1()
// default_action = send_to_all_ports; // test_allports():
}
apply {
lookup_table.apply();
}
}
/********************************************************************************
* Deparser
*/
@Xilinx_MaxPacketRegion(1024)
control TopDeparser(packet_out packet,
in headers hdr,
in user_metadata_t user_metadata,
// in metadata meta,
inout digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
// @Xilinx_MaxPacketRegion(1024)
// control TopDeparser(packet_out b,
// in Parsed_packet p,
// inout digest_data_t digest_data,
// inout sume_metadata_t sume_metadata) {
apply {
packet.emit(hdr.ethernet);
}
// #include "deparser.p4"
}
/********************************************************************************
* Switch
*/
SimpleSumeSwitch(
TopParser(),
TopPipe(),
TopDeparser()
) main;