276 lines
7.8 KiB
Text
276 lines
7.8 KiB
Text
#include <core.p4>
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#include <sume_switch.p4>
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#include "headers.p4"
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/********************************************************************************
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* Features
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*/
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// #define ENABLE_CONTROLLER 1
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/********************************************************************************
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* Header
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*/
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typedef bit<48> EthAddr_t;
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header Ethernet_h {
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EthAddr_t dstAddr;
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EthAddr_t srcAddr;
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bit<16> etherType;
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}
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struct Parsed_packet {
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Ethernet_h ethernet;
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}
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// user defined metadata: can be used to share information between
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// TopParser, TopPipe, and TopDeparser
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struct user_metadata_t {
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bit<8> unused;
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}
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// digest_data, MUST be 256 bits -- what is this used for?
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struct digest_data_t {
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bit<256> unused;
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}
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/********************************************************************************
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* Parser
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*/
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// @Xilinx_MaxPacketRegion(1024)
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// parser TopParser(packet_in b,
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// out Parsed_packet p,
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// out user_metadata_t user_metadata,
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// out digest_data_t digest_data,
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// inout sume_metadata_t sume_metadata) {
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// }
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@Xilinx_MaxPacketRegion(1024)
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parser TopParser(packet_in packet,
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out headers hdr,
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// out metadata meta,
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out user_metadata_t user_metadata,
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out digest_data_t digest_data,
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inout sume_metadata_t standard_metadata) {
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state start {
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packet.extract(hdr.ethernet);
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user_metadata.unused = 0;
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digest_data.unused = 0;
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transition accept;
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}
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// #include "parsers.p4"
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}
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/********************************************************************************
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* Main
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*/
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// control TopPipe(inout Parsed_packet p,
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// inout digest_data_t digest_data,
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// inout sume_metadata_t sume_metadata) {
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control TopPipe(inout headers hdr,
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//inout metadata meta,
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inout user_metadata_t user_metadata,
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inout digest_data_t digest_data,
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inout sume_metadata_t sume_metadata) {
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// actions to be enabled
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// #include "actions_nat64_generic.p4" // includes controller & delta checksum
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// #include "actions_egress.p4" // includes v6_networks, v4_networks
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// #include "actions_icmp6_ndp_icmp.p4" // includes icmp6 table, triggers payload checksum!
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// #include "actions_arp.p4" // includes v4_arp, v4_egress
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// #include "actions_delta_checksum.p4" // non payload based checksumming
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// apply {
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// if(hdr.ipv6.isValid()) {
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// if(nat64.apply().hit) { /* generic / static nat64 done */
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// if(hdr.icmp6.isValid()) {
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// nat64_icmp6_generic();
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// if(hdr.icmp6.type == ICMP6_ECHO_REPLY) {
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// hdr.icmp.type = ICMP_ECHO_REPLY;
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// hdr.icmp.code = 0;
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// }
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// if(hdr.icmp6.type == ICMP6_ECHO_REQUEST) {
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// hdr.icmp.type = ICMP_ECHO_REQUEST;
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// hdr.icmp.code = 0;
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// }
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// }
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// if(hdr.udp.isValid()) {
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// #ifdef USE_NICO_DELTA_CHECKSUM
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// delta_udp_from_v6_to_v4();
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// #else
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// meta.chk_udp_v4 = 1;
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// #endif
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// }
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// if(hdr.tcp.isValid()) {
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// #ifdef USE_NICO_DELTA_CHECKSUM
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// delta_tcp_from_v6_to_v4();
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// #else
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// meta.chk_tcp_v4 = 1;
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// #endif
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// }
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// v4_networks.apply(); /* apply egress for IPv4 */
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// exit; /* no further v6 processing */
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// }
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// icmp6.apply(); /* icmp6 echo, icmp6 ndp */
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// v6_networks.apply(); /* regular egress / routing */
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// } else if(hdr.ipv4.isValid()) {
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// if(icmp.apply().hit) {
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// v4_networks.apply();
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// exit;
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// } else if(nat46.apply().hit) {
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// if(hdr.icmp.isValid()) {
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// nat46_icmp_generic();
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// if(hdr.icmp.type == ICMP_ECHO_REPLY) {
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// hdr.icmp6.type = ICMP6_ECHO_REPLY;
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// }
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// if(hdr.icmp.type == ICMP_ECHO_REQUEST) {
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// hdr.icmp6.type = ICMP6_ECHO_REQUEST;
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// }
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// }
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// if(hdr.udp.isValid()) {
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// #ifdef USE_NICO_DELTA_CHECKSUM
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// delta_udp_from_v4_to_v6();
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// #else
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// meta.chk_udp_v6 = 1;
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// #endif
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// }
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// if(hdr.tcp.isValid()) {
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// #ifdef USE_NICO_DELTA_CHECKSUM
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// delta_tcp_from_v4_to_v6();
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// #else
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// meta.chk_tcp_v6 = 1;
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// #endif
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// }
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// v6_networks.apply();
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// exit;
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// }
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// v4_networks.apply(); /* regular routing, egress */
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// } else if(hdr.arp.isValid()) {
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// if(v4_arp.apply().hit) {
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// v4_arp_egress.apply();
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// }
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// }
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// }
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action swap_eth_addresses() {
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EthAddr_t temp = hdr.ethernet.dst_addr;
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hdr.ethernet.dst_addr = hdr.ethernet.src_addr;
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hdr.ethernet.src_addr = temp;
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/* set egress port */
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sume_metadata.dst_port = sume_metadata.src_port;
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}
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action send_to_port1() {
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sume_metadata.dst_port = 1;
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}
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// action send_testdata_to_port1() {
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// // python: MAC2 = "08:22:22:22:22:08"
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// if(hdr.ethernet.dst_addr == 0x082222222208) {
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// sume_metadata.dst_port = 1;
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// }
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// }
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action send_to_all_ports() {
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/* Taken from commands.txt of the "int" project:
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table_cam_add_entry forward set_output_port 0xffffffffffff => 0b01010101
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python convert:
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>>> 0b01010101
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85
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*/
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sume_metadata.dst_port = 85;
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}
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action do_nothing() {
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EthAddr_t temp = hdr.ethernet.dst_addr;
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}
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#ifdef ENABLE_CONTROLLER
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#include "actions_controller.p4"
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#endif
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table lookup_table {
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key = {
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hdr.ethernet.dst_addr: exact;
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}
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actions = {
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#ifdef ENABLE_CONTROLLER
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controller_debug;
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#endif
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swap_eth_addresses;
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do_nothing;
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send_to_port1;
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send_to_all_ports;
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}
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size = 64;
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// default_action = swap_eth_addresses; // test_mirror(): in gen_testdata.py
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default_action = send_to_port1; // test_port1()
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// default_action = send_to_all_ports; // test_allports():
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}
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apply {
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lookup_table.apply();
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}
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}
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/********************************************************************************
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* Deparser
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*/
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@Xilinx_MaxPacketRegion(1024)
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control TopDeparser(packet_out packet,
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in headers hdr,
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in user_metadata_t user_metadata,
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// in metadata meta,
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inout digest_data_t digest_data,
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inout sume_metadata_t sume_metadata) {
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// @Xilinx_MaxPacketRegion(1024)
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// control TopDeparser(packet_out b,
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// in Parsed_packet p,
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// inout digest_data_t digest_data,
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// inout sume_metadata_t sume_metadata) {
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apply {
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packet.emit(hdr.ethernet);
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}
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// #include "deparser.p4"
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}
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/********************************************************************************
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* Switch
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*/
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SimpleSumeSwitch(
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TopParser(),
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TopPipe(),
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TopDeparser()
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) main;
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