214 lines
7.0 KiB
Tcl
214 lines
7.0 KiB
Tcl
#
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# Copyright (c) 2015 Digilent Inc.
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# Copyright (c) 2015 Tinghui Wang (Steve)
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# All rights reserved.
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#
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# File:
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# nf_sume_mbsys.tcl
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#
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# Project:
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# acceptance_test
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#
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# Author:
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# Tinghui Wang (Steve)
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#
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# Description:
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# tcl function to create basic microblaze sub-system (mbsys) for
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# embedded design projects. Default bram size is 64KB.
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# useage:
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# create_hier_cell_mbsys <parentCell> <nameHier> <M_AXI_LITE_No>
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#
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# @NETFPGA_LICENSE_HEADER_START@
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#
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#
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# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
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# license agreements. See the NOTICE file distributed with this work for
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# additional information regarding copyright ownership. NetFPGA licenses this
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# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at:
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#
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# http://www.netfpga-cic.org
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#
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# Unless required by applicable law or agreed to in writing, Work distributed
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# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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# CONDITIONS OF ANY KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations under the License.
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#
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# @NETFPGA_LICENSE_HEADER_END@
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#
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set help_msg "create_bd -name <bd_name> \[-iic <true\/false>\] \[-uart <true\/false>\] \[-add_ro <ro_width>\] \[-add_rw <rw_width>\]"
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proc create_bd args {
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if { [llength $args] % 2 == 1 } {
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error "create_bd: Wrong # args."
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puts $help_msg
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}
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array set opts {
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-name "system"
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-iic false
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-uart false
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-add_ro {}
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-add_rw {}
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}
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foreach {opt value} [lrange $args 0 end] {
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if {![info exist opts($opt)]} {
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error "create_bd: unreconized option \"$opt\""
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}
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if {$opt != "-add_ro" && $opt != "-add_rw"} {
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set opts($opt) $value
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} else {
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set opts($opt) [lappend opts($opt) $value]
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}
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}
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# Create Block Diagram
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set design_name $opts(-name)
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set current_bd [create_bd_design $design_name]
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current_bd_design $design_name
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set parentCell [get_bd_cells /]
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set parentObj [get_bd_cells $parentCell]
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set parentType [get_property TYPE $parentObj]
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# Create Reset Ports
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set reset [ create_bd_port -dir I -type rst reset ]
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set_property -dict [ list CONFIG.POLARITY {ACTIVE_HIGH} ] $reset
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# Create Sysclk Ports
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set sysclk [ create_bd_port -dir I -type clk sysclk ]
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set_property CONFIG.FREQ_HZ 100000000 $sysclk
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# Create instance: mbsys
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create_mbsys [current_bd_instance .] mbsys
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if { $opts(-iic) } {
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create_iic
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}
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if { $opts(-uart) } {
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create_uart
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}
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set index 0
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foreach ro_width $opts(-add_ro) {
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create_gpio_ro $index $ro_width
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set index [expr $index + 1]
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}
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set index 0
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foreach rw_width $opts(-add_rw) {
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create_gpio_rw $index $rw_width
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set index [expr $index + 1]
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}
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regenerate_bd_layout
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save_bd_design
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close_bd_design [current_bd_design]
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}
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proc create_mbsys { parentCell hierName} {
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# Create microblaze and apply automation
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create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze microblaze_0
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apply_bd_automation -rule xilinx.com:bd_rule:microblaze -config { \
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local_mem "64KB" \
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ecc "None" \
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cache "None" \
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debug_module "Debug Only" \
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axi_periph "Enabled" \
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axi_intc "1" \
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clk "New Clocking Wizard (100 MHz)" }\
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[get_bd_cells microblaze_0]
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# Configure clock wizard
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set_property -dict [list\
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CONFIG.PRIM_IN_FREQ.VALUE_SRC USER]\
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[get_bd_cells clk_wiz_1]
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set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} CONFIG.PRIM_IN_FREQ {100.000}] [get_bd_cells clk_wiz_1]
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# Connect sysclk
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connect_bd_net [get_bd_pins sysclk] [get_bd_pins clk_wiz_1/clk_in1]
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# Connect reset
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connect_bd_net [get_bd_ports reset] [get_bd_pins clk_wiz_1/reset] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]
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# Create Hierarchy
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group_bd_cells $hierName\
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[get_bd_cells microblaze_0_axi_intc]\
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[get_bd_cells mdm_1]\
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[get_bd_cells microblaze_0_xlconcat]\
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[get_bd_cells microblaze_0]\
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[get_bd_cells rst_clk_wiz_1_100M]\
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[get_bd_cells microblaze_0_axi_periph]\
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[get_bd_cells microblaze_0_local_memory]
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}
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proc create_iic {} {
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## Create instance: axi_iic_0, and set properties
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set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic axi_iic_0 ]
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set_property -dict [ list CONFIG.C_GPO_WIDTH {2} CONFIG.C_SCL_INERTIAL_DELAY {5} CONFIG.C_SDA_INERTIAL_DELAY {5} ] $axi_iic_0
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apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/mbsys/microblaze_0 (Periph)" Clk "Auto" } [get_bd_intf_pins axi_iic_0/S_AXI]
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## Create and connect to external ports
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set iic_fpga [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga ]
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set iic_reset [ create_bd_port -dir O -from 1 -to 0 iic_reset ]
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connect_bd_intf_net [get_bd_intf_ports iic_fpga] [get_bd_intf_pins axi_iic_0/IIC]
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connect_bd_net [get_bd_ports iic_reset] [get_bd_pins axi_iic_0/gpo]
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## Connect interrupts
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connect_bd_net [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins mbsys/microblaze_0_xlconcat/In0]
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}
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proc create_uart {} {
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## Create instance: axi_uartlite_0, and set properties
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set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite axi_uartlite_0 ]
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set_property -dict [ list CONFIG.C_BAUDRATE {115200} ] $axi_uartlite_0
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apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/mbsys/microblaze_0 (Periph)" Clk "Auto" } [get_bd_intf_pins axi_uartlite_0/S_AXI]
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## Create and connect to external ports
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set uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart ]
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connect_bd_intf_net [get_bd_intf_ports uart] [get_bd_intf_pins axi_uartlite_0/UART]
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## Connect interrupts
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connect_bd_net [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins mbsys/microblaze_0_xlconcat/In1]
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}
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proc create_gpio_ro { index width } {
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set gpio_name axi_gpio_ro_$index
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## Create instance: axi_gpio_ro, and set properties
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create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio $gpio_name
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set_property -dict [ list\
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CONFIG.C_IS_DUAL 0\
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CONFIG.C_ALL_INPUTS 1\
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CONFIG.C_ALL_OUTPUTS 0\
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CONFIG.C_GPIO_WIDTH $width ]\
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[get_bd_cells $gpio_name]
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apply_bd_automation -rule xilinx.com:bd_rule:axi4\
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-config {Master "/mbsys/microblaze_0 (Periph)" Clk "Auto" }\
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[get_bd_intf_pins $gpio_name/S_AXI]
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set gpio_in_$index [create_bd_port -dir I -from [expr $width - 1] -to 0 gpio_in_$index]
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connect_bd_net [get_bd_pins $gpio_name/gpio_io_i] [get_bd_ports gpio_in_$index]
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}
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proc create_gpio_rw { index width } {
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set gpio_name axi_gpio_rw_$index
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create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio $gpio_name
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set_property -dict [ list\
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CONFIG.C_IS_DUAL 0\
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CONFIG.C_ALL_INPUTS 0\
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CONFIG.C_ALL_OUTPUTS 1\
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CONFIG.C_GPIO_WIDTH $width ]\
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[get_bd_cells $gpio_name]
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apply_bd_automation -rule xilinx.com:bd_rule:axi4\
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-config {Master "/mbsys/microblaze_0 (Periph)" Clk "Auto" }\
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[get_bd_intf_pins $gpio_name/S_AXI]
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set gpio_out_$index [create_bd_port -dir O -from [expr $width - 1] -to 0 gpio_out_$index]
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connect_bd_net [get_bd_pins $gpio_name/gpio_io_o] [get_bd_ports gpio_out_$index]
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}
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