168 lines
8.8 KiB
Tcl
168 lines
8.8 KiB
Tcl
#
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# Copyright (c) 2015 Noa Zilberman
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# All rights reserved.
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#
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# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
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# under National Science Foundation under Grant No. CNS-0855268,
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# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
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# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
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# as part of the DARPA MRC research programme.
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#
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# @NETFPGA_LICENSE_HEADER_START@
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#
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# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
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# license agreements. See the NOTICE file distributed with this work for
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# additional information regarding copyright ownership. NetFPGA licenses this
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# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at:
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#
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# http://www.netfpga-cic.org
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#
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# Unless required by applicable law or agreed to in writing, Work distributed
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# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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# CONDITIONS OF ANY KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations under the License.
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#
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# @NETFPGA_LICENSE_HEADER_END@
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#
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# Vivado Launch Script
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#### Change design settings here #######
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set design $::env(NF_PROJECT_NAME)
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set top top
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set device xc7vx690t-3-ffg1761
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set proj_dir ./project
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set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
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set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/
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set repo_dir ./ip_repo
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set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc
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set project_constraints ./constraints/nf_sume_general.xdc
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set nf_10g_constraints ./constraints/nf_sume_10g.xdc
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#####################################
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# Read IP Addresses and export registers
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#####################################
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source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl
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source ./tcl/export_registers.tcl
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#####################################
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# set IP paths
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#####################################
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#####################################
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# Project Settings
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#####################################
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create_project -name ${design} -force -dir "./${proj_dir}" -part ${device}
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set_property source_mgmt_mode DisplayOnly [current_project]
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set_property top ${top} [current_fileset]
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puts "Creating User Datapath reference project"
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#####################################
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# Project Constraints
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#####################################
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create_fileset -constrset -quiet constraints
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file copy ${public_repo_dir}/ ${repo_dir}
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set_property ip_repo_paths ${repo_dir} [current_fileset]
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add_files -fileset constraints -norecurse ${bit_settings}
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add_files -fileset constraints -norecurse ${project_constraints}
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add_files -fileset constraints -norecurse ${nf_10g_constraints}
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set_property is_enabled true [get_files ${project_constraints}]
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set_property is_enabled true [get_files ${bit_settings}]
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set_property is_enabled true [get_files ${nf_10g_constraints}]
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set_property constrset constraints [get_runs synth_1]
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set_property constrset constraints [get_runs impl_1]
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#####################################
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# Project
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#####################################
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update_ip_catalog
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create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip
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set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci]
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reset_target all [get_ips input_arbiter_ip]
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generate_target all [get_ips input_arbiter_ip]
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create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip
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set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci]
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reset_target all [get_ips sss_output_queues_ip]
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generate_target all [get_ips sss_output_queues_ip]
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#create the IPI Block Diagram
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source ./tcl/control_sub.tcl
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#source ../hw/create_ip/nf_sume_sdnet.tcl # only need this if sdnet_to_sume has fifo in wrapper
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create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
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set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci]
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reset_target all [get_ips nf_sume_sdnet_ip]
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generate_target all [get_ips nf_sume_sdnet_ip]
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source ./create_ip/nf_10ge_interface.tcl
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create_ip -name nf_10ge_interface -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_ip
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set_property generate_synth_checkpoint false [get_files nf_10g_interface_ip.xci]
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reset_target all [get_ips nf_10g_interface_ip]
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generate_target all [get_ips nf_10g_interface_ip]
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source ./create_ip/nf_10ge_interface_shared.tcl
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create_ip -name nf_10ge_interface_shared -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_shared_ip
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set_property generate_synth_checkpoint false [get_files nf_10g_interface_shared_ip.xci]
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reset_target all [get_ips nf_10g_interface_shared_ip]
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generate_target all [get_ips nf_10g_interface_shared_ip]
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#Add a clock wizard
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create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip
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set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip]
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set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci]
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reset_target all [get_ips clk_wiz_ip]
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generate_target all [get_ips clk_wiz_ip]
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create_ip -name proc_sys_reset -vendor xilinx.com -library ip -version 5.0 -module_name proc_sys_reset_ip
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set_property -dict [list CONFIG.C_EXT_RESET_HIGH {0} CONFIG.C_AUX_RESET_HIGH {0}] [get_ips proc_sys_reset_ip]
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set_property -dict [list CONFIG.C_NUM_PERP_RST {1} CONFIG.C_NUM_PERP_ARESETN {1}] [get_ips proc_sys_reset_ip]
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set_property generate_synth_checkpoint false [get_files proc_sys_reset_ip.xci]
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reset_target all [get_ips proc_sys_reset_ip]
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generate_target all [get_ips proc_sys_reset_ip]
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#Add ID block
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create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip
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set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {4096} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip]
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set_property generate_synth_checkpoint false [get_files identifier_ip.xci]
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reset_target all [get_ips identifier_ip]
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generate_target all [get_ips identifier_ip]
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read_verilog "./hdl/axi_clocking.v"
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read_verilog "./hdl/nf_datapath.v"
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read_verilog "./hdl/top.v"
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#Setting Synthesis options
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create_run -flow {Vivado Synthesis 2018} synth
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#Setting Implementation options
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create_run impl -parent_run synth -flow {Vivado Implementation 2018}
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#set_property strategy Performance_LateBlockPlacement [get_runs impl_1]
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set_property steps.phys_opt_design.is_enabled true [get_runs impl_1]
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#set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
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#set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
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#set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AlternateFlowWithRetiming [get_runs impl_1]
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set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE ExploreWithHoldFix [get_runs impl_1]
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set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
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set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.is_enabled true [get_runs impl_1]
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#set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
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set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
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# The following implementation options will increase runtime, but get the best timing results
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#set_property strategy Performance_Explore [get_runs impl_1]
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### Solves synthesis crash in 2013.2
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##set_param synth.filterSetMaxDelayWithDataPathOnly true
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set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
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launch_runs synth
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wait_on_run synth
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launch_runs impl_1 -to_step write_bitstream
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wait_on_run impl_1
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exit
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