335 lines
17 KiB
Tcl
335 lines
17 KiB
Tcl
#
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# Copyright (c) 2015 Georgina Kalogeridou
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# All rights reserved.
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#
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# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
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# under National Science Foundation under Grant No. CNS-0855268,
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# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
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# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
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# as part of the DARPA MRC research programme.
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#
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# @NETFPGA_LICENSE_HEADER_START@
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#
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# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
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# license agreements. See the NOTICE file distributed with this work for
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# additional information regarding copyright ownership. NetFPGA licenses this
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# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at:
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#
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# http://www.netfpga-cic.org
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#
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# Unless required by applicable law or agreed to in writing, Work distributed
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# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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# CONDITIONS OF ANY KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations under the License.
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#
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# @NETFPGA_LICENSE_HEADER_END@
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#
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# Set variables.
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set design $::env(NF_PROJECT_NAME)
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set top top_sim
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set sim_top top_tb
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set device xc7vx690t-3-ffg1761
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set proj_dir ./project
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set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
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set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/
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set repo_dir ./ip_repo
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set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc
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set project_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_general.xdc
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set nf_10g_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_10g.xdc
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set test_name [lindex $argv 0]
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#####################################
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# Read IP Addresses and export registers
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#####################################
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source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
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# Build project.
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create_project -name ${design} -force -dir "$::env(NF_DESIGN_DIR)/hw/${proj_dir}" -part ${device}
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set_property source_mgmt_mode DisplayOnly [current_project]
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set_property top ${top} [current_fileset]
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puts "Creating User Datapath reference project"
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create_fileset -constrset -quiet constraints
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file copy ${public_repo_dir}/ ${repo_dir}
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set_property ip_repo_paths ${repo_dir} [current_fileset]
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add_files -fileset constraints -norecurse ${bit_settings}
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add_files -fileset constraints -norecurse ${project_constraints}
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add_files -fileset constraints -norecurse ${nf_10g_constraints}
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set_property is_enabled true [get_files ${project_constraints}]
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set_property is_enabled true [get_files ${bit_settings}]
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set_property is_enabled true [get_files ${project_constraints}]
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update_ip_catalog
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#source ../hw/create_ip/nf_sume_sdnet.tcl # only need this if have sdnet_to_sume fifo in wrapper
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create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
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set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci]
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reset_target all [get_ips nf_sume_sdnet_ip]
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generate_target all [get_ips nf_sume_sdnet_ip]
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create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip
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set_property -dict [list CONFIG.C_BASEADDR $INPUT_ARBITER_BASEADDR] [get_ips input_arbiter_ip]
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set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci]
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reset_target all [get_ips input_arbiter_ip]
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generate_target all [get_ips input_arbiter_ip]
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create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip
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set_property -dict [list CONFIG.C_BASEADDR $OUTPUT_QUEUES_BASEADDR] [get_ips sss_output_queues_ip]
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set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci]
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reset_target all [get_ips sss_output_queues_ip]
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generate_target all [get_ips sss_output_queues_ip]
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#Add ID block
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create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip
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set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {1024} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip]
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set_property generate_synth_checkpoint false [get_files identifier_ip.xci]
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reset_target all [get_ips identifier_ip]
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generate_target all [get_ips identifier_ip]
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create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip
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set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip]
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set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci]
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reset_target all [get_ips clk_wiz_ip]
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generate_target all [get_ips clk_wiz_ip]
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create_ip -name barrier -vendor NetFPGA -library NetFPGA -module_name barrier_ip
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reset_target all [get_ips barrier_ip]
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generate_target all [get_ips barrier_ip]
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create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip0
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set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_0_log.axi] [get_ips axis_sim_record_ip0]
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reset_target all [get_ips axis_sim_record_ip0]
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generate_target all [get_ips axis_sim_record_ip0]
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create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip1
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set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_1_log.axi] [get_ips axis_sim_record_ip1]
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reset_target all [get_ips axis_sim_record_ip1]
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generate_target all [get_ips axis_sim_record_ip1]
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create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip2
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set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_2_log.axi] [get_ips axis_sim_record_ip2]
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reset_target all [get_ips axis_sim_record_ip2]
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generate_target all [get_ips axis_sim_record_ip2]
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create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip3
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set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_3_log.axi] [get_ips axis_sim_record_ip3]
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reset_target all [get_ips axis_sim_record_ip3]
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generate_target all [get_ips axis_sim_record_ip3]
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create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip4
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set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/dma_0_log.axi] [get_ips axis_sim_record_ip4]
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reset_target all [get_ips axis_sim_record_ip4]
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generate_target all [get_ips axis_sim_record_ip4]
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create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip0
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set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_0_stim.axi] [get_ips axis_sim_stim_ip0]
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generate_target all [get_ips axis_sim_stim_ip0]
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create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip1
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set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_1_stim.axi] [get_ips axis_sim_stim_ip1]
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generate_target all [get_ips axis_sim_stim_ip1]
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create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip2
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set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_2_stim.axi] [get_ips axis_sim_stim_ip2]
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generate_target all [get_ips axis_sim_stim_ip2]
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create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip3
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set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_3_stim.axi] [get_ips axis_sim_stim_ip3]
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generate_target all [get_ips axis_sim_stim_ip3]
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create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip4
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set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/dma_0_stim.axi] [get_ips axis_sim_stim_ip4]
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generate_target all [get_ips axis_sim_stim_ip4]
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create_ip -name axi_sim_transactor -vendor NetFPGA -library NetFPGA -module_name axi_sim_transactor_ip
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set_property -dict [list CONFIG.STIM_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.axi CONFIG.EXPECT_FILE $::env(NF_DESIGN_DIR)/test/reg_expect.axi CONFIG.LOG_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.log] [get_ips axi_sim_transactor_ip]
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reset_target all [get_ips axi_sim_transactor_ip]
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generate_target all [get_ips axi_sim_transactor_ip]
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update_ip_catalog
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source $::env(NF_DESIGN_DIR)/hw/tcl/control_sub_sim.tcl
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read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/axi_clocking.v"
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read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/nf_datapath.v"
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read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_sim.v"
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read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_tb.v"
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update_compile_order -fileset sources_1
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update_compile_order -fileset sim_1
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set_property top ${sim_top} [get_filesets sim_1]
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set_property include_dirs ${proj_dir} [get_filesets sim_1]
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set_property simulator_language Mixed [current_project]
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set_property verilog_define { {SIMULATION=1} } [get_filesets sim_1]
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set_property -name xsim.more_options -value {-testplusarg TESTNAME=basic_test} -objects [get_filesets sim_1]
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set_property runtime {} [get_filesets sim_1]
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set_property target_simulator xsim [current_project]
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set_property compxlib.xsim_compiled_library_dir {} [current_project]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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update_compile_order -fileset sim_1
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set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]
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puts $output
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set_property xsim.view {} [get_filesets sim_1]
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launch_simulation -simset sim_1 -mode behavioral
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# Add top level datapath IO
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set nf_datapath top_tb/top_sim/nf_datapath_0/
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add_wave_divider {input arbiter input signals}
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add_wave $nf_datapath/s_axis_0_tdata -color blue
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add_wave $nf_datapath/s_axis_0_tkeep -color blue
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add_wave $nf_datapath/s_axis_0_tuser -color blue
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add_wave $nf_datapath/s_axis_0_tvalid -color blue
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add_wave $nf_datapath/s_axis_0_tready -color blue
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add_wave $nf_datapath/s_axis_0_tlast -color blue
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add_wave $nf_datapath/s_axis_1_tdata -color gold
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add_wave $nf_datapath/s_axis_1_tkeep -color gold
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add_wave $nf_datapath/s_axis_1_tuser -color gold
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add_wave $nf_datapath/s_axis_1_tvalid -color gold
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add_wave $nf_datapath/s_axis_1_tready -color gold
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add_wave $nf_datapath/s_axis_1_tlast -color gold
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add_wave $nf_datapath/s_axis_2_tdata -color orange
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add_wave $nf_datapath/s_axis_2_tkeep -color orange
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add_wave $nf_datapath/s_axis_2_tuser -color orange
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add_wave $nf_datapath/s_axis_2_tvalid -color orange
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add_wave $nf_datapath/s_axis_2_tready -color orange
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add_wave $nf_datapath/s_axis_2_tlast -color orange
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add_wave $nf_datapath/s_axis_3_tdata -color purple
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add_wave $nf_datapath/s_axis_3_tkeep -color purple
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add_wave $nf_datapath/s_axis_3_tuser -color purple
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add_wave $nf_datapath/s_axis_3_tvalid -color purple
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add_wave $nf_datapath/s_axis_3_tready -color purple
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add_wave $nf_datapath/s_axis_3_tlast -color purple
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add_wave $nf_datapath/s_axis_4_tdata -color cyan
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add_wave $nf_datapath/s_axis_4_tkeep -color cyan
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add_wave $nf_datapath/s_axis_4_tuser -color cyan
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add_wave $nf_datapath/s_axis_4_tvalid -color cyan
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add_wave $nf_datapath/s_axis_4_tready -color cyan
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add_wave $nf_datapath/s_axis_4_tlast -color cyan
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add_wave_divider {output queues output signals}
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add_wave $nf_datapath/m_axis_0_tdata -color blue
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add_wave $nf_datapath/m_axis_0_tkeep -color blue
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add_wave $nf_datapath/m_axis_0_tuser -color blue
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add_wave $nf_datapath/m_axis_0_tvalid -color blue
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add_wave $nf_datapath/m_axis_0_tready -color blue
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add_wave $nf_datapath/m_axis_0_tlast -color blue
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add_wave $nf_datapath/m_axis_1_tdata -color gold
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add_wave $nf_datapath/m_axis_1_tkeep -color gold
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add_wave $nf_datapath/m_axis_1_tuser -color gold
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add_wave $nf_datapath/m_axis_1_tvalid -color gold
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add_wave $nf_datapath/m_axis_1_tready -color gold
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add_wave $nf_datapath/m_axis_1_tlast -color gold
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add_wave $nf_datapath/m_axis_2_tdata -color orange
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add_wave $nf_datapath/m_axis_2_tkeep -color orange
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add_wave $nf_datapath/m_axis_2_tuser -color orange
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add_wave $nf_datapath/m_axis_2_tvalid -color orange
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add_wave $nf_datapath/m_axis_2_tready -color orange
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add_wave $nf_datapath/m_axis_2_tlast -color orange
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add_wave $nf_datapath/m_axis_3_tdata -color purple
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add_wave $nf_datapath/m_axis_3_tkeep -color purple
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add_wave $nf_datapath/m_axis_3_tuser -color purple
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add_wave $nf_datapath/m_axis_3_tvalid -color purple
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add_wave $nf_datapath/m_axis_3_tready -color purple
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add_wave $nf_datapath/m_axis_3_tlast -color purple
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add_wave $nf_datapath/m_axis_4_tdata -color cyan
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add_wave $nf_datapath/m_axis_4_tkeep -color cyan
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add_wave $nf_datapath/m_axis_4_tuser -color cyan
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add_wave $nf_datapath/m_axis_4_tvalid -color cyan
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add_wave $nf_datapath/m_axis_4_tready -color cyan
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add_wave $nf_datapath/m_axis_4_tlast -color cyan
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## Add top level AXI Lite control signals to P4_SWITCH
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#add_wave_divider {Top-Level SDNet Control Signals}
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#add_wave top_tb/top_sim/M02_AXI_araddr
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#add_wave top_tb/top_sim/M02_AXI_arprot
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#add_wave top_tb/top_sim/M02_AXI_arready
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#add_wave top_tb/top_sim/M02_AXI_arvalid
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#add_wave top_tb/top_sim/M02_AXI_awaddr
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#add_wave top_tb/top_sim/M02_AXI_awprot
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#add_wave top_tb/top_sim/M02_AXI_awready
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#add_wave top_tb/top_sim/M02_AXI_awvalid
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#add_wave top_tb/top_sim/M02_AXI_bready
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#add_wave top_tb/top_sim/M02_AXI_bresp
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#add_wave top_tb/top_sim/M02_AXI_bvalid
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#add_wave top_tb/top_sim/M02_AXI_rdata
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#add_wave top_tb/top_sim/M02_AXI_rready
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#add_wave top_tb/top_sim/M02_AXI_rresp
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#add_wave top_tb/top_sim/M02_AXI_rvalid
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#add_wave top_tb/top_sim/M02_AXI_wdata
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#add_wave top_tb/top_sim/M02_AXI_wready
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#add_wave top_tb/top_sim/M02_AXI_wstrb
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#add_wave top_tb/top_sim/M02_AXI_wvalid
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# Add SDNet Interface Signals
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set sdnet_ip top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/
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add_wave_divider {SDNet Control Interface}
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add_wave top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/internal_rst_done -color yellow
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add_wave $sdnet_ip/control_S_AXI_AWADDR
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add_wave $sdnet_ip/control_S_AXI_AWVALID
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add_wave $sdnet_ip/control_S_AXI_AWREADY
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add_wave $sdnet_ip/control_S_AXI_WDATA
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add_wave $sdnet_ip/control_S_AXI_WSTRB
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add_wave $sdnet_ip/control_S_AXI_WVALID
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add_wave $sdnet_ip/control_S_AXI_WREADY
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add_wave $sdnet_ip/control_S_AXI_BRESP
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add_wave $sdnet_ip/control_S_AXI_BVALID
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add_wave $sdnet_ip/control_S_AXI_BREADY
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add_wave $sdnet_ip/control_S_AXI_ARADDR
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add_wave $sdnet_ip/control_S_AXI_ARVALID
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add_wave $sdnet_ip/control_S_AXI_ARREADY
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add_wave $sdnet_ip/control_S_AXI_RDATA
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add_wave $sdnet_ip/control_S_AXI_RRESP
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add_wave $sdnet_ip/control_S_AXI_RVALID
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add_wave $sdnet_ip/control_S_AXI_RREADY
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set nf_sume_sdnet_ip top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/
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add_wave_divider {nf_sume_sdnet input interface}
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add_wave $sdnet_ip/clk_lookup_rst
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add_wave $sdnet_ip/clk_lookup
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add_wave $nf_sume_sdnet_ip/s_axis_tdata -radix hex
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add_wave $nf_sume_sdnet_ip/s_axis_tkeep -radix hex
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add_wave $nf_sume_sdnet_ip/s_axis_tvalid
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add_wave $nf_sume_sdnet_ip/s_axis_tready
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add_wave $nf_sume_sdnet_ip/s_axis_tlast
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add_wave_divider {SDNet Tuple-In}
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add_wave $nf_sume_sdnet_ip/sume_tuple_in_VALID
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add_wave $nf_sume_sdnet_ip/s_axis_tuser -radix hex
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add_wave $nf_sume_sdnet_ip/in_pkt_len
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add_wave $nf_sume_sdnet_ip/in_src_port
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add_wave $nf_sume_sdnet_ip/in_dst_port
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add_wave_divider {nf_sume_sdnet output interface}
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add_wave $sdnet_ip/clk_lookup_rst
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add_wave $sdnet_ip/clk_lookup
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add_wave $nf_sume_sdnet_ip/m_axis_tdata -radix hex
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add_wave $nf_sume_sdnet_ip/m_axis_tkeep -radix hex
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add_wave $nf_sume_sdnet_ip/m_axis_tvalid
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add_wave $nf_sume_sdnet_ip/m_axis_tready
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add_wave $nf_sume_sdnet_ip/m_axis_tlast
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add_wave_divider {SDNet Tuple-Out}
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add_wave $nf_sume_sdnet_ip/sume_tuple_out_VALID
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add_wave $nf_sume_sdnet_ip/m_axis_tuser -radix hex
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add_wave $nf_sume_sdnet_ip/out_pkt_len
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add_wave $nf_sume_sdnet_ip/out_src_port
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add_wave $nf_sume_sdnet_ip/out_dst_port
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set const_reg_ip /top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/const_reg_rw_0/
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add_wave_divider {const reg extern signals}
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add_wave $const_reg_ip
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add_wave_divider {const cpu reg signals}
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add_wave $const_reg_ip/const_cpu_regs_inst
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run 60us
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