679 lines
35 KiB
C
679 lines
35 KiB
C
//-
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// Copyright (c) 2015 University of Cambridge
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// All rights reserved.
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//
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// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
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// under National Science Foundation under Grant No. CNS-0855268,
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// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
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// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
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// as part of the DARPA MRC research programme.
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//
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// @NETFPGA_LICENSE_HEADER_START@
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//
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// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
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// license agreements. See the NOTICE file distributed with this work for
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// additional information regarding copyright ownership. NetFPGA licenses this
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// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
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// "License"); you may not use this file except in compliance with the
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// License. You may obtain a copy of the License at:
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//
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// http://www.netfpga-cic.org
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//
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// Unless required by applicable law or agreed to in writing, Work distributed
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// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// @NETFPGA_LICENSE_HEADER_END@
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/////////////////////////////////////////////////////////////////////////////////
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// This is an automatically generated header definitions file
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/////////////////////////////////////////////////////////////////////////////////
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//######################################################
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//# Definitions for MICROBLAZE_AXI_IIC
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//######################################################
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#define SUME_MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
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#define SUME_MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
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#define SUME_MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
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//######################################################
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//# Definitions for MICROBLAZE_UARTLITE
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//######################################################
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#define SUME_MICROBLAZE_UARTLITE_BASEADDR 0x40600000
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#define SUME_MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
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#define SUME_MICROBLAZE_UARTLITE_SIZEADDR 0x10000
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//######################################################
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//# Definitions for MICROBLAZE_DLMB_BRAM
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//######################################################
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#define SUME_MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
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#define SUME_MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
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#define SUME_MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
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//######################################################
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//# Definitions for MICROBLAZE_ILMB_BRAM
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//######################################################
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#define SUME_MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
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#define SUME_MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
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#define SUME_MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
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//######################################################
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//# Definitions for MICROBLAZE_AXI_INTC
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//######################################################
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#define SUME_MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
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#define SUME_MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
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#define SUME_MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
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//######################################################
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//# Definitions for INPUT_ARBITER
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//######################################################
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#define SUME_INPUT_ARBITER_BASEADDR 0x44010000
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#define SUME_INPUT_ARBITER_HIGHADDR 0x44010FFF
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#define SUME_INPUT_ARBITER_SIZEADDR 0x1000
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#define SUME_INPUT_ARBITER_0_ID_OFFSET 0x0
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#define SUME_INPUT_ARBITER_0_ID_DEFAULT 0x0000DA01
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#define SUME_INPUT_ARBITER_0_ID_WIDTH 32
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#define SUME_INPUT_ARBITER_0_VERSION_OFFSET 0x4
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#define SUME_INPUT_ARBITER_0_VERSION_DEFAULT 0x1
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#define SUME_INPUT_ARBITER_0_VERSION_WIDTH 32
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#define SUME_INPUT_ARBITER_0_RESET_OFFSET 0x8
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#define SUME_INPUT_ARBITER_0_RESET_DEFAULT 0x0
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#define SUME_INPUT_ARBITER_0_RESET_WIDTH 16
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#define SUME_INPUT_ARBITER_0_FLIP_OFFSET 0xC
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#define SUME_INPUT_ARBITER_0_FLIP_DEFAULT 0x0
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#define SUME_INPUT_ARBITER_0_FLIP_WIDTH 32
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#define SUME_INPUT_ARBITER_0_DEBUG_OFFSET 0x10
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#define SUME_INPUT_ARBITER_0_DEBUG_DEFAULT 0x0
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#define SUME_INPUT_ARBITER_0_DEBUG_WIDTH 32
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#define SUME_INPUT_ARBITER_0_PKTIN_OFFSET 0x14
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#define SUME_INPUT_ARBITER_0_PKTIN_DEFAULT 0x0
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#define SUME_INPUT_ARBITER_0_PKTIN_WIDTH 32
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#define SUME_INPUT_ARBITER_0_PKTOUT_OFFSET 0x18
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#define SUME_INPUT_ARBITER_0_PKTOUT_DEFAULT 0x0
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#define SUME_INPUT_ARBITER_0_PKTOUT_WIDTH 32
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//######################################################
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//# Definitions for OUTPUT_QUEUES
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//######################################################
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#define SUME_OUTPUT_QUEUES_BASEADDR 0x44030000
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#define SUME_OUTPUT_QUEUES_HIGHADDR 0x44030FFF
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#define SUME_OUTPUT_QUEUES_SIZEADDR 0x1000
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#define SUME_OUTPUT_QUEUES_0_ID_OFFSET 0x0
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#define SUME_OUTPUT_QUEUES_0_ID_DEFAULT 0x0000DA03
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#define SUME_OUTPUT_QUEUES_0_ID_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_VERSION_OFFSET 0x4
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#define SUME_OUTPUT_QUEUES_0_VERSION_DEFAULT 0x1
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#define SUME_OUTPUT_QUEUES_0_VERSION_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_RESET_OFFSET 0x8
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#define SUME_OUTPUT_QUEUES_0_RESET_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_RESET_WIDTH 16
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#define SUME_OUTPUT_QUEUES_0_FLIP_OFFSET 0xC
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#define SUME_OUTPUT_QUEUES_0_FLIP_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_FLIP_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_DEBUG_OFFSET 0x10
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#define SUME_OUTPUT_QUEUES_0_DEBUG_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_DEBUG_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTIN_OFFSET 0x14
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#define SUME_OUTPUT_QUEUES_0_PKTIN_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTIN_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTOUT_OFFSET 0x18
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#define SUME_OUTPUT_QUEUES_0_PKTOUT_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTOUT_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_OFFSET 0x1C
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_OFFSET 0x20
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_OFFSET 0x24
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_OFFSET 0x28
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_OFFSET 0x2C
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_OFFSET 0x30
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_OFFSET 0x34
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_OFFSET 0x38
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_OFFSET 0x3C
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_OFFSET 0x40
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_OFFSET 0x44
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_OFFSET 0x48
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_OFFSET 0x4C
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_OFFSET 0x50
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_OFFSET 0x54
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_OFFSET 0x58
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_OFFSET 0x5C
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_OFFSET 0x60
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_OFFSET 0x64
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_OFFSET 0x68
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_OFFSET 0x6C
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_OFFSET 0x70
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_OFFSET 0x74
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_OFFSET 0x78
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_OFFSET 0x7C
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_OFFSET 0x80
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_OFFSET 0x84
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_OFFSET 0x88
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_OFFSET 0x8C
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_OFFSET 0x90
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_OFFSET 0x94
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_OFFSET 0x98
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_OFFSET 0x9C
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_OFFSET 0xA0
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_WIDTH 32
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_OFFSET 0xA4
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_DEFAULT 0x0
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#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_WIDTH 32
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//######################################################
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//# Definitions for OUTPUT_PORT_LOOKUP
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//######################################################
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#define SUME_OUTPUT_PORT_LOOKUP_BASEADDR 0x44020000
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#define SUME_OUTPUT_PORT_LOOKUP_HIGHADDR 0x44020FFF
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#define SUME_OUTPUT_PORT_LOOKUP_SIZEADDR 0x1000
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#define SUME_OUTPUT_PORT_LOOKUP_0_ID_OFFSET 0x0
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#define SUME_OUTPUT_PORT_LOOKUP_0_ID_DEFAULT 0x0001DA02
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#define SUME_OUTPUT_PORT_LOOKUP_0_ID_WIDTH 32
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#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_OFFSET 0x4
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#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_DEFAULT 0x1
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#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_WIDTH 32
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#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_OFFSET 0x8
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#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_DEFAULT 0x0
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#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_WIDTH 16
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#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_OFFSET 0xC
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#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_DEFAULT 0x0
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#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_WIDTH 32
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#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_OFFSET 0x10
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#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_DEFAULT 0x0
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#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_WIDTH 32
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#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_OFFSET 0x14
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#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_DEFAULT 0x0
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#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_WIDTH 32
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#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_OFFSET 0x18
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#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_DEFAULT 0x0
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#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_WIDTH 32
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#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_OFFSET 0x1C
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#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_DEFAULT 0x0
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#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_WIDTH 32
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#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_OFFSET 0x20
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#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_DEFAULT 0x0
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#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_WIDTH 32
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//######################################################
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//# Definitions for NF_10G_INTERFACE0
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//######################################################
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#define SUME_NF_10G_INTERFACE0_BASEADDR 0x44040000
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#define SUME_NF_10G_INTERFACE0_HIGHADDR 0x44040FFF
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#define SUME_NF_10G_INTERFACE0_SIZEADDR 0x1000
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#define SUME_NF_10G_INTERFACE_SHARED_0_ID_OFFSET 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_ID_DEFAULT 0x00001F10
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#define SUME_NF_10G_INTERFACE_SHARED_0_ID_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_OFFSET 0x4
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#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_DEFAULT 0x1
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#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_OFFSET 0x8
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#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_WIDTH 16
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#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_OFFSET 0xC
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#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_OFFSET 0x10
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#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_OFFSET 0x14
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#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_OFFSET 0x18
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#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_OFFSET 0x1C
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#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_OFFSET 0x20
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#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_WIDTH 2
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_OFFSET 0x24
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_WIDTH 8
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_OFFSET 0x28
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_OFFSET 0x2C
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_OFFSET 0x30
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_OFFSET 0x34
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_OFFSET 0x38
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_OFFSET 0x3C
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_OFFSET 0x40
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_OFFSET 0x44
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_OFFSET 0x48
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_OFFSET 0x4C
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_OFFSET 0x50
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_OFFSET 0x54
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_OFFSET 0x58
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_WIDTH 32
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_OFFSET 0x5C
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_WIDTH 32
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//######################################################
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//# Definitions for NF_10G_INTERFACE1
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//######################################################
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#define SUME_NF_10G_INTERFACE1_BASEADDR 0x44050000
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#define SUME_NF_10G_INTERFACE1_HIGHADDR 0x44050FFF
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#define SUME_NF_10G_INTERFACE1_SIZEADDR 0x1000
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#define SUME_NF_10G_INTERFACE_1_ID_OFFSET 0x0
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#define SUME_NF_10G_INTERFACE_1_ID_DEFAULT 0x00001F10
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#define SUME_NF_10G_INTERFACE_1_ID_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_VERSION_OFFSET 0x4
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#define SUME_NF_10G_INTERFACE_1_VERSION_DEFAULT 0x1
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#define SUME_NF_10G_INTERFACE_1_VERSION_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_RESET_OFFSET 0x8
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#define SUME_NF_10G_INTERFACE_1_RESET_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_RESET_WIDTH 16
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#define SUME_NF_10G_INTERFACE_1_FLIP_OFFSET 0xC
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#define SUME_NF_10G_INTERFACE_1_FLIP_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_FLIP_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_DEBUG_OFFSET 0x10
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#define SUME_NF_10G_INTERFACE_1_DEBUG_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_DEBUG_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_INTERFACEID_OFFSET 0x14
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#define SUME_NF_10G_INTERFACE_1_INTERFACEID_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_INTERFACEID_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PKTIN_OFFSET 0x18
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#define SUME_NF_10G_INTERFACE_1_PKTIN_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PKTIN_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PKTOUT_OFFSET 0x1C
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#define SUME_NF_10G_INTERFACE_1_PKTOUT_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PKTOUT_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_OFFSET 0x20
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#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_WIDTH 2
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_OFFSET 0x24
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_WIDTH 8
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_OFFSET 0x28
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_OFFSET 0x2C
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_OFFSET 0x30
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_OFFSET 0x34
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_OFFSET 0x38
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_OFFSET 0x3C
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_OFFSET 0x40
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_OFFSET 0x44
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_OFFSET 0x48
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_OFFSET 0x4C
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_OFFSET 0x50
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_OFFSET 0x54
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_OFFSET 0x58
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_WIDTH 32
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_OFFSET 0x5C
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_WIDTH 32
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//######################################################
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//# Definitions for NF_10G_INTERFACE2
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//######################################################
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#define SUME_NF_10G_INTERFACE2_BASEADDR 0x44060000
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#define SUME_NF_10G_INTERFACE2_HIGHADDR 0x44060FFF
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#define SUME_NF_10G_INTERFACE2_SIZEADDR 0x1000
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#define SUME_NF_10G_INTERFACE_2_ID_OFFSET 0x0
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#define SUME_NF_10G_INTERFACE_2_ID_DEFAULT 0x00001F10
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#define SUME_NF_10G_INTERFACE_2_ID_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_VERSION_OFFSET 0x4
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#define SUME_NF_10G_INTERFACE_2_VERSION_DEFAULT 0x1
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#define SUME_NF_10G_INTERFACE_2_VERSION_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_RESET_OFFSET 0x8
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#define SUME_NF_10G_INTERFACE_2_RESET_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_RESET_WIDTH 16
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#define SUME_NF_10G_INTERFACE_2_FLIP_OFFSET 0xC
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#define SUME_NF_10G_INTERFACE_2_FLIP_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_FLIP_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_DEBUG_OFFSET 0x10
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#define SUME_NF_10G_INTERFACE_2_DEBUG_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_DEBUG_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_INTERFACEID_OFFSET 0x14
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#define SUME_NF_10G_INTERFACE_2_INTERFACEID_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_INTERFACEID_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PKTIN_OFFSET 0x18
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#define SUME_NF_10G_INTERFACE_2_PKTIN_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PKTIN_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PKTOUT_OFFSET 0x1C
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#define SUME_NF_10G_INTERFACE_2_PKTOUT_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PKTOUT_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_OFFSET 0x20
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#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_WIDTH 2
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_OFFSET 0x24
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_WIDTH 8
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_OFFSET 0x28
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_OFFSET 0x2C
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_OFFSET 0x30
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_OFFSET 0x34
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_OFFSET 0x38
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_OFFSET 0x3C
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_OFFSET 0x40
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_OFFSET 0x44
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_OFFSET 0x48
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_OFFSET 0x4C
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_OFFSET 0x50
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_OFFSET 0x54
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_WIDTH 32
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_OFFSET 0x58
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_WIDTH 32
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|
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_OFFSET 0x5C
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|
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_DEFAULT 0x0
|
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#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_WIDTH 32
|
|
|
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//######################################################
|
|
//# Definitions for NF_10G_INTERFACE3
|
|
//######################################################
|
|
#define SUME_NF_10G_INTERFACE3_BASEADDR 0x44070000
|
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#define SUME_NF_10G_INTERFACE3_HIGHADDR 0x44070FFF
|
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#define SUME_NF_10G_INTERFACE3_SIZEADDR 0x1000
|
|
|
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#define SUME_NF_10G_INTERFACE_3_ID_OFFSET 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_ID_DEFAULT 0x00001F10
|
|
#define SUME_NF_10G_INTERFACE_3_ID_WIDTH 32
|
|
#define SUME_NF_10G_INTERFACE_3_VERSION_OFFSET 0x4
|
|
#define SUME_NF_10G_INTERFACE_3_VERSION_DEFAULT 0x1
|
|
#define SUME_NF_10G_INTERFACE_3_VERSION_WIDTH 32
|
|
#define SUME_NF_10G_INTERFACE_3_RESET_OFFSET 0x8
|
|
#define SUME_NF_10G_INTERFACE_3_RESET_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_RESET_WIDTH 16
|
|
#define SUME_NF_10G_INTERFACE_3_FLIP_OFFSET 0xC
|
|
#define SUME_NF_10G_INTERFACE_3_FLIP_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_FLIP_WIDTH 32
|
|
#define SUME_NF_10G_INTERFACE_3_DEBUG_OFFSET 0x10
|
|
#define SUME_NF_10G_INTERFACE_3_DEBUG_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_DEBUG_WIDTH 32
|
|
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_OFFSET 0x14
|
|
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_WIDTH 32
|
|
#define SUME_NF_10G_INTERFACE_3_PKTIN_OFFSET 0x18
|
|
#define SUME_NF_10G_INTERFACE_3_PKTIN_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_PKTIN_WIDTH 32
|
|
#define SUME_NF_10G_INTERFACE_3_PKTOUT_OFFSET 0x1C
|
|
#define SUME_NF_10G_INTERFACE_3_PKTOUT_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_PKTOUT_WIDTH 32
|
|
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_OFFSET 0x20
|
|
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_WIDTH 2
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_OFFSET 0x24
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_WIDTH 8
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_OFFSET 0x28
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_WIDTH 32
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_OFFSET 0x2C
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_WIDTH 32
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_OFFSET 0x30
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_WIDTH 32
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_OFFSET 0x34
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_DEFAULT 0x0
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_WIDTH 32
|
|
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_OFFSET 0x38
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_WIDTH 32
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_OFFSET 0x3C
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_WIDTH 32
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_OFFSET 0x40
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_WIDTH 32
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_OFFSET 0x44
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_WIDTH 32
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_OFFSET 0x48
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_WIDTH 32
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_OFFSET 0x4C
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_WIDTH 32
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_OFFSET 0x50
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_WIDTH 32
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_OFFSET 0x54
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_WIDTH 32
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_OFFSET 0x58
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_WIDTH 32
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_OFFSET 0x5C
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_DEFAULT 0x0
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#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_WIDTH 32
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//######################################################
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//# Definitions for NF_RIFFA_DMA
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//######################################################
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#define SUME_NF_RIFFA_DMA_BASEADDR 0x44080000
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#define SUME_NF_RIFFA_DMA_HIGHADDR 0x44080FFF
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#define SUME_NF_RIFFA_DMA_SIZEADDR 0x1000
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#define SUME_NF_RIFFA_DMA_0_ID_OFFSET 0x0
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#define SUME_NF_RIFFA_DMA_0_ID_DEFAULT 0x00001FFA
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#define SUME_NF_RIFFA_DMA_0_ID_WIDTH 32
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#define SUME_NF_RIFFA_DMA_0_VERSION_OFFSET 0x4
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#define SUME_NF_RIFFA_DMA_0_VERSION_DEFAULT 0x1
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#define SUME_NF_RIFFA_DMA_0_VERSION_WIDTH 32
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#define SUME_NF_RIFFA_DMA_0_RESET_OFFSET 0x8
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#define SUME_NF_RIFFA_DMA_0_RESET_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_RESET_WIDTH 16
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#define SUME_NF_RIFFA_DMA_0_FLIP_OFFSET 0xC
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#define SUME_NF_RIFFA_DMA_0_FLIP_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_FLIP_WIDTH 32
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#define SUME_NF_RIFFA_DMA_0_DEBUG_OFFSET 0x10
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#define SUME_NF_RIFFA_DMA_0_DEBUG_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_DEBUG_WIDTH 32
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#define SUME_NF_RIFFA_DMA_0_RQPKT_OFFSET 0x14
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#define SUME_NF_RIFFA_DMA_0_RQPKT_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_RQPKT_WIDTH 32
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#define SUME_NF_RIFFA_DMA_0_RCPKT_OFFSET 0x18
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#define SUME_NF_RIFFA_DMA_0_RCPKT_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_RCPKT_WIDTH 32
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#define SUME_NF_RIFFA_DMA_0_CQPKT_OFFSET 0x1C
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#define SUME_NF_RIFFA_DMA_0_CQPKT_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_CQPKT_WIDTH 32
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#define SUME_NF_RIFFA_DMA_0_CCPKT_OFFSET 0x20
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#define SUME_NF_RIFFA_DMA_0_CCPKT_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_CCPKT_WIDTH 32
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#define SUME_NF_RIFFA_DMA_0_XGETXPKT_OFFSET 0x24
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#define SUME_NF_RIFFA_DMA_0_XGETXPKT_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_XGETXPKT_WIDTH 32
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#define SUME_NF_RIFFA_DMA_0_XGERXPKT_OFFSET 0x28
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#define SUME_NF_RIFFA_DMA_0_XGERXPKT_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_XGERXPKT_WIDTH 32
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#define SUME_NF_RIFFA_DMA_0_PCIERQ_OFFSET 0x2C
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#define SUME_NF_RIFFA_DMA_0_PCIERQ_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_PCIERQ_WIDTH 32
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|
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_OFFSET 0x30
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|
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_DEFAULT 0x0
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|
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_WIDTH 32
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|
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_OFFSET 0x34
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#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_WIDTH 32
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|
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_OFFSET 0x38
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#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_WIDTH 32
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|
#define SUME_NF_RIFFA_DMA_0_PCIEERROR_OFFSET 0x3C
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#define SUME_NF_RIFFA_DMA_0_PCIEERROR_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_PCIEERROR_WIDTH 32
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|
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_OFFSET 0x40
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|
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_PCIEMISC_WIDTH 32
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|
#define SUME_NF_RIFFA_DMA_0_PCIETPH_OFFSET 0x44
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#define SUME_NF_RIFFA_DMA_0_PCIETPH_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_PCIETPH_WIDTH 32
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|
#define SUME_NF_RIFFA_DMA_0_PCIEFC1_OFFSET 0x48
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#define SUME_NF_RIFFA_DMA_0_PCIEFC1_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_PCIEFC1_WIDTH 32
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|
#define SUME_NF_RIFFA_DMA_0_PCIEFC2_OFFSET 0x4C
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#define SUME_NF_RIFFA_DMA_0_PCIEFC2_DEFAULT 0x0
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#define SUME_NF_RIFFA_DMA_0_PCIEFC2_WIDTH 32
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|
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_OFFSET 0x50
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#define SUME_NF_RIFFA_DMA_0_PCIEFC3_DEFAULT 0x0
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|
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_WIDTH 32
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#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_OFFSET 0x54
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#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_DEFAULT 0x0
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_WIDTH 32
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_OFFSET 0x58
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|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_DEFAULT 0x0
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_WIDTH 32
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_OFFSET 0x5C
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|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_DEFAULT 0x0
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_WIDTH 32
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_OFFSET 0x60
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_DEFAULT 0x0
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_WIDTH 32
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_OFFSET 0x64
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_DEFAULT 0x0
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_WIDTH 32
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_OFFSET 0x68
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_DEFAULT 0x0
|
|
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_WIDTH 32
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