393 lines
18 KiB
TeX
393 lines
18 KiB
TeX
\chapter{\label{summary}Conclusion}
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%** Summary.tex: What have you achieved, what have you presented in this
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% document. What are the highlights of your work.
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% It should conclude by a conclusion.
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Sum up what you have done and recapitulate your key findings.
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%\section{\label{conclusion:overall}Overall}
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\section{\label{conclusion:softwarenat64}Software based NAT64}
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\section{\label{conclusion:general}General}
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Many misleading
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\section{\label{conclusion:bmv2}BMV2}
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\section{\label{conclusion:P4}P4}
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NDP parsing problem
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checksumming a frequent problem and helper
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Many possibilities
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Protocol independent
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Easy architecture
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Limitations in
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if in action limitations
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Limits if in actions
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python2 only - unicode errors
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IPv6: NDP: not easy to parse, as unknown number of following fields
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No support for multiple LPM keys in a table, can be solved with
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ternary matching.
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switch cannot be used in actions
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if things don't work, often a checksum problem.
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if frame checksum, then length of packet is broken
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\begin{verbatim}
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p4c --target bmv2 --arch v1model --std p4-16 "../p4src/static-mapping.p4" -o "/home/p4/master-thesis/p4src"
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../p4src/static-mapping.p4(366): error: Program is not supported by this target, because table MyIngress.v6_networks has multiple successors
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table v6_networks {
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^^^^^^^^^^^
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\end{verbatim}
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\begin{verbatim}
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ipaddress.ip_network("2001:db8:61::/64")
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IPv6Network(u'3230:3031:3a64:6238:3a36:313a:3a2f:3634/128')
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Fix:
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from __future__ import unicode_literals
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\end{verbatim}
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The tooling around P4 is still fragile, encountered many bugs
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in the development.\cite{schottelius:github1675}
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or missing features (\cite{schottelius:github745},
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\cite{theojepsen:_get})
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Hitting expression bug
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retrieving information from tables
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\begin{verbatim}
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Key and mask for matching destination is in table. We need this
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information in the action. However this information is not exposed, so
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we need to specify another parameter with the same information as in
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the key(s).
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Log from slack: (2019-03-14)
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nico [1:55 PM]
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If I use LPM for matching, can I easily get the network address from P4 or do I have to use a bitmask myself? In the latter case it is not exactly clear how to get the mask from the table
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Nate Foster [1:58 PM]
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You want to retrieve the address in the packet? In a table?
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And do you want to do the retrieving from the data plane or the control plane? (edited)
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nico [2:00 PM]
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If I have a match in a table that matches on LPM, it can be any IP address in a network
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For calculating the NAT64/NAT46 translation, I will need the base address, i.e. network address to do subtractions/additions
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So it is fully data plane, what I would like to do
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I'll commit sample code to show the use case more clearly
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https://gitlab.ethz.ch/nicosc/master-thesis/blob/master/p4src/static-mapping.p4#L73
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GitLab
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p4src/static-mapping.p4 · master · nicosc / master-thesis
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gitlab.ethz.ch
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So the action nat64_static() is used in the table v6_networks.
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In v6_networks I use a match on `hdr.ipv6.dst_addr: lpm;`
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What I would like to be able is to get the network address ; I can do that manually, if I have the mask
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I can also re-inject this parameter by another action argument, but I'd assume that I can somewhere read this out from the table / match
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Nate Foster [2:15 PM]
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To make sure I understand, in the data plane, you want to retrieve the address in the lpm pattern? (edited)
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nico [2:16 PM]
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I want to retrieve the key
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Nate Foster [2:16 PM]
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Wait. The value `hdr.ipv6.dst_addr` is the thing used in the match.
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So you have that.
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What you don’t have is the IPv6 address and mask put into the table by the control plane.
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I assume you want the latter, right?
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nico [2:17 PM]
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For example, if my matching key is 2001:db8::/32 and the real address is 2001:db8::f00, then I would like to retrieve 2001:db8:: and 32 from the table
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exactly :slightly_smiling_face:
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I can "fix" this by adding another argument, but it feels somewhat wrong to do that
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Because the table already knows this information
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Nate Foster [2:26 PM]
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I can’t think of a way other than the action parameter hack.
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nico [2:26 PM]
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Oh, ok
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Is it because the information is "lost in hardware"?
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Nate Foster [2:31 PM]
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No you’re right that most implementations have the value in memory. And one can imagine a different table API that allowed one to retrieve it in the data plane.
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But unless I am missing something obvious, P4 hides it…
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\end{verbatim}
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no meta information
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\begin{verbatim}
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Is there any meta information for "from which table was the action
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called" available? My use case is having a debug action that sends
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packets to the controller and I use it as a default_action in various
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tables; however know I don't know anymore from which table the action
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was called. Is there any kind of meta information which table called
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me available?
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I could work around this by using if(! .. .hit) { my_action(table_id)
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}, but it would not work with using default_action = ...
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\end{verbatim}
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type definitions separate
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Code sharing (controller, switch)
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\begin{verbatim}
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*** DONE Synchronisation with the controller
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- Double data type definition -> might differ
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- TYPE_CPU for ethernet
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- Port ingress offset (9 vs. 16 bit)
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\end{verbatim}
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No switch in actions, No conditional execution in actions
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P4os - reusable code
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\begin{verbatim}
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Not addressed so far: how to create re-usable code fragments that can
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be plugged in easily. There could be a hypothetical "P4OS" that
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manages code fragments. This might include, but not limited to
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downloading (signed?) source code, managing dependencies similar to
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Linux package management, handling updates, etc.
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\end{verbatim}
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idomatic problem: Security issue: not checking checksums before
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% ----------------------------------------------------------------------
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\section{\label{conclusion:netpfga}NetFGPA - all HERE}
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many dependencies
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lpm not supported!
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Netpfga live,
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Many workarounds
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packet size / annotation
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Needed to debug internal parsing errors
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debugging generated tcl code to debug impl1 error
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function syntax not supported, using defines instead
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match type exact - table must be at least 64 in size
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Damaged, enlarged packets
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\begin{verbatim}
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** The NetPFGA saga
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Problems encountered:
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- The logfile for a compile run is 10k+ lines
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- Many logged errors can actually be ignored (?) like:
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ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
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ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_DATA on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:219]
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ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_VALID on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:218]
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ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_DATA on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:185]
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ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_VALID on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:184]
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ERROR: [VRFC 10-2063] Module <S_RESETTER_line> not found while processing module instance <S_RESET_clk_line> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/Simp
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leSumeSwitch/SimpleSumeSwitch.v:332]
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ERROR: [VRFC 10-2063] Module <S_RESETTER_lookup> not found while processing module instance <S_RESET_clk_lookup> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/
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SimpleSumeSwitch/SimpleSumeSwitch.v:343]
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ERROR: [VRFC 10-2063] Module <S_RESETTER_control> not found while processing module instance <S_RESET_clk_control> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_i
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p/SimpleSumeSwitch/SimpleSumeSwitch.v:354]
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ERROR: [VRFC 10-2063] Module <TopParser_t> not found while processing module instance <TopParser> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitc
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h/SimpleSumeSwitch.v:436]
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ERROR: [VRFC 10-2063] Module <TopPipe_lvl_t> not found while processing module instance <TopPipe_lvl> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeS
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witch/SimpleSumeSwitch.v:474]
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ERROR: [VRFC 10-2063] Module <dummy_table_for_netpfga_t> not found while processing module instance <dummy_table_for_netpfga> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_s
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ume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:502]
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ERROR: [VRFC 10-2063] Module <TopPipe_lvl_0_t> not found while processing module instance <TopPipe_lvl_0> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleS
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umeSwitch/SimpleSumeSwitch.v:533]
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ERROR: [VRFC 10-2063] Module <TopDeparser_t> not found while processing module instance <TopDeparser> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeS
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witch/SimpleSumeSwitch.v:561]
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# launch_simulation -simset sim_1 -mode behavioral
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INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
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CRITICAL WARNING: [BD 41-1356] Address block </M04_AXI/Reg> is not mapped into </S00_AXI>. Please use Address Editor to either map or exclude it.
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CRITICAL WARNING: [BD 41-1356] Address block </M05_AXI/Reg> is not mapped into </S00_AXI>. Please use Address Editor to either map or exclude it.
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WARNING: [VRFC 10-756] identifier state is used before its declaration [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:93]
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WARNING: [VRFC 10-756] identifier ready_count is used before its declaration [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:94]
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INFO: [#UNDEF] Sorry, too many errors..
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ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
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INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
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INFO: [USF-XSim-99] Step results log file:'/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log'
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ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' file for more information.
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nico@nsg-System:~/master-thesis$ find . -name elaborate.log
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nico@nsg-System:~/master-thesis$ find ~ -name elaborate.log
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nico@nsg-System:~/master-thesis$
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- Scripts that "fail" (generate wrong data) do exit 0 ->
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There is no easy / reliable error detection
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- Writing tables resulted in ioctl errors
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- Hardware test: unclear if first board was/is broken or not,
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BUT: second board in different computer allows writing tables
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- Many scripts depend on each other in later stages, without clear
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dependencies
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- There is basically no documentation for someone who "just wants to
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compile from P4 to netpfga" or A LOT of documentation (if vivado,
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vhld, sdnet documentation is counted)
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- Very high complexity in toolchain, scripts that are generated
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default
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+ make
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rm -f config_writes.py*
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rm -f *.pyc
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nico@nsg-System:~$ cat /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py
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from NFTest import *
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NUM_WRITES = 4
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def config_tables():
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nftest_regwrite(0x44020050, 0x22222208)
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nftest_regwrite(0x44020054, 0x00000822)
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nftest_regwrite(0x44020080, 0x00000201)
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nftest_regwrite(0x44020040, 0x00000001)
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nico@nsg-System:~$ cat /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.sh
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#!/bin/bash
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${SUME_SDNET}/sw/sume/rwaxi -a 0x44020050 -w 0x22222208
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${SUME_SDNET}/sw/sume/rwaxi -a 0x44020054 -w 0x00000822
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${SUME_SDNET}/sw/sume/rwaxi -a 0x44020080 -w 0x00000201
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${SUME_SDNET}/sw/sume/rwaxi -a 0x44020040 -w 0x00000001
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nico@nsg-System:~$
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- Misleading errors like
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ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' file for more information.
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nico@nsg-System:~/master-thesis/netpfga$ ls /home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log
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ls: cannot access '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log': No such file or directory
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- not using raise() and hiding source of errors (_hexify)
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- sometimes flashing fails:
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#+BEGIN_CENTER
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nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles$ sudo bash -c ". $HOME/master-thesis/netpfga/bashinit && $(pwd -P)/program_switch.sh"
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++ which vivado
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+ xilinx_tool_path=/opt/Xilinx/Vivado/2018.2/bin/vivado
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+ bitimage=minip4.bit
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+ configWrites=config_writes.sh
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+ '[' -z minip4.bit ']'
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+ '[' -z config_writes.sh ']'
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+ '[' /opt/Xilinx/Vivado/2018.2/bin/vivado == '' ']'
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+ rmmod sume_riffa
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+ xsct /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl -tclargs minip4.bit
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rlwrap: warning: your $TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems.
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RUN loading image file.
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minip4.bit
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100% 19MB 1.7MB/s 00:11
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fpga configuration failed. DONE PIN is not HIGH
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invoked from within
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"::tcf::eval -progress ::xsdb::print_progress {::tcf::cache_enter tcfchan#0 {tcf_cache_eval {process_tcf_actions_cache_client ::tcfclient#0::arg}}}"
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(procedure "::tcf::cache_eval_with_progress" line 2)
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invoked from within
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"::tcf::cache_eval_with_progress [dict get $arg chan] [list process_tcf_actions_cache_client $argvar] $progress"
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(procedure "process_tcf_actions" line 1)
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invoked from within
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"process_tcf_actions $arg ::xsdb::print_progress"
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(procedure "fpga" line 430)
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invoked from within
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"fpga -f $bitimage"
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(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl" line 33)
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+ bash /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/pci_rescan_run.sh
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Check programming FPGA or Reboot machine !
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+ rmmod sume_riffa
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rmmod: ERROR: Module sume_riffa is not currently loaded
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+ modprobe sume_riffa
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+ ifconfig nf0 up
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nf0: ERROR while getting interface flags: No such device
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+ ifconfig nf1 up
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nf1: ERROR while getting interface flags: No such device
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+ ifconfig nf2 up
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nf2: ERROR while getting interface flags: No such device
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+ ifconfig nf3 up
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nf3: ERROR while getting interface flags: No such device
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+ bash config_writes.sh
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nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles$
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#+END_CENTER
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\end{verbatim}
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\section{\label{conclusion:realworld}Real world applications}
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Can be deployed using the netpfga. Or Barefoot or Arista.
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\section{\label{conclusion:outlook}Outlook}
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%** Outlook.tex: What needs to be done further, what is planed
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%
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What are the consequences of your work for future work?
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Different HW
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Speed only limited to line speed. Could be running at 100 Gbit/s
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without modifications.
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PMTU
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handling error cases
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Our algorithm uses the IPv4-Compatible IPv6 Address\cite{rfc4291} to
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embed IPv4 addresses. However RFC6052\cite{rfc6052} defines different
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embeddings depending on the prefix size. A future version should
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support these schemes to be compatible to other implementations.
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No fragmentation
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No address / mac learning
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**** No DNS64
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has already been solved in a different domain - could even do
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transparent / in network modification
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**** Incomplete NDP
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Very limited option support
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No resolution of hardware addresses
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\section{\label{conclusion:closing}Closing words (NAME?)}
|
||
While the port to NetPFGA was significantly more effort then expected,
|
||
the learnings of the different layers were very much appreciated / liked
|
||
|
||
It was a
|
||
|
||
|
||
% ----------------------------------------------------------------------
|
||
\section{\label{conclusion:netpfga2}NetFGPA2 - conclusion here}
|
||
Very time intensive development due to usability problems and
|
||
uncertainty of functionality (compare sections
|
||
\ref{results:netpfga:usability} and \ref{results:netpfga:stability}).
|
||
|
||
|
||
\section{todo - FIXME: remove}
|
||
\begin{verbatim}
|
||
***** Summary eher kurz
|
||
***** Outlook als subsection!
|
||
\end{verbatim}
|