545 lines
24 KiB
TeX
545 lines
24 KiB
TeX
\chapter{\label{summary}Conclusion}
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%** Summary.tex: What have you achieved, what have you presented in this
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% document. What are the highlights of your work.
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% It should conclude by a conclusion.
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Sum up what you have done and recapitulate your key findings.
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%\section{\label{conclusion:overall}Overall}
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\section{\label{conclusion:softwarenat64}Software based NAT64}
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\section{\label{conclusion:general}General}
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Many misleading
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\section{\label{conclusion:bmv2}BMV2}
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\section{\label{conclusion:P4}P4}
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checksumming a frequent problem and helper
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Many possibilities
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Protocol independent
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Easy architecture
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Limitations in
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if in action limitations
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Limits if in actions
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python2 only - unicode errors
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IPv6: NDP: not easy to parse, as unknown number of following fields
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No support for multiple LPM keys in a table, can be solved with
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ternary matching.
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switch cannot be used in actions
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if things don't work, often a checksum problem.
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if frame checksum, then length of packet is broken
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\begin{verbatim}
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p4c --target bmv2 --arch v1model --std p4-16 "../p4src/static-mapping.p4" -o "/home/p4/master-thesis/p4src"
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../p4src/static-mapping.p4(366): error: Program is not supported by this target, because table MyIngress.v6_networks has multiple successors
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table v6_networks {
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^^^^^^^^^^^
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\end{verbatim}
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\begin{verbatim}
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ipaddress.ip_network("2001:db8:61::/64")
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IPv6Network(u'3230:3031:3a64:6238:3a36:313a:3a2f:3634/128')
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Fix:
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from __future__ import unicode_literals
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\end{verbatim}
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The tooling around P4 is still fragile, encountered many bugs
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in the development.\cite{schottelius:github1675}
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or missing features (\cite{schottelius:github745},
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\cite{theojepsen:_get})
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Hitting expression bug
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retrieving information from tables
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\begin{verbatim}
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Key and mask for matching destination is in table. We need this
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information in the action. However this information is not exposed, so
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we need to specify another parameter with the same information as in
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the key(s).
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Log from slack: (2019-03-14)
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nico [1:55 PM]
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If I use LPM for matching, can I easily get the network address from P4 or do I have to use a bitmask myself? In the latter case it is not exactly clear how to get the mask from the table
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Nate Foster [1:58 PM]
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You want to retrieve the address in the packet? In a table?
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And do you want to do the retrieving from the data plane or the control plane? (edited)
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nico [2:00 PM]
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If I have a match in a table that matches on LPM, it can be any IP address in a network
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For calculating the NAT64/NAT46 translation, I will need the base address, i.e. network address to do subtractions/additions
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So it is fully data plane, what I would like to do
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I'll commit sample code to show the use case more clearly
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https://gitlab.ethz.ch/nicosc/master-thesis/blob/master/p4src/static-mapping.p4#L73
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GitLab
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p4src/static-mapping.p4 · master · nicosc / master-thesis
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gitlab.ethz.ch
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So the action nat64_static() is used in the table v6_networks.
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In v6_networks I use a match on `hdr.ipv6.dst_addr: lpm;`
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What I would like to be able is to get the network address ; I can do that manually, if I have the mask
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I can also re-inject this parameter by another action argument, but I'd assume that I can somewhere read this out from the table / match
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Nate Foster [2:15 PM]
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To make sure I understand, in the data plane, you want to retrieve the address in the lpm pattern? (edited)
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nico [2:16 PM]
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I want to retrieve the key
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Nate Foster [2:16 PM]
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Wait. The value `hdr.ipv6.dst_addr` is the thing used in the match.
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So you have that.
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What you don’t have is the IPv6 address and mask put into the table by the control plane.
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I assume you want the latter, right?
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nico [2:17 PM]
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For example, if my matching key is 2001:db8::/32 and the real address is 2001:db8::f00, then I would like to retrieve 2001:db8:: and 32 from the table
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exactly :slightly_smiling_face:
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I can "fix" this by adding another argument, but it feels somewhat wrong to do that
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Because the table already knows this information
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Nate Foster [2:26 PM]
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I can’t think of a way other than the action parameter hack.
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nico [2:26 PM]
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Oh, ok
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Is it because the information is "lost in hardware"?
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Nate Foster [2:31 PM]
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No you’re right that most implementations have the value in memory. And one can imagine a different table API that allowed one to retrieve it in the data plane.
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But unless I am missing something obvious, P4 hides it…
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\end{verbatim}
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no meta information
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\begin{verbatim}
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Is there any meta information for "from which table was the action
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called" available? My use case is having a debug action that sends
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packets to the controller and I use it as a default_action in various
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tables; however know I don't know anymore from which table the action
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was called. Is there any kind of meta information which table called
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me available?
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I could work around this by using if(! .. .hit) { my_action(table_id)
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}, but it would not work with using default_action = ...
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\end{verbatim}
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type definitions separate
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Code sharing (controller, switch)
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\begin{verbatim}
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*** DONE Synchronisation with the controller
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- Double data type definition -> might differ
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- TYPE_CPU for ethernet
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- Port ingress offset (9 vs. 16 bit)
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\end{verbatim}
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No switch in actions, No conditional execution in actions
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P4os - reusable code
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\begin{verbatim}
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Not addressed so far: how to create re-usable code fragments that can
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be plugged in easily. There could be a hypothetical "P4OS" that
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manages code fragments. This might include, but not limited to
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downloading (signed?) source code, managing dependencies similar to
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Linux package management, handling updates, etc.
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\end{verbatim}
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idomatic problem: Security issue: not checking checksums before
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% ----------------------------------------------------------------------
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\section{\label{conclusion:netpfga}NetFGPA - all HERE}
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personal note here
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tested various kernels for table debugging
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MTU limitations: 1500 according to a private mail from Salvator Galea
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cambridge / uk
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long compile process
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error prone compile process
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many dependencies
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lpm not supported!
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Netpfga live,
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Vivado
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SDNET
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xx k lines of supporting code
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Vivado installation: silent errors, infinite loop, missing libncurses5
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82k lines of code that are interdependent
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Many non critical error messages on the way
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Zero exit fatal errors
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missing / spreaded documentation
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tcpdump on local nfX doesn't work -> can only debug on other endpoint
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First card: Writing tables fails
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hardware debug shows some errors
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but hardware debug on correct card also shows some error
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Debug ioctl errors when writing table entries
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Output all ports -> port mapping documented only in a testdata script
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hwtest: Execution fails due to missing djtgcfg
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no payload accessq
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Many workarounds
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Table size 63, table size 64,
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Table entries require arguments of all possible actions, not only used
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one.
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Compile time hours
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Silent errors
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Unclear errors: broken board
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Due to the very fragile nature of the build framework from the
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NetFPGA-Live repository,
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Renaming VARIABLES in the definition of
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Reproducibility:
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hours for finding right output ports
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packet size / annotation
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Needed to debug internal parsing errors
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3x rebooting to get card working with bitstream
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Variable renaming breaks the compile process
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\begin{verbatim}
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It seems I was really mistaken for the last weeks
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If I am not totally mistaken, the following is happening with the netpfga:
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I was testing sending and receiving packets on the same computer; so I sent a packet on nfX and expected an answer on nf0, which is how I wanted to verify that the card works
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So I ran tcpdump on nf0, send a packet with ping6 and scapy on nf{0,1,2,3} (edited)
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I have never seen the switch emitting ANY packet back with tcpdump
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Now with the card connected to another host, sending neighbor solicitation, I see duplicated packets on the other host - so it seems that it might have worked all the time, just that tcpdump on nfX on the host which contains the card does not show the packets
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\end{verbatim}
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debugging generated tcl code to debug impl1 error
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Cable problems:
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\begin{verbatim}
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[ 488.265148] ixgbe 0000:02:00.0: failed to initialize because an unsupported SFP+ module type was detected.
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[ 488.265157] ixgbe 0000:02:00.0: Reload the driver after installing a supported module.
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[ 488.265605] ixgbe 0000:02:00.0: removed PHC on enp2s0f0
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\end{verbatim}
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function syntax not supported, using defines instead
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4-6 MB logfiles for a compile process.
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confusing messages
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\begin{verbatim}
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WARNING: command 'get_user_parameter' will be removed in the 2015.3
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release, use 'get_user_parameters' instead
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\end{verbatim}
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critical non critical errors
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\begin{verbatim}
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CRITICAL WARNING: [BD 41-737] Cannot set the parameter TRANSLATION_MODE on /axi_interconnect_0. It is read-only.
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\end{verbatim}
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\begin{verbatim}
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- step9 (sume simulation, the longest step) in the process calls
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"config_writes.py"
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- config_writes.py fails with a syntax error, as it is incomplete
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python code
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- config_writes.py and config_writes.sh are generated by
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gen_config_writes.py
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- gen_config_writes.py reads config_writes.txt
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- config_writes.txt is created in step 5 (sdnet simulation)
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- step 5 consists of running xsc, xelab and xsim
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- xsim (re-)generates config_writes.txt according to a watch ls -l
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on the file: ${XILINX_VIVADO}/bin/xsim --runall
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SimpleSumeSwitch_tb#work.glbl
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- it seems (by grep -r) that ./Testbench/SimpleSumeSwitch_tb.sv is
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responsible for writing config_writes.txt
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- It seems that the "task" "SV_write_control" inside that file is
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responsible for writing the content, which in turn uses
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axi4_lite_master_write_request_control
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\end{verbatim}
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\begin{verbatim}
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- Cannot easily run P4 on notebook - changes to the system very
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invasive
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- Varous compiler bugs/limitations
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- Very very deep rabbithole problems
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- Hanging/sleeping issue -- unclear whether it does something or
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not
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- Open impl_1 error with unclear reason
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- logfiles referenced that don't exist
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Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log
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nico@nsg-System:~/master-thesis/netpfga/log$ ls -alh /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log
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ls: cannot access '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log': No such file or directory
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- even "short" compile runs taking 30m+
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control_sub_m02_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log
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nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ less /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log: No such file or directory
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- Wrong warnings: using 2018.2, getting warnings about things
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removed in 2015.3
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WARNING: command 'get_user_parameter' will be removed in the 2015.3
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release, use 'get_user_parameters' instead
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- A script/makefile generates a python script that generates a shell
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script and later then a python script. If there is a mistake in
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generating the first python script (syntax ok, but content is
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not correct) then a much later stage of the compile process will
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fail due to a syntax error in the third generated
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script. However that syntax error is not fatal in the build
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process and thus can only be seen with careful analysis of the
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logfile, which is around 700 KiB or 10k lines per compile
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process and contains 328 lines matching "error" and
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"warning".
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Most of the error and warning messages seem to be non-critical
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(even if saying they are). Then there are a variety of INFO
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messages that actually constitute ERROR messages, but are not
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flagged as such nor do they cause the build process to abort.
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\end{verbatim}
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LPM tables don't work
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match type exact - table must be at least 64 in size
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multiple reboots sometimes required for flashing
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Damaged, enlarged packets
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\begin{verbatim}
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** The NetPFGA saga
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Problems encountered:
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- The logfile for a compile run is 10k+ lines
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- Many logged errors can actually be ignored (?) like:
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ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
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ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_DATA on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:219]
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ERROR: [VRFC 10-426] cannot find port tuple_out_sume_metadata_VALID on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:218]
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ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_DATA on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:185]
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ERROR: [VRFC 10-426] cannot find port tuple_in_sume_metadata_VALID on this module [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/wrapper/nf_sume_sdnet.v:184]
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ERROR: [VRFC 10-2063] Module <S_RESETTER_line> not found while processing module instance <S_RESET_clk_line> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/Simp
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leSumeSwitch/SimpleSumeSwitch.v:332]
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ERROR: [VRFC 10-2063] Module <S_RESETTER_lookup> not found while processing module instance <S_RESET_clk_lookup> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/
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SimpleSumeSwitch/SimpleSumeSwitch.v:343]
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ERROR: [VRFC 10-2063] Module <S_RESETTER_control> not found while processing module instance <S_RESET_clk_control> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_i
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p/SimpleSumeSwitch/SimpleSumeSwitch.v:354]
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ERROR: [VRFC 10-2063] Module <TopParser_t> not found while processing module instance <TopParser> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeSwitc
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h/SimpleSumeSwitch.v:436]
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ERROR: [VRFC 10-2063] Module <TopPipe_lvl_t> not found while processing module instance <TopPipe_lvl> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeS
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witch/SimpleSumeSwitch.v:474]
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ERROR: [VRFC 10-2063] Module <dummy_table_for_netpfga_t> not found while processing module instance <dummy_table_for_netpfga> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_s
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ume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v:502]
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ERROR: [VRFC 10-2063] Module <TopPipe_lvl_0_t> not found while processing module instance <TopPipe_lvl_0> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleS
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umeSwitch/SimpleSumeSwitch.v:533]
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ERROR: [VRFC 10-2063] Module <TopDeparser_t> not found while processing module instance <TopDeparser> [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/nf_sume_sdnet_ip/nf_sume_sdnet_ip/SimpleSumeS
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witch/SimpleSumeSwitch.v:561]
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# launch_simulation -simset sim_1 -mode behavioral
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INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
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CRITICAL WARNING: [BD 41-1356] Address block </M04_AXI/Reg> is not mapped into </S00_AXI>. Please use Address Editor to either map or exclude it.
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CRITICAL WARNING: [BD 41-1356] Address block </M05_AXI/Reg> is not mapped into </S00_AXI>. Please use Address Editor to either map or exclude it.
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WARNING: [VRFC 10-756] identifier state is used before its declaration [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:93]
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WARNING: [VRFC 10-756] identifier ready_count is used before its declaration [/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/ip/axis_sim_record_ip0/hdl/axis_sim_record.v:94]
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INFO: [#UNDEF] Sorry, too many errors..
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ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
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INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
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INFO: [USF-XSim-99] Step results log file:'/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log'
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ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' file for more information.
|
||
|
||
nico@nsg-System:~/master-thesis$ find . -name elaborate.log
|
||
nico@nsg-System:~/master-thesis$ find ~ -name elaborate.log
|
||
nico@nsg-System:~/master-thesis$
|
||
|
||
- Scripts that "fail" (generate wrong data) do exit 0 ->
|
||
There is no easy / reliable error detection
|
||
- Writing tables resulted in ioctl errors
|
||
- Hardware test: unclear if first board was/is broken or not,
|
||
BUT: second board in different computer allows writing tables
|
||
- Many scripts depend on each other in later stages, without clear
|
||
dependencies
|
||
- There is basically no documentation for someone who "just wants to
|
||
compile from P4 to netpfga" or A LOT of documentation (if vivado,
|
||
vhld, sdnet documentation is counted)
|
||
- Very high complexity in toolchain, scripts that are generated
|
||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default
|
||
+ make
|
||
rm -f config_writes.py*
|
||
rm -f *.pyc
|
||
|
||
nico@nsg-System:~$ cat /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py
|
||
|
||
from NFTest import *
|
||
|
||
NUM_WRITES = 4
|
||
|
||
def config_tables():
|
||
nftest_regwrite(0x44020050, 0x22222208)
|
||
nftest_regwrite(0x44020054, 0x00000822)
|
||
nftest_regwrite(0x44020080, 0x00000201)
|
||
nftest_regwrite(0x44020040, 0x00000001)
|
||
nico@nsg-System:~$ cat /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.sh
|
||
#!/bin/bash
|
||
|
||
${SUME_SDNET}/sw/sume/rwaxi -a 0x44020050 -w 0x22222208
|
||
${SUME_SDNET}/sw/sume/rwaxi -a 0x44020054 -w 0x00000822
|
||
${SUME_SDNET}/sw/sume/rwaxi -a 0x44020080 -w 0x00000201
|
||
${SUME_SDNET}/sw/sume/rwaxi -a 0x44020040 -w 0x00000001
|
||
nico@nsg-System:~$
|
||
|
||
|
||
- Misleading errors like
|
||
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log' file for more information.
|
||
nico@nsg-System:~/master-thesis/netpfga$ ls /home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log
|
||
ls: cannot access '/home/nico/master-thesis/netpfga/minip4/simple_sume_switch/hw/project/simple_sume_switch.sim/sim_1/behav/xsim/elaborate.log': No such file or directory
|
||
|
||
- not using raise() and hiding source of errors (_hexify)
|
||
|
||
- sometimes flashing fails:
|
||
|
||
#+BEGIN_CENTER
|
||
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles$ sudo bash -c ". $HOME/master-thesis/netpfga/bashinit && $(pwd -P)/program_switch.sh"
|
||
++ which vivado
|
||
+ xilinx_tool_path=/opt/Xilinx/Vivado/2018.2/bin/vivado
|
||
+ bitimage=minip4.bit
|
||
+ configWrites=config_writes.sh
|
||
+ '[' -z minip4.bit ']'
|
||
+ '[' -z config_writes.sh ']'
|
||
+ '[' /opt/Xilinx/Vivado/2018.2/bin/vivado == '' ']'
|
||
+ rmmod sume_riffa
|
||
+ xsct /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl -tclargs minip4.bit
|
||
rlwrap: warning: your $TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems.
|
||
RUN loading image file.
|
||
minip4.bit
|
||
100% 19MB 1.7MB/s 00:11
|
||
fpga configuration failed. DONE PIN is not HIGH
|
||
invoked from within
|
||
"::tcf::eval -progress ::xsdb::print_progress {::tcf::cache_enter tcfchan#0 {tcf_cache_eval {process_tcf_actions_cache_client ::tcfclient#0::arg}}}"
|
||
(procedure "::tcf::cache_eval_with_progress" line 2)
|
||
invoked from within
|
||
"::tcf::cache_eval_with_progress [dict get $arg chan] [list process_tcf_actions_cache_client $argvar] $progress"
|
||
(procedure "process_tcf_actions" line 1)
|
||
invoked from within
|
||
"process_tcf_actions $arg ::xsdb::print_progress"
|
||
(procedure "fpga" line 430)
|
||
invoked from within
|
||
"fpga -f $bitimage"
|
||
(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl" line 33)
|
||
|
||
+ bash /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/pci_rescan_run.sh
|
||
Check programming FPGA or Reboot machine !
|
||
+ rmmod sume_riffa
|
||
rmmod: ERROR: Module sume_riffa is not currently loaded
|
||
+ modprobe sume_riffa
|
||
+ ifconfig nf0 up
|
||
nf0: ERROR while getting interface flags: No such device
|
||
+ ifconfig nf1 up
|
||
nf1: ERROR while getting interface flags: No such device
|
||
+ ifconfig nf2 up
|
||
nf2: ERROR while getting interface flags: No such device
|
||
+ ifconfig nf3 up
|
||
nf3: ERROR while getting interface flags: No such device
|
||
+ bash config_writes.sh
|
||
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles$
|
||
|
||
#+END_CENTER
|
||
|
||
\end{verbatim}
|
||
|
||
\section{\label{conclusion:realworld}Real world applications}
|
||
Can be deployed using the netpfga. Or Barefoot or Arista.
|
||
|
||
|
||
|
||
\section{\label{conclusion:outlook}Outlook}
|
||
|
||
%** Outlook.tex: What needs to be done further, what is planed
|
||
%
|
||
What are the consequences of your work for future work?
|
||
|
||
Different HW
|
||
|
||
Speed only limited to line speed. Could be running at 100 Gbit/s
|
||
without modifications.
|
||
|
||
PMTU
|
||
handling error cases
|
||
|
||
Our algorithm uses the IPv4-Compatible IPv6 Address\cite{rfc4291} to
|
||
embed IPv4 addresses. However RFC6052\cite{rfc6052} defines different
|
||
embeddings depending on the prefix size. A future version should
|
||
support these schemes to be compatible to other implementations.
|
||
|
||
No fragmentation
|
||
No address / mac learning
|
||
|
||
**** No DNS64
|
||
has already been solved in a different domain - could even do
|
||
transparent / in network modification
|
||
**** Incomplete NDP
|
||
Very limited option support
|
||
|
||
No resolution of hardware addresses
|
||
|
||
\section{\label{conclusion:closing}Closing words (NAME?)}
|
||
While the port to NetPFGA was significantly more effort then expected,
|
||
the learnings of the different layers were very much appreciated / liked
|
||
|
||
It was a
|
||
|
||
\section{todo - FIXME: remove}
|
||
\begin{verbatim}
|
||
***** Summary eher kurz
|
||
***** Outlook als subsection!
|
||
\end{verbatim}
|