419 lines
18 KiB
Coq
419 lines
18 KiB
Coq
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`timescale 1ns / 1ps
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//-
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// Copyright (c) 2015 Noa Zilberman
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// All rights reserved.
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//
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// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
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// under National Science Foundation under Grant No. CNS-0855268,
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// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
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// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
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// as part of the DARPA MRC research programme.
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//
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// File:
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// nf_datapath.v
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//
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// Module:
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// nf_datapath
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//
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// Author: Noa Zilberman
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//
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// Description:
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// NetFPGA user data path wrapper, wrapping input arbiter, output port lookup and output queues
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//
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//
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// @NETFPGA_LICENSE_HEADER_START@
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//
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// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
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// license agreements. See the NOTICE file distributed with this work for
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// additional information regarding copyright ownership. NetFPGA licenses this
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// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
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// "License"); you may not use this file except in compliance with the
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// License. You may obtain a copy of the License at:
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//
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// http://www.netfpga-cic.org
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//
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// Unless required by applicable law or agreed to in writing, Work distributed
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// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// @NETFPGA_LICENSE_HEADER_END@
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//
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module nf_datapath #(
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//Slave AXI parameters
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parameter C_S_AXI_DATA_WIDTH = 32,
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parameter C_S_AXI_ADDR_WIDTH = 32,
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parameter C_BASEADDR = 32'h00000000,
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// Master AXI Stream Data Width
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parameter C_M_AXIS_DATA_WIDTH=256,
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parameter C_S_AXIS_DATA_WIDTH=256,
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parameter C_M_AXIS_TUSER_WIDTH=128,
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parameter C_S_AXIS_TUSER_WIDTH=128,
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parameter NUM_QUEUES=5,
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parameter DIGEST_WIDTH =80
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)
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(
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//Datapath clock
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input axis_aclk,
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input axis_resetn,
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//Registers clock
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input axi_aclk,
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input axi_resetn,
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// Slave AXI Ports
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input [C_S_AXI_ADDR_WIDTH-1 : 0] S0_AXI_AWADDR,
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input S0_AXI_AWVALID,
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input [C_S_AXI_DATA_WIDTH-1 : 0] S0_AXI_WDATA,
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input [C_S_AXI_DATA_WIDTH/8-1 : 0] S0_AXI_WSTRB,
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input S0_AXI_WVALID,
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input S0_AXI_BREADY,
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input [C_S_AXI_ADDR_WIDTH-1 : 0] S0_AXI_ARADDR,
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input S0_AXI_ARVALID,
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input S0_AXI_RREADY,
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output S0_AXI_ARREADY,
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output [C_S_AXI_DATA_WIDTH-1 : 0] S0_AXI_RDATA,
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output [1 : 0] S0_AXI_RRESP,
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output S0_AXI_RVALID,
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output S0_AXI_WREADY,
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output [1 :0] S0_AXI_BRESP,
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output S0_AXI_BVALID,
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output S0_AXI_AWREADY,
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input [C_S_AXI_ADDR_WIDTH-1 : 0] S1_AXI_AWADDR,
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input S1_AXI_AWVALID,
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input [C_S_AXI_DATA_WIDTH-1 : 0] S1_AXI_WDATA,
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input [C_S_AXI_DATA_WIDTH/8-1 : 0] S1_AXI_WSTRB,
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input S1_AXI_WVALID,
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input S1_AXI_BREADY,
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input [C_S_AXI_ADDR_WIDTH-1 : 0] S1_AXI_ARADDR,
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input S1_AXI_ARVALID,
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input S1_AXI_RREADY,
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output S1_AXI_ARREADY,
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output [C_S_AXI_DATA_WIDTH-1 : 0] S1_AXI_RDATA,
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output [1 : 0] S1_AXI_RRESP,
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output S1_AXI_RVALID,
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output S1_AXI_WREADY,
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output [1 :0] S1_AXI_BRESP,
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output S1_AXI_BVALID,
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output S1_AXI_AWREADY,
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input [C_S_AXI_ADDR_WIDTH-1 : 0] S2_AXI_AWADDR,
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input S2_AXI_AWVALID,
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input [C_S_AXI_DATA_WIDTH-1 : 0] S2_AXI_WDATA,
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input [C_S_AXI_DATA_WIDTH/8-1 : 0] S2_AXI_WSTRB,
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input S2_AXI_WVALID,
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input S2_AXI_BREADY,
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input [C_S_AXI_ADDR_WIDTH-1 : 0] S2_AXI_ARADDR,
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input S2_AXI_ARVALID,
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input S2_AXI_RREADY,
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output S2_AXI_ARREADY,
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output [C_S_AXI_DATA_WIDTH-1 : 0] S2_AXI_RDATA,
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output [1 : 0] S2_AXI_RRESP,
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output S2_AXI_RVALID,
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output S2_AXI_WREADY,
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output [1 :0] S2_AXI_BRESP,
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output S2_AXI_BVALID,
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output S2_AXI_AWREADY,
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// Slave Stream Ports (interface from Rx queues)
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input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_0_tdata,
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input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_0_tkeep,
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input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_0_tuser,
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input s_axis_0_tvalid,
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output s_axis_0_tready,
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input s_axis_0_tlast,
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input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_1_tdata,
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input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_1_tkeep,
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input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_1_tuser,
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input s_axis_1_tvalid,
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output s_axis_1_tready,
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input s_axis_1_tlast,
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input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_2_tdata,
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input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_2_tkeep,
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input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_2_tuser,
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input s_axis_2_tvalid,
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output s_axis_2_tready,
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input s_axis_2_tlast,
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input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_3_tdata,
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input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_3_tkeep,
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input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_3_tuser,
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input s_axis_3_tvalid,
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output s_axis_3_tready,
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input s_axis_3_tlast,
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input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_4_tdata,
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input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_4_tkeep,
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input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_4_tuser,
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input s_axis_4_tvalid,
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output s_axis_4_tready,
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input s_axis_4_tlast,
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// Master Stream Ports (interface to TX queues)
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output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_0_tdata,
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output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_0_tkeep,
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output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_0_tuser,
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output m_axis_0_tvalid,
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input m_axis_0_tready,
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output m_axis_0_tlast,
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output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_1_tdata,
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output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_1_tkeep,
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output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_1_tuser,
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output m_axis_1_tvalid,
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input m_axis_1_tready,
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output m_axis_1_tlast,
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output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_2_tdata,
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output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_2_tkeep,
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output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_2_tuser,
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output m_axis_2_tvalid,
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input m_axis_2_tready,
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output m_axis_2_tlast,
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output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_3_tdata,
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output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_3_tkeep,
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output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_3_tuser,
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output m_axis_3_tvalid,
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input m_axis_3_tready,
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output m_axis_3_tlast,
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output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_4_tdata,
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output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_4_tkeep,
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output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_4_tuser,
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output m_axis_4_tvalid,
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input m_axis_4_tready,
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output m_axis_4_tlast
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);
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localparam C_AXIS_TUSER_DIGEST_WIDTH = 304;
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//internal connectivity
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(* mark_debug = "true" *) wire [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_opl_tdata;
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(* mark_debug = "true" *) wire [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_opl_tkeep;
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(* mark_debug = "true" *) wire [C_AXIS_TUSER_DIGEST_WIDTH-1:0] m_axis_opl_tuser;
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(* mark_debug = "true" *) wire m_axis_opl_tvalid;
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(* mark_debug = "true" *) wire m_axis_opl_tready;
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(* mark_debug = "true" *) wire m_axis_opl_tlast;
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(* mark_debug = "true" *) wire [C_M_AXIS_DATA_WIDTH - 1:0] s_axis_opl_tdata;
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(* mark_debug = "true" *) wire [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_opl_tkeep;
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(* mark_debug = "true" *) wire [C_M_AXIS_TUSER_WIDTH-1:0] s_axis_opl_tuser;
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(* mark_debug = "true" *) wire s_axis_opl_tvalid;
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(* mark_debug = "true" *) wire s_axis_opl_tready;
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(* mark_debug = "true" *) wire s_axis_opl_tlast;
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localparam Q_SIZE_WIDTH = 16;
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(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf0_q_size;
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(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf1_q_size;
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(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf2_q_size;
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(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf3_q_size;
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(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] dma_q_size;
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//Input Arbiter
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input_arbiter_ip
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input_arbiter_v1_0 (
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.axis_aclk(axis_aclk),
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.axis_resetn(axis_resetn),
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.m_axis_tdata (s_axis_opl_tdata),
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.m_axis_tkeep (s_axis_opl_tkeep),
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.m_axis_tuser (s_axis_opl_tuser),
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.m_axis_tvalid(s_axis_opl_tvalid),
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.m_axis_tready(s_axis_opl_tready),
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.m_axis_tlast (s_axis_opl_tlast),
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.s_axis_0_tdata (s_axis_0_tdata),
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.s_axis_0_tkeep (s_axis_0_tkeep),
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.s_axis_0_tuser (s_axis_0_tuser),
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.s_axis_0_tvalid(s_axis_0_tvalid),
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.s_axis_0_tready(s_axis_0_tready),
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.s_axis_0_tlast (s_axis_0_tlast),
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.s_axis_1_tdata (s_axis_1_tdata),
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.s_axis_1_tkeep (s_axis_1_tkeep),
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.s_axis_1_tuser (s_axis_1_tuser),
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.s_axis_1_tvalid(s_axis_1_tvalid),
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.s_axis_1_tready(s_axis_1_tready),
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.s_axis_1_tlast (s_axis_1_tlast),
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.s_axis_2_tdata (s_axis_2_tdata),
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.s_axis_2_tkeep (s_axis_2_tkeep),
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.s_axis_2_tuser (s_axis_2_tuser),
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.s_axis_2_tvalid(s_axis_2_tvalid),
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.s_axis_2_tready(s_axis_2_tready),
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.s_axis_2_tlast (s_axis_2_tlast),
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.s_axis_3_tdata (s_axis_3_tdata),
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.s_axis_3_tkeep (s_axis_3_tkeep),
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.s_axis_3_tuser (s_axis_3_tuser),
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.s_axis_3_tvalid(s_axis_3_tvalid),
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.s_axis_3_tready(s_axis_3_tready),
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.s_axis_3_tlast (s_axis_3_tlast),
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.s_axis_4_tdata (s_axis_4_tdata),
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.s_axis_4_tkeep (s_axis_4_tkeep),
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.s_axis_4_tuser (s_axis_4_tuser),
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.s_axis_4_tvalid(s_axis_4_tvalid),
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.s_axis_4_tready(s_axis_4_tready),
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.s_axis_4_tlast (s_axis_4_tlast),
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.S_AXI_AWADDR(S0_AXI_AWADDR),
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.S_AXI_AWVALID(S0_AXI_AWVALID),
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.S_AXI_WDATA(S0_AXI_WDATA),
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.S_AXI_WSTRB(S0_AXI_WSTRB),
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.S_AXI_WVALID(S0_AXI_WVALID),
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.S_AXI_BREADY(S0_AXI_BREADY),
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.S_AXI_ARADDR(S0_AXI_ARADDR),
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.S_AXI_ARVALID(S0_AXI_ARVALID),
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.S_AXI_RREADY(S0_AXI_RREADY),
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.S_AXI_ARREADY(S0_AXI_ARREADY),
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.S_AXI_RDATA(S0_AXI_RDATA),
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.S_AXI_RRESP(S0_AXI_RRESP),
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.S_AXI_RVALID(S0_AXI_RVALID),
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.S_AXI_WREADY(S0_AXI_WREADY),
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.S_AXI_BRESP(S0_AXI_BRESP),
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.S_AXI_BVALID(S0_AXI_BVALID),
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.S_AXI_AWREADY(S0_AXI_AWREADY),
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.S_AXI_ACLK (axi_aclk),
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.S_AXI_ARESETN(axi_resetn),
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.pkt_fwd()
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);
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// SUME SDNet Module
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nf_sume_sdnet_ip
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nf_sume_sdnet_wrapper_1 (
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.axis_aclk(axis_aclk),
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.axis_resetn(axis_resetn),
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.m_axis_tdata (m_axis_opl_tdata),
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.m_axis_tkeep (m_axis_opl_tkeep),
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.m_axis_tuser (m_axis_opl_tuser),
|
||
|
|
.m_axis_tvalid(m_axis_opl_tvalid),
|
||
|
|
.m_axis_tready(m_axis_opl_tready),
|
||
|
|
.m_axis_tlast (m_axis_opl_tlast),
|
||
|
|
.s_axis_tdata (s_axis_opl_tdata),
|
||
|
|
.s_axis_tkeep (s_axis_opl_tkeep),
|
||
|
|
.s_axis_tuser ({dma_q_size, nf3_q_size, nf2_q_size, nf1_q_size, nf0_q_size, s_axis_opl_tuser[C_M_AXIS_TUSER_WIDTH-DIGEST_WIDTH-1:0]}),
|
||
|
|
.s_axis_tvalid(s_axis_opl_tvalid),
|
||
|
|
.s_axis_tready(s_axis_opl_tready),
|
||
|
|
.s_axis_tlast (s_axis_opl_tlast),
|
||
|
|
|
||
|
|
.S_AXI_AWADDR(S1_AXI_AWADDR),
|
||
|
|
.S_AXI_AWVALID(S1_AXI_AWVALID),
|
||
|
|
.S_AXI_WDATA(S1_AXI_WDATA),
|
||
|
|
.S_AXI_WSTRB(S1_AXI_WSTRB),
|
||
|
|
.S_AXI_WVALID(S1_AXI_WVALID),
|
||
|
|
.S_AXI_BREADY(S1_AXI_BREADY),
|
||
|
|
.S_AXI_ARADDR(S1_AXI_ARADDR),
|
||
|
|
.S_AXI_ARVALID(S1_AXI_ARVALID),
|
||
|
|
.S_AXI_RREADY(S1_AXI_RREADY),
|
||
|
|
.S_AXI_ARREADY(S1_AXI_ARREADY),
|
||
|
|
.S_AXI_RDATA(S1_AXI_RDATA),
|
||
|
|
.S_AXI_RRESP(S1_AXI_RRESP),
|
||
|
|
.S_AXI_RVALID(S1_AXI_RVALID),
|
||
|
|
.S_AXI_WREADY(S1_AXI_WREADY),
|
||
|
|
.S_AXI_BRESP(S1_AXI_BRESP),
|
||
|
|
.S_AXI_BVALID(S1_AXI_BVALID),
|
||
|
|
.S_AXI_AWREADY(S1_AXI_AWREADY),
|
||
|
|
.S_AXI_ACLK (axi_aclk),
|
||
|
|
.S_AXI_ARESETN(axi_resetn)
|
||
|
|
|
||
|
|
);
|
||
|
|
|
||
|
|
|
||
|
|
(* mark_debug = "true" *) wire [C_S_AXI_DATA_WIDTH-1:0] bytes_dropped;
|
||
|
|
(* mark_debug = "true" *) wire [5-1:0] pkt_dropped;
|
||
|
|
|
||
|
|
// assign nf0_q_size = 'd12;
|
||
|
|
// assign nf1_q_size = 'd13;
|
||
|
|
// assign nf2_q_size = 'd14;
|
||
|
|
// assign nf3_q_size = 'd15;
|
||
|
|
// assign dma_q_size = 'd16;
|
||
|
|
|
||
|
|
//Output queues
|
||
|
|
sss_output_queues_ip
|
||
|
|
bram_output_queues_1 (
|
||
|
|
.axis_aclk(axis_aclk),
|
||
|
|
.axis_resetn(axis_resetn),
|
||
|
|
.s_axis_tdata (m_axis_opl_tdata),
|
||
|
|
.s_axis_tkeep (m_axis_opl_tkeep),
|
||
|
|
.s_axis_tuser (m_axis_opl_tuser),
|
||
|
|
.s_axis_tvalid (m_axis_opl_tvalid),
|
||
|
|
.s_axis_tready (m_axis_opl_tready),
|
||
|
|
.s_axis_tlast (m_axis_opl_tlast),
|
||
|
|
.m_axis_0_tdata (m_axis_0_tdata),
|
||
|
|
.m_axis_0_tkeep (m_axis_0_tkeep),
|
||
|
|
.m_axis_0_tuser (m_axis_0_tuser),
|
||
|
|
.m_axis_0_tvalid(m_axis_0_tvalid),
|
||
|
|
.m_axis_0_tready(m_axis_0_tready),
|
||
|
|
.m_axis_0_tlast (m_axis_0_tlast),
|
||
|
|
.m_axis_1_tdata (m_axis_1_tdata),
|
||
|
|
.m_axis_1_tkeep (m_axis_1_tkeep),
|
||
|
|
.m_axis_1_tuser (m_axis_1_tuser),
|
||
|
|
.m_axis_1_tvalid(m_axis_1_tvalid),
|
||
|
|
.m_axis_1_tready(m_axis_1_tready),
|
||
|
|
.m_axis_1_tlast (m_axis_1_tlast),
|
||
|
|
.m_axis_2_tdata (m_axis_2_tdata),
|
||
|
|
.m_axis_2_tkeep (m_axis_2_tkeep),
|
||
|
|
.m_axis_2_tuser (m_axis_2_tuser),
|
||
|
|
.m_axis_2_tvalid(m_axis_2_tvalid),
|
||
|
|
.m_axis_2_tready(m_axis_2_tready),
|
||
|
|
.m_axis_2_tlast (m_axis_2_tlast),
|
||
|
|
.m_axis_3_tdata (m_axis_3_tdata),
|
||
|
|
.m_axis_3_tkeep (m_axis_3_tkeep),
|
||
|
|
.m_axis_3_tuser (m_axis_3_tuser),
|
||
|
|
.m_axis_3_tvalid(m_axis_3_tvalid),
|
||
|
|
.m_axis_3_tready(m_axis_3_tready),
|
||
|
|
.m_axis_3_tlast (m_axis_3_tlast),
|
||
|
|
.m_axis_4_tdata (m_axis_4_tdata),
|
||
|
|
.m_axis_4_tkeep (m_axis_4_tkeep),
|
||
|
|
.m_axis_4_tuser (m_axis_4_tuser),
|
||
|
|
.m_axis_4_tvalid(m_axis_4_tvalid),
|
||
|
|
.m_axis_4_tready(m_axis_4_tready),
|
||
|
|
.m_axis_4_tlast (m_axis_4_tlast),
|
||
|
|
|
||
|
|
.nf0_q_size(nf0_q_size),
|
||
|
|
.nf1_q_size(nf1_q_size),
|
||
|
|
.nf2_q_size(nf2_q_size),
|
||
|
|
.nf3_q_size(nf3_q_size),
|
||
|
|
.dma_q_size(dma_q_size),
|
||
|
|
|
||
|
|
.bytes_stored(),
|
||
|
|
.pkt_stored(),
|
||
|
|
.bytes_removed_0(),
|
||
|
|
.bytes_removed_1(),
|
||
|
|
.bytes_removed_2(),
|
||
|
|
.bytes_removed_3(),
|
||
|
|
.bytes_removed_4(),
|
||
|
|
.pkt_removed_0(),
|
||
|
|
.pkt_removed_1(),
|
||
|
|
.pkt_removed_2(),
|
||
|
|
.pkt_removed_3(),
|
||
|
|
.pkt_removed_4(),
|
||
|
|
.bytes_dropped(bytes_dropped),
|
||
|
|
.pkt_dropped(pkt_dropped),
|
||
|
|
|
||
|
|
.S_AXI_AWADDR(S2_AXI_AWADDR),
|
||
|
|
.S_AXI_AWVALID(S2_AXI_AWVALID),
|
||
|
|
.S_AXI_WDATA(S2_AXI_WDATA),
|
||
|
|
.S_AXI_WSTRB(S2_AXI_WSTRB),
|
||
|
|
.S_AXI_WVALID(S2_AXI_WVALID),
|
||
|
|
.S_AXI_BREADY(S2_AXI_BREADY),
|
||
|
|
.S_AXI_ARADDR(S2_AXI_ARADDR),
|
||
|
|
.S_AXI_ARVALID(S2_AXI_ARVALID),
|
||
|
|
.S_AXI_RREADY(S2_AXI_RREADY),
|
||
|
|
.S_AXI_ARREADY(S2_AXI_ARREADY),
|
||
|
|
.S_AXI_RDATA(S2_AXI_RDATA),
|
||
|
|
.S_AXI_RRESP(S2_AXI_RRESP),
|
||
|
|
.S_AXI_RVALID(S2_AXI_RVALID),
|
||
|
|
.S_AXI_WREADY(S2_AXI_WREADY),
|
||
|
|
.S_AXI_BRESP(S2_AXI_BRESP),
|
||
|
|
.S_AXI_BVALID(S2_AXI_BVALID),
|
||
|
|
.S_AXI_AWREADY(S2_AXI_AWREADY),
|
||
|
|
.S_AXI_ACLK (axi_aclk),
|
||
|
|
.S_AXI_ARESETN(axi_resetn)
|
||
|
|
);
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|